NSF Award
1237813
Objective<br/>The objective of this project is to conduct an international series of four face-to-face workshops<br/>to assess quantitatively the potential and status of four topics related to research on nanoelectronics<br/>devices and materials. The topics are: Emerging Research Memory Devices, Emerging Research<br/>Logic Devices, Emerging Research Architectures, and Emerging Research Materials critical for<br/>the realization of specific nanoelectronics devices. Participants and contributors to these<br/>workshops will include academic and industrial domain experts. The outputs of these workshops<br/>will guide and input preparation of the 2013 International Technology Roadmap for Semiconductors<br/>chapters on Emerging Research Devices and Emerging Research Materials. This grant will<br/>be used to pay partial travel expenses for some presenters, particularly academics, requesting<br/>travel assistance.<br/>The workshops series will focus on the relationship between the Semiconductor Industry as<br/>it endeavors to continue to advance semiconductor technology and the work of the National<br/>Nanotechnology Initiative (NNI) research community. One purpose of these meetings is to evaluate<br/>the potential and status of each specific nanotechnology entry identified by the ITRS ERD/ERM<br/>Working Groups as having potential to enable a new paradigm for information processing. Another<br/>purpose is to identify research opportunities that, if addressed, will benefit the Semiconductor<br/>Industry and fall within the scope of the NNI research agenda. Presenters will be provided<br/>with a list of questions that are intended to stimulate discussions during the workshops.<br/>Each workshop will be documented by a report described below.<br/><br/>Intellectual Merit<br/>In bringing together leading academic and industrial scientists to discuss, debate and reach<br/>consensus on the potential performance and key scientific challenges related to several emerging<br/>research memory and logic device technologies, these workshops will provide an excellent forum<br/>for intellectual pursuit and discernment of important/limiting scientific issues related to<br/>approaches to information processing. The intellectual merit of these workshops is illustrated<br/>by way of example.<br/>In the first example, the physics of operation and extreme scaling projections are not well<br/>understood for ?select devices? required for use in nanoscale memory arrays. These select<br/>devices are needed to employ a new class of non-volatile memory cells, called resistive random<br/>access memory (ReRAM),that may replace NAND flash for technology generations beyond the 16nm<br/>technology node. Generally speaking, a memory cell in an array can be viewed as being composed<br/>of two fundamental components: a ?storage node?, which is usually characterized by the physics<br/>of operation of the particular memory device used, and a ?selector?. The selector is a device<br/>which allows a given memory cell in an array to be singularly addressed for read or write<br/>operation without addressing its nearest neighbor cells. It is a non-linear element, which<br/>can operate as a switch, such as a diode-type, or as a resistive-switch-type structure. The<br/>latter category includes novel concepts such as Mott switches, threshold switches, and mixed<br/>ionic electronic conduction switches. Understanding the dominant physics related to their<br/>non-linear I-V characteristics is essential to employing these select devices in a highly<br/>dense non-volatile ReRAM crossbar architecture. It should be noted that for several advanced<br/>concepts of ReRAM, the storage node in principle can be scaled down below 10 nm, and the memory<br/>density will be limited by a somewhat larger conventional three-terminal select device. Thus<br/>the select device represents a serious bottleneck for scaling a ReRAM memory cell to 16 nm<br/>and beyond. Application of these new non-volatile memory devices to a crossbar memory structure<br/>will enable a paradigm shift to a new storage class memory (SCM) off-chip memory architecture<br/>discussed below.<br/>Another example, related to logic, is a family of new nanoelectronic low subthreshold-swing<br/>devices: e.g., negative Cg devices. These devices offer the attractive possibility of performing<br/>high speed logic while dissipating much lower power compared to a conventional MOSFET. The<br/>circuit design and the academic research communities have a expressed a strong interest for<br/>the ERD Technical Working Group to explore the physics of operation of these devices and the<br/>circuit design space in which they can operate in order to better understand their potential<br/>performance. This information will provide important input to these communities regarding<br/>their accelerating development of low-power electronics.<br/><br/>Broader Impact<br/>By carefully assessing the potential performance and scientific/technological challenges for<br/>each new memory select device and of new low-power logic devices, as well as emerging architectures,<br/>these workshops will provide important documented inputs to the research community as they<br/>pursue their exploration of many emerging research devices.<br/>One venue being initiated to obtain broad dissemination of this information is the editing<br/>and publication of a comprehensive book on nanoelectronics entitled ?Emerging Nanoelectronic<br/>Devices?. A proposal is under review by a major publisher who has expressed considerable interest.<br/>Furthermore, the educational value and planning impact of these workshops on the international<br/>research community are quite substantial. Several universities (e.g., Stanford, U. Minnesota,<br/>U. Tokyo,?) use the ITRS chapters on Emerging Research Devices and Emerging Research Materials<br/>resulting from these workshops as texts in their Nanoelectronics courses. Also several international<br/>research funding agencies (e.g., SRC, NSF, and NIST Nanoelectronics Research Initiative, the<br/>EU Framework Program 8, ?) use the material in these chapters as inputs to their decisions<br/>on research directions in their Nanoelectronics research programs.
