Patent Application
20090295498
1. Technical Field
The present invention relates to printed circuit boards (PCBs) and more particularly to improving electrical performance of PCBs with plated-through-holes (PTH) for connections among layers.
2. Description of the Related Art
Electronic packaging has become a bottle neck that limits electrical performance of both digital and analog systems. With the ever increasing operating speed/frequency or decrease in signal propagating wavelength, the effects of small features, which were negligible in the past, are now becoming critical and even detrimental to signal integrity. One of the most significant examples is the vertical interconnects used in printed circuit boards (PCBs), also known as vias, which disturb electromagnetic wave propagation and therefore introduce transmission and reflection losses.
Further, when plated through holes (PTH) are used as in today's prevalent PCB technology and signal traces are connected intermittently, the excessive via-stub (section below signal layer) may introduce parasitic LC resonances and result in detrimental losses in the multi-GHz frequency range. This jeopardizes signal integrity of such systems as servers, routers, etc. As a result, various approaches have been pursued to mitigate the negative effects of via stubs, including back-drill (remove via stubs from the bottom side of PCB) and build-up technologies for blind vias, etc. However, back-drill not only increases cost but also affects mechanical stability of the board, and blind vias require a future technology and will result in much higher manufacturing costs.
Multi-layer printed circuit boards (PCBs) are widely used in electrical systems, and often include metal lines and plated-through-hole (PTH) vias for signal and power/ground interconnections. PTHs are often employed in connecting to transmission lines in the PCB structure.
Referring to
Since sections of via 3 below transmission lines 6 are not on the path of signal propagation, this portion of the via is usually called a “via stub” 15. The use of PTH vias tends to introduce excessive via sections or via stubs.
The length of a via stub is determined by a layer that the connected transmission line is located on. The parasitic capacitance and inductance due to these via stubs 15 results in LC resonances, whose frequencies vary with stub lengths. These LC resonances significantly increase insertion and reflection losses, and therefore become a main limiting factor for high-speed and multi-layer PCB applications.
Methods and apparatuses disclosed herein utilize surface-mount or integral shunt resistors attached to the external pads of a signal-via and ground-via on the stub side or at an internal level close to the end of a via stub, so that a Q-factor of such resonances is dramatically reduced, and therefore relatively “flat” transmission response is achieved in an extended frequency range.
Reflection loss may also be reduced significantly at the resonance frequency. A resonance extinction resistor virtually converts a “non-working” link into a performance link without changing the PCB design and technology.
An apparatus includes a multi-layer printed circuit board having a first through-hole via for a signal connection and a second through hole via for power/ground connections. The printed circuit includes a transmission line connected to at least one through-hole via. A resistor is connected between the first and second through-hole vias to eliminate a resonance notch and achieve a flat frequency response for insertion loss when an integrated circuit chip is connected to the through-hole vias in operation.
These and other objects, features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
The disclosure will provide details in the following description of preferred embodiments with reference to the following figures wherein:
Exemplary embodiments of the present invention extinguish deep resonance notches due to via-stub LC resonance, so that both insertion loss and reflection may be reduced significantly, and electrical performance is improved. In one implementation, an extinction resistor is employed, which helps eliminate the resonance notch and achieve a desirable flat frequency response.
One application of such resonance extinction resistors employs surface-mount or integral resistors. In the case of surface-mount resistors, proper size and resistance may be used, and the resistor may be directly soldered onto existing external pads of a PCB, which guarantees backward compatibility.
As an example, in a via field of 1 mm pitch, which is common in existing packaging technologies, 0402 surface-mount resistors may be applied to a signal pad and an adjacent power/ground pad at the via-stub side (normally bottom side) without any modifications. Otherwise, additional solder pads may be added at the design stage to receive the resonance extinction resistors, or other size/type of resistors may be used to match a specific via pitch/pattern. An alternative is to use integrated internal resistors at a level that is close to the end of a via-stub. These resistors may be connected to signal vias at one end and power/ground planes at the other.
The assembly as described herein includes PCBs which may include one or more integrated circuit chips. The PCB design may be created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate PCBs or populated PCB assemblies or the photolithographic masks used to fabricate these items, the designer transmits the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer or board (and/or the layers thereon) to be etched or otherwise processed.
The resulting PCB can be distributed by the fabricator as a single PCB or in a packaged form with chips. In the latter case an integrated circuit chip or chips are mounted in a single chip package (such as a plastic carrier, with leads that are affixed to the PCB or other higher level carrier by joints) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips and/or PCBs, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
Referring now to the drawings in which like numerals represent the same or similar elements and initially to
The resonance extinction resistor 26 is directly soldered onto external pads 27 and 28 of via 23 and via 25 on the bottom side of the printed circuit board 24. The proper size surface mount resistor should be employed to match the pitch of via 23 and via 25. Vias 23 and 25 may include plated-through-holes (PTH).
Referring to
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An integrated resonance extinction resistor 66 is fabricated on an internal layer close the bottom side of printed circuit board 64, and connects via 63 to a power/ground plane on the same layer. In this embodiment, the resistor 66 may be part of the PCB 64 design or applied during the fabrication of the assembly (e.g., attaching layers of printed circuit boards together).
Referring to
As an example, for a 24-layer and 4.2 mm thick board, a via stub (3.9 mm long) may introduce a resonance at approximately 6.2 GHz. At this resonance frequency, insertion loss is as high as −30 dB, and reflection loss is −0.46 dB or 97.5% energy is reflected. For a system link that includes such via stubs, operating below 3 GHz requires carefully constructed designs, and operating above 3 GHz is almost impracticable. Further analysis reveals that sub-resonances occur at even lower frequency when such via-stubs are cascaded with low-loss transmission lines, e.g., inter-via resonances.
By applying a resonance extinction resistor, e.g. 50 ohm, insertion loss is lowered to −5 dB and reflection loss to −10 dB, a deterministic improvement for high-speed links. Similar results were also obtained in hardware measurements as will be described below. The selection of the resonance extinction resistance should depend on resonance frequency as well as frequencies of interest. The outcome can be either uniform transmission or minimized losses within certain frequency range.
Properly sized surface-mount resistors may be directly soldered onto existing external pads at the via stub ends, which offers backward compatibility. As an example, in a via field of 1 mm pitch, which is very common in existing packaging technologies, 0402 surface-mount chip resistors may be used without any modifications. Otherwise, additional solder pads may be added at the design stage to receive the resonance extinction resistors. An alternative is to employ integrated internal resistors at a level that close to the end of a via stub.
Referring to
Having described preferred embodiments of a device and method of via-stub resonance extinction (which are intended to be illustrative and not limiting), it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments disclosed which are within the scope and spirit of the invention as outlined by the appended claims. Having thus described aspects of the invention, with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.
This application is a Divisional application of co-pending U.S. patent application Ser. No. 11/325,794 filed on Jan. 5, 2006, incorporated herein by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 11325794 | Jan 2006 | US |
| Child | 12543854 | US |
