Patent Application
20190157160
Aspects of the present disclosure relate generally to semiconductor transistors and, more particularly, to minimizing punch-through leakage current in bulk Fin Field-Effect Transistors (FinFETs).
Fin Field-Effect Transistor (FinFET) devices have been developed to replace conventional planar bulk Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) in advanced Complementary Metal-Oxide-Semiconductor (CMOS) technology due to their improved short-channel effect immunity. A problem with bulk FinFET devices, however, is that a leakage path from source to drain exists through a portion of the fin lying below the channel. The leakage of current from source to drain through the lower (un-gated) part of the fin, commonly known as punch-through leakage, causes an undesirable increase of static power consumption. One known solution is implanting a punch-through-stopper (PTS) dopant in a portion of the fin directly below the channel. However, the impurities doped by the punch-through-stopper (PTS) implantation may diffuse into the channel region, increasing the variability due to random dopant fluctuation (RDF) and lowering the carrier mobility of the channel region. Thus, there continues to be a need for a solution for punch-through leakage.
The following presents a simplified summary of one or more embodiments to provide a basic understanding of such embodiments. This summary is not an extensive overview of all contemplated embodiments, and is intended to neither identify key or critical elements of all embodiments nor delineate the scope of any or all embodiments. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description that is presented later.
A method according to one aspect is described. The method may include providing a semiconductor substrate including a bulk semiconductor material, forming a plurality of fins from the bulk semiconductor material, forming shallow trench isolation (STI) trenches between the plurality of fins, forming a hardmask around the plurality of fins, forming a plurality of spacers on sidewalls of the plurality of fins protecting the sidewalls and exposing bottom portions of the fins where isolation is formed, and selectively etching and oxidizing the exposed bottom portions of the fins.
A semiconductor device according to one aspect is described. The semiconductor device may include a plurality of fins formed on a semiconductor substrate including a bulk semiconductor material, a plurality of STI trenches formed between the plurality of fins, a hardmask formed around the plurality of fins, and a plurality of fin bottoms formed below the plurality of fins.
These and other aspects of the invention will become more fully understood upon a review of the detailed description, which follows. Other aspects, features, and embodiments of the invention will become apparent to those of ordinary skill in the art, upon reviewing the following description of specific, exemplary embodiments of the invention in conjunction with the accompanying figures.
The detailed description set forth below, in connection with the appended drawings, is intended as a description of various configurations and is not intended to represent the only configurations in which the concepts described herein may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to simplify explanation and avoid obscuring such concepts.
Next, a hardmask 310 is then formed around fins 306 as shown in
Within the present disclosure, the word “exemplary” is used to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term “aspects” does not require that all aspects of the disclosure include the discussed feature, advantage or mode of operation. The term “coupled” is used herein to refer to the direct or indirect coupling between two objects. For example, if object A physically touches object B, and object B touches object C, then objects A and C may still be considered coupled to one another—even if they do not directly physically touch each other. For instance, a first die may be coupled to a second die in a package even though the first die is never directly physically in contact with the second die.
One or more of the components, steps, features and/or functions illustrated in the figures may be rearranged and/or combined into a single component, step, feature or function or embodied in several components, steps, or functions. Additional elements, components, steps, and/or functions may also be added without departing from novel features disclosed herein. The apparatus, devices, and/or components illustrated in the figures may be configured to perform one or more of the methods, features, or steps described herein. The novel algorithms described herein may also be efficiently implemented in software and/or embedded in hardware.
It is to be understood that the specific order or hierarchy of steps in the methods disclosed is an illustration of exemplary processes. Based upon design preferences, it is understood that the specific order or hierarchy of steps in the methods may be rearranged. The accompanying method claims present elements of the various steps in a sample order, and are not meant to be limited to the specific order or hierarchy presented unless specifically recited therein.
The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but are to be accorded the full scope consistent with the language of the claims, wherein reference to an element in the singular is not intended to mean “one and only one” unless specifically so stated, but rather “one or more.” Unless specifically stated otherwise, the term “some” refers to one or more. A phrase referring to “at least one of” a list of items refers to any combination of those items, including single members. As an example, “at least one of: a, b, or c” is intended to cover: a; b; c; a and b; a and c; b and c; and a, b and c. All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. No claim element is to be construed under the provisions of 35 U.S.C. § 112, sixth paragraph, unless the element is expressly recited using the phrase “means for” or, in the case of a method claim, the element is recited using the phrase “step for.”
