Circuit for detecting and correcting central level of FSK demodulation signal

Abstract

A circuit for detecting and correcting a central level according to the present invention is constituted such that there occurs a case that the length of a code of “1” or “0” in an FSK signal extremely long, and even if this extremely long code superimposed with a frequency fluctuation of a transmitter/receiver is received, a central level can always be detected accurately. This circuit is provided with sample value holding circuits exclusive to “1” and “0” of an input demodulation data signal respectively. After a difference voltage between both sample values is once converted to a digital code in an ADA converter, and the converted code is re-converted to an analog value, thereby holding the value digitally. When “1”s continue sequentially, the hold voltage to “1” is momently updated to new values and simultaneously a voltage obtained by subtracting the difference voltage from the above-described voltage is applied to the holding circuit for “0” to update the value in the holding circuit. Also, when “0”s continue sequentially, the processing proceeds in reverse to the former case and simultaneously with a self-updating the holding circuit for “1” is updated with a voltage obtained by adding the difference voltage to the hold voltage so that a determination on data information is made as a reference value for a comparator CMP utilizing a mean value between both the hold voltages as a central level value.

Description

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to improvement in a circuit configuration technique of a circuit for detecting and correcting a central level required at a time of demodulation of an FSK (Frequency Shift Keying) signal.

[0003] 2. Description of the Related Art

[0004] An error generally occurs due to many factors such as a transmission frequency error, a frequency error in a receiver station, a frequency error in a frequency discriminator, a drift in a direct current circuit system and the like. For this reason, various circuits for detecting a central level of the demodulation output or correcting the central level error have been proposed and used. As typical ones among correcting methods used in these circuits, there are (1) a method where peak holding circuits for positive and negative peaks are provided for two values of a demodulation base band signal and a central level is obtained from a mean value of these positive and negative peak values, (2) a method where a die band circuit to a direct current input voltage is provided in a direct circuit system for a base band signal processing, and an amplitude value of a demodulation base band signal is tuned to this die band voltage width, so that there does not occur any output in the die band circuit when there is not any error, but the output overflows from the die bandwidth when there is an error, thereby detecting a central error from this output, (3) a method where a central level is obtained by integrating bit synchronization signals positioned at a head of a packet signal over two bit length, (4) a method where a bit synchronization signal is sampled two times at an interval of 1/band (sec) which is a bit length and a central level is obtained from a mean value of these sampled values, and (5) a method which is obtained by developing the method (1) and where, in addition of holding of respective two values, a holding circuit for holding a value of ½ difference between these two values (corresponding to a shift width) is provided, and. even if “1”s or “0”s of information continue long sequentially, a central level is obtained by addition or subtraction of a shift width voltage to or from the voltage continuing long, and the like.

[0005] In these methods, however, there are the following drawbacks. That is, in the respective methods, since the central level is first obtained in an initial stage of signal reception start, an error of the central level can be corrected by using the central level thus obtained. However, a problem occurs thereafter. When a central level has fluctuated due to a frequency fluctuation or the like, it is impossible to follow this fluctuation in the methods (1), (3) and (4). In the method (2), when a central level has fluctuated in a state where a signal is frequently fluctuating between “1” and “0”, which side of the die band an output has overflowed to can be found so that an error of a central level can be detected immediately. However, in case that the signal remains “1” or “0” long, detection can be made when “1” or “0” shifts in an overflowing direction from the die band, but in case that the signal shifts in a reverse direction thereto, detection can not be made except that the shifting exceeds the die bandwidth. In the method (5), the drawbacks found in the above-described methods can be solved, but there occurs another problem. The problem also occurs in the method (1), and it is a problem due to discharging of a hold voltage inevitably caused by using an analog circuit. Therefore, the method (5) can not be applied except for a time range where an influence of the discharging can be disregarded.

[0006] In order to solve the above problem, an object of the present invention is to construct a circuit where in a demodulation of an FSK signal, not only at a time of communication start but also even in a case that “1” or “0”, of the FSK demodulation signal continues long, a central level can always be detected and an error, if any, can be corrected.

SUMMARY OF THE INVENTION

[0007] In order to solve the above problem, according to an aspect of the present invention, there is provided a circuit for detecting and correcting a central level of an FSK demodulation signal, comprising: a first holding circuit which holds a first sample signal of a base band signal demodulated of an FSK signal by a first sampler; a second holding circuit which holds a second sample signal of the base band signal by a second sampler; shift value calculating means for taking a difference between outputs from the first and second holding circuits to calculate a shift width value; converting means for analog-digital-analog converting the shift width value; adding means for adding an analog-converted signal of the converting means to the base band signal; subtracting means for subtracting the analog-converted signal from the base band signal; a third sampler which holds a third sample signal of the output of the adding means at the first holding circuit; a fourth sampler which holds a fourth sample signal at the second holding circuit; mean value calculating means for taking a mean of outputs of the first and second holding circuits to calculate a central level value of an FSK demodulation signal; determining means for making determination about “1” or “0” of signal reception information data of the FSK signal by utilizing the central level value as a reference value; and control means for controlling a holding function of the converting means and operations of the first to fourth samplers according to the determination result of the determination means.

[0008] Further, in another aspect of the invention, the circuit for detecting and correcting a central level of an FSK demodulation signal may be provided with means for subtracting the central level value from the base band signal to output the same.

[0009] Furthermore, in still another aspect of the invention, the circuit for detecting and correcting a central level of an FSK demodulation signal may be provided with means for feeding back the central level value to a local oscillator for frequency conversion of an FSK demodulation circuit to control a oscillation frequency of the local oscillator.

[0010] According to the above-described configuration, in the circuit of the present invention, the holding circuits are respectively caused to hold two sample values corresponding to “1” and “0” individually, a mean value of the outputs of the holding circuits is set to a central level value and a difference voltage (corresponding to a peak-to-peak value in case of a bit synchronization signal) of between the outputs of both the holding circuits is once converted to a digital code, so that holding is performed with this digital code as necessary. When “1”s come sequentially, the holding circuit for “1”, is momently updated with sample values of respective “1”s and voltages obtained by subtracting voltages where the digital codes have been converted to analog values from the sample values are added to the holding circuit for “0” to conduct updating to momentary values. When “0”s come sequentially, the holding circuit for “1” is momently updated with sample values of respective “0”s, and voltages obtained by adding voltages where the digital codes have been converted to analog values to the sample values are added to the holding circuit for “1” to conduct updating of momentary values. According to this operation, when “1” is being received, a voltage corresponding to “0” can be obtained together with a received voltage of “1”, and when “0” is being received, a voltage corresponding to “1” can be obtained together with a received voltage of “0”, so that these values are held by the respective holding circuits. Both the holding circuits are always updated to momentary values (for example, at a baud speed of communication). Since a mean value of both the hold voltages obtained in this manner is a central level, this voltage is used as a reference voltage for a comparator.

[0011] Thus, even if a code where “1”s or “0”s continue long is used, and even if a central frequency is fluctuating, a correct central level value can always be obtained.

[0012] As described above, according to the present invention, in demodulation of an FSK signal, even if “1”s or “0”s of information continue long and sequentially, a shift width is stored as a digital code, so that a central level can be detected by adding or subtracting a voltage of the shift width to or from a signal voltage being currently received. Therefore, “1”, or “0”, can be determined by a comparator on the basis of this central level or an AFC system can be configured by feeding back the central level. In this invention, since a central level is detected by using a signal being currently received, a fluctuation of the central level can be detected and corrected irrespective of the contents of a transmission code sequence.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention;

[0014] FIGS. 2A and 2B are waveforms for explaining an operation of a circuit shown in FIG. 1;

[0015] FIG. 3 is a block diagram showing another embodiment of the invention; and

[0016] FIG. 4 is a block diagram showing still another embodiment of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] One embodiment of a circuit for detecting and correcting a central level of an FSK demodulation circuit of the present invention will be explained below with reference to the drawings.

[0018] FIG. 1 is a configuration diagram of a circuit of an embodiment, and FIG. 2 is a diagram showing waveforms for explaining an operation of the circuit, where (a) indicates waveforms of respective portions at a time of bit synchronization signal reception of an FSK signal and (b) indicates waveforms of respective portions at a time of an normal data signal reception.

[0019] In FIG. 1, IN denotes an input terminal for an FSK demodulation base band signal, CD denotes a carrier detection signal input terminal from a carrier detector of an FSK demodulation circuit, CLK denotes an output terminal for a clock signal regenerated, OUT denotes an output terminal for a FSK demodulation signal (data information) whose central level has been corrected, ADD denotes an addition circuit, SUB1, SUB2 denotes subtracting circuits, SPL1, SPL2, SPL3, SPL4 denote samplers, ADA denotes an analog-digital-analog converter, HLD1, HLD2 denote holding circuits, MEAN denotes a mean value circuit, LPF denotes a low-pass filter, CMP denotes a comparator, REG1, REG2 denote a registers, EXOR denotes an explosive OR circuit, CONT denotes a control circuit, and CLK a clock regenerating circuit.

[0020] First of all, an operation at a time of reception of a bit synchronization signal component of an FSK demodulation signal will be explained.

[0021] A FSK demodulation base band signal input from the signal input terminal IN is applied to the clock regenerating circuit CLK so that clock signals are regenerated. The regenerated signals which have been regenerated in the clock regenerating circuit include three kinds of signals a1, a0, clk. As shown in FIG. 2A, these clock signals are constituted such that the signal a1 is generated at a sampling point (a positive peak point) of “1” of a bit synchronization signal while a0 is generated at another sampling point (a negative peak point) of “0” of the bit synchronization signal, that is, a1 is generated when “1” is to be sampled while a0 is generated when “0” is to be sampled. In the explanation of the present embodiment, hereinafter, it is assumed that “1” of information bit is received at a positive voltage relative to “0” while “0” thereof is received at a negative voltage relative to “1”. In case that this relationship is reversed, “1”should be read as “0” while “0”should be read as “1”.

[0022] During reception of a bit synchronization signal, such a configuration is employed that both the clock pulses of a1 and a0 appear at the b1 , b0 through the control circuit CONT as they are, so that a positive peak value e1 of “1” and a negative peak value e2 of “0” are respectively sampled at the sampler SPL3 and the sampler SPL4 and held at the holding circuits HLD1 and HLD2. Outputs of both the holding circuits are inputted into the subtracting circuit SUB2 where a difference between a positive peak voltage and a negative peak voltage e1-e2 is obtained. Since this voltage is a difference between the both peak voltages, it corresponds to a value two times a shift width from a central level to both the peaks. Hereinafter, this voltage is abbreviated as a shift width voltage.

[0023] Next, after the shift width voltage is applied to the analog-digital-analog converter ADA (hereinafter, abbreviated as ADA converter) to be once converted to a digital code, it is recovered to an analog voltage, again. The ADA has a function for making it possible to perform a complete holding of the shift width voltage by holding the shift width voltage as the digital code when the shift width voltage has once been converted to a digital code.

[0024] In case that it can be assumed that the shift width of an FSK signal does not fluctuate within a time range of about one packet, a time of a holding start is determined from a structure of a packet and a reception start time, so that the ADA converter is held by controlling conducted according to a hold instruction signal outputted to a control line d depicted with a dotted line extending from the control circuit CONT. Therefore, in this case, this hold is maintained until the packet is terminated.

[0025] The shift width voltage obtained in this manner is applied to the adding circuit ADD and the subtracting circuit SUB1. This is because “1” of information bit is received at a positive voltage so that, when “1” has been received, a voltage corresponding to “0” can be obtained by subtracting the shift voltage from the voltage at that time, and “0” is received at a negative voltage so that, when “0” has been received, a voltage corresponding to “1” can be obtained by adding the shift width voltage to the voltage at that time.

[0026] The voltage corresponding to “1”, thus obtained is inputted to the sampler SPL1, while the voltage corresponding to “0” is inputted to the sampler SPL2. As understood from FIG. 2A, in the samplers SPL1 and SPL2, since the sampling pulses c1 and c0 do not occur, sampling is not conducted.

[0027] Since outputs from the holding circuits HLD1 and HLD2 are applied to the mean value circuit MEAN, a central level value of the FSK signal can be obtained here. The central level value is inputted into the comparator CMP via the low-pass filter LPF where the central level value is used as a reference voltage. Thereby, the comparator CMP can make a determination about whether the reception information data of the FSK signal is “1” or “0” on the basis of the just central level of a binary signal.

[0028] Next, operation at the data signal component reception time of the FSK demodulation signal will be explained.

[0029] As mentioned above, since a shift width signal is held in the ADA converter, when “1” has been received, a voltage corresponding to “0” can be obtained at the output of the subtracting circuit SUB1, while the voltage corresponding to “1” can be obtained at the output of the adding circuit ADD when “0” has been received. Accordingly, as shown in FIG. 2B, when “1” has been received, the signal voltage is read in at the sampling pulse b1 to be held in the holding circuit HLD1 and simultaneously the voltage corresponding to “0”, obtained by subtracting the shift width voltage from this signal voltage is read in at the sampling pulse c0 to be held in the holding circuit HLD2. On the other hand, when “0” has been received, the signal voltage is read in at a sampling pulse b0 to be held at the holding circuit HLD2 and simultaneously the voltage corresponding to “1”, obtained by adding the shift width voltage to this signal voltage is read in at a sampling pulse c1 to be held at the holding circuit HLD1. That is, the reception voltage corresponding to “1” and the reception voltage corresponding to “0” are respectively applied and held in the holding circuits HLD1 and HLD2 for each bit of the data signal component whether the information is “1” or “0”.

[0030] Thus, since the values in the holding circuits HLD1 and HLD2 are always updated to new values whether the information is “1” or “0”, the central level can correctly be detected even if “1”s or “0”s continue long sequentially.

[0031] The binary signal (data information) shaped in the comparator CMP is outputted into the signal output terminal OUT and is applied to a two-stage shift register constituted with the registers REG1 and REG2. When an input and an output of the register REG1 are inputted to the exclusive OR circuit EXOR, determination can be made about whether or not sequential bits of the data information are the same polarity. Therefore, such a constitution can be employed that, when the same polarity bits continue, the ADA converter is held but when a bit has a different polarity, the holding is not conducted, that is, updating to a new value can be made. Thus, even if the shift width fluctuates during communication, such a fluctuation can be followed so that a correct central level can always be detected.

[0032] In the above explanation, the method which obtains a central level value to utilize the value as a reference voltage for the comparator CMP has been described, but such a constitution shown in FIG. 3 can be employed when a base band signal whose center error is zero is required for another different purpose. In FIG. 3, SUB3 denotes a subtracting circuit and MISC denotes an output terminal for another purpose, where a central level value is subtracted from an FSK demodulation base band signal to be outputted to the output terminal MISC.

[0033] Further, in the FSK demodulation circuit, an AFC (automatic frequency control) is effected for improving an effective use and an SN ratio of an intermediate frequency amplifier or the like. In this case, such a configuration can be employed that a signal representing a detected central level is fed back to a local oscillator for frequency conversion VCO (a voltage control oscillator) as it is to control an oscillation frequency thereof.

Claims

1. A circuit for detecting and correcting a central level of an FSK demodulation signal, comprising: a first holding circuit which holds a first sample signal of a base band signal demodulated of an FSK signal by a first sampler; a second holding circuit which holds a second sample signal of the base band signal by a second sampler; shift value calculating means for taking a difference between outputs from the first and second holding circuits to calculate a shift width value; converting means for analog-digital-analog converting the shift width value; adding means for adding an analog-converted signal of the converting means to the base band signal; subtracting means for subtracting the analog-converted signal from the base band signal; a third sampler which holds a third sample signal of the output of the adding means at the first holding circuit; a fourth sampler which holds a fourth sample signal at the second holding circuit; mean value calculating means for taking a mean of outputs of the first and second holding circuits to calculate a central level value of an FSK demodulation signal; determining means for making determination about “1” or “0” of reception information data of the FSK signal utilizing the central level value as a reference value; and control means for controlling a holding function of the converting means and operations of the first to fourth samplers according to the determination result of the determination means.

2. A circuit for detecting and correcting a central level of an FSK demodulation signal according to claim 1, further comprising means for subtracting the central level value from the base band signal to output the same.

3. A circuit for detecting and correcting a central level of an FSK demodulation signal according to claim 1, further comprising means for feeding the central level value back to a local oscillator for frequency conversion and controlling an oscillation frequency of the local oscillator thereby correcting a central frequency error.