Component package for maintaining safe operating temperature of components

Information

  • Patent Grant
  • 8604361
  • Patent Number
    8,604,361
  • Date Filed
    Wednesday, January 20, 2010
    15 years ago
  • Date Issued
    Tuesday, December 10, 2013
    11 years ago
Abstract
A thermally insulated electronic component package and an instrument suitable for process conditions in a high temperature environment are disclosed. The component package includes a thin electronic component, a thermally insulating outer enclosure, and an insert made of a thermally insulating material that is sized and shaped to fit within the outer enclosure. The insert includes an inner cavity sized and shaped to receive the thin electronic component. In the instrument, the outer enclosure can be configured to mount to a substrate.
Description
FIELD OF THE INVENTION

This invention generally relates to high temperature, wireless measurement devices and more particularly to methods that keep the components of the devices safe while the device is exposed to high temperatures over an extend period of time.


BACKGROUND OF THE INVENTION

The fabrication of an integrated circuit, display or disc memory generally employs numerous processing steps. Each process step must be carefully monitored in order to provide an operational device. Throughout the imaging process, deposition and growth process, etching and masking process, etc., it is critical, for example, that temperature, gas flow, vacuum pressure, chemical gas or plasma composition and exposure distance be carefully controlled during each step. Careful attention to the various processing conditions involved in each step is a requirement of optimal semiconductor or thin film processes. Any deviation from optimal processing conditions may cause the ensuing integrated circuit or device to perform at a substandard level or, worse yet, fail completely.


Within a processing chamber, processing conditions vary. The variations in processing conditions such as temperature, gas flow rate and/or gas composition greatly affect the formation and thus the performance of the integrated circuit. Using a substrate-like device to measure the processing conditions that is of the same or similar material as the integrated circuit or other device provides the most accurate measure of the conditions because the thermal conductivity of the substrate is the same as the actual circuits that will be processed. Gradients and variations exist throughout the chamber for virtually all process conditions. These gradients therefore also exist across the surface of a substrate. In order to precisely control processing conditions at the substrate, it is critical that measurements be taken upon the substrate and that the readings are available to an automated control system or operator so that the optimization of the chamber processing conditions can be readily achieved. Processing conditions include any parameter used to control semiconductor or other device manufacture or any condition a manufacturer would desire to monitor.


U.S. Pat. No. 6,691,068 to Freed et al. teaches a sensor apparatus capable of measuring data, processing data, storing data, and transmitting data for a process tool used for processing workpieces. The sensor apparatus includes an information processor, embedded executable commands for controlling the apparatus, and at least one sensor. The sensor apparatus is capable of being loaded into a process tool. The sensor apparatus has capabilities for near real time data collection and communication.


Conventionally, the low profile wireless measurement device is mounted on the substrate to measure the processing conditions. For a low profile wireless measurement device to work in a high temperature environment (e.g., temperatures greater than about 150° C.), certain key components of the device, such as thin batteries and microprocessors, must be able to function when the device is exposed to the high temperature environment. Conventionally, the back AR coating (BARC) process operates at 250° C.; a CVD process may operate at a temperature of about 500° C.; and a PVD process may operate at about 300° C. Unfortunately, many types of battery, for example thin film Li batteries, melt at 180° C. The battery packaging materials may outgas at 180° C. also causing battery damage.


To build a high temperature (150° C. and higher) version of a wireless temperature measurement device, certain components that are commercially available have limited ability to operate at high temperatures. Furthermore, components with sufficient high temperature capability are not likely to be commercially available in the near future. A further challenge is that, in addition to being insulated against heat transfer, the battery should keep a profile of 2 mm or less in the wireless measurement device in order to fit into various process chambers.


It is within this context that embodiments of the present invention arise.





BRIEF DESCRIPTION OF THE DRAWINGS

Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which:



FIG. 1A is an exploded three dimensional diagram of a thin insulated component package according to an embodiment of the present invention.



FIG. 1B is a cross-sectional view of a thin insulated component package according to an embodiment of the present invention.



FIG. 1C is a cross-sectional view of a thin insulated thin component package according to an alternative embodiment of the present invention.



FIG. 2A is a top view schematic diagram of a measurement substrate with thin insulated component packages mounted on top of the substrate.



FIG. 2B is a side view of the measurement substrate of FIG. 2A with thin insulated component packages mounted on top of the substrate without stand-offs according to an embodiment of the present invention.



FIG. 2C is a side view of the measurement substrate of FIG. 2A with thin insulated component packages mounted on top of the substrate with stand-offs according to an embodiment of the present invention.



FIG. 2D is a side view cross-section of the measurement substrate of FIG. 2A with thin insulated component packages mounted into substrate cavities according to an embodiment of the present invention.





DESCRIPTION OF THE SPECIFIC EMBODIMENTS

Although the following detailed description contains many specific details for the purposes of illustration, anyone of ordinary skill in the art will appreciate that many variations and alterations to the following details are within the scope of the invention. Accordingly, the exemplary embodiments of the invention described below are set forth without any loss of generality to, and without imposing limitations upon, the claimed invention.


U.S. Pat. No. 6,889,568 and US publication No. 20060174720 to Renken et al. (the entire disclosures of both of which are incorporated herein by reference) teach a measuring device incorporating a substrate with a plurality of sensors attached to the substrate used to measure the processing conditions of the substrate during the manufacturing. The substrate can be inserted into a processing chamber by a robot head and the measuring device can transmit the conditions in real time or store the conditions for subsequent analysis. Sensitive electronic components of the device can be distanced or isolated from the most deleterious processing conditions in order to increase the accuracy, operating range, and reliability of the device. Often however, it may not be practical or desirable to raise an electronic component on legs if a low profile is desired. In addition, raising the component above a substrate might not be sufficient by itself to protect the components exposed to high temperatures over an extended period of time.


Embodiments of the present invention utilize novel thin insulated component packages that keep temperature-sensitive components within a safe operating temperature range while the device is exposed to high temperatures over an extended period of time (such as survey time). FIG. 1A is an exploded three dimensional diagram and FIG. 1B is a schematic cross-sectional view of a thin insulated component package 100A according to an embodiment of the present invention. The package 100A can include a thermally insulating outer enclosure 126 which may be made of a thermally insulating material, such as a ceramic glass. It is desirable to make the outer enclosure 126 from high specific heat capacity materials to add thermal mass to the package 100A without adding too much height.


As used herein, the term “thermally insulating” refers to the property of being resistant to transfer of heat across a material or medium as a result of low thermal conductivity and/or high heat capacity. As used herein, the term “thermally absorbing” refers to the property of being resistant to transfer of heat as a result of high heat capacity, but not necessarily due to low thermal conductivity. As may be seen from the foregoing, “thermally absorbing” is a subset of “thermally insulating.”


The thermally insulating outer enclosure 126 can be made of a thin, flat and high modulus material, e.g., sapphire, mica, an Inconel alloy, Kovar, ceramic, or a combination of Kovar and ceramic. Inconel is a registered trademark of Special Metals Corporation that refers to a family of austenitic nickel-chromium-based superalloys. A non-limiting example of an Inconel alloy is Inconel 600, which is 72% nickel, 14-17% chromium, 6-10% iron, 1% manganese, 0.5% copper, 0.5% silicon, 0.15% carbon and 0.015% sulfur. Kovar is a trademark of Carpenter Technology Corporation and refers to a nickel-cobalt ferrous alloy designed to be compatible with the thermal expansion characteristics of borosilicate glass. The composition of Kovar is about 29% nickel, 17% cobalt, less than 0.1% carbon, 0.2% silicon, 0.3% manganese with the balance being iron.


An insulating insert 128 is sized and shaped to fit within a cavity or recess in the outer enclosure 126. The insert 128 can be made essentially of high temperature machinable thermally insulating refractory ceramic material. Examples of such materials include, but are not limited to, commercially available rigid ceramic materials made from silica (SiO2) or yttria-stabilized ceramic fibers, e.g., Zirconia (ZrO2) fibers, that do not undergo the usual phase transitions associated with pure form of the ceramic. Other suitable materials include mica ceramic. By way of example, and not by way of limitation, a suitable ceramic material may have a nominal composition of about 90% by weight of Zirconia (ZrO2) and Hafnia (HfO2) (e.g., about 1-2 wt % Hafnia, which occurs naturally with Zirconia) and about 10% by weight of yttria (Y2O3). It is possible that other oxides may be present as impurities, e.g., of 0.1% or less.


The insulating insert 128 can encapsulate a thin electronic component 102, e.g., a thin film battery. By way of example, and not by way of limitation, the thickness of the component 102 may be about 6 mils. By way of example, the insert 128 may include an inner cavity or recess 130 that is sized and shaped to receive the component 102. By way of example, and not by way of limitation, the electronic component 102 may be, e.g., a thin film battery or an integrated circuit, such as a processor. The inner cavity 130 is generally thinner than the cavity in the enclosure 126. By way of example, and not by way of limitation, the inner cavity 130 may be ⅔ the overall thickness of the component package 100A. By way of example, the overall dimensions of the enclosure 126 and insert 128 the may be selected such that the component package 100A is approximately 36 mm square by 5 to 6 mm thick or less.


One or more feed-thrus for kinematic anchors 133 or electrical connections to the electronic component 102 may be formed in the outer enclosure 126 or the insert 128. The kinematic anchors 133 can facilitate mounting the component package 100A to a substrate, such as a semiconductor wafer. By way of example, and not by way of limitation, the kinematic anchors may be pins that fit into holes or recesses in a side of the outer enclosure 126. The pins can mount the outer enclosure to a kinematic structure that mounts the component package 100A onto a substrate. The kinematic structure can be custom made to the package size. Each pin may include a shoulder proximate one end to stop the pin from sliding too far into the hole in the side of the enclosure. The pins may be made of a suitable material having good structural properties and relatively good thermally insulating properties, such as stainless steel. Each pin can be received at a second end by a corresponding structure (e.g., a slot or groove) on the substrate. The use of sufficiently small diameter straight pins in holes in a side of the outer enclosure can provide for stability in mounting the component package 100A to the substrate while reducing thermal contact with the substrate.


The electronic component 102 may be bonded into the inner cavity 130 of the insert 128, e.g., using a suitable adhesive (e.g., Fire Temp glue) or other bonding technique. An optional insulating cover piece 134 may be sized and shaped to cover the electronic component 102 and close the inner cavity 130. The cover piece 134 may be made of the same insulating ceramic material as the insert 128. The package 100A may be sealed with a lid 136 that is bonded to a top of a wall of the insert 128, or a top of a wall of the outer enclosure 126, e.g., with a high temperature adhesive. By way of example, the lid 136 may be made of a material having similar thermal expansion characteristics to that of the outer enclosure 126. By way of example and not by way of limitation, if the outer enclosure 126 is made of a ceramic glass such as borosilicate glass or Al2O3 ceramic, the lid 136 may be made of Kovar. Alternatively, the lid 136 can be bonded to a top of a wall of the insert 128 or to a substrate to which the package 100A is to be mounted. In such cases, the lid 136 may be made of a material having similar thermal expansion characteristics to that of the insert or the substrate. For example, if the lid is to be bonded to a substrate that is made of silicon, the lid 136 can also be made of silicon.


The electronic component 102 and insert 128 can be sealed in the outer enclosure 126 under vacuum so that vacuum further insulates the electronic component 102. By way of example, and not by way of limitation, the thickness of the wall of the outer enclosure 126 may be about 10 to 15 mil. The internal volume of the enclosure cavity may be about 1 cubic centimeter (1 ml). The enclosure 126 may be internally and externally coated with low emissivity film, e.g., gold film, or a film having emissivity similar to that of gold or lower than that of gold, to minimize radiative heat transfer from the enclosure to the parts inside. The enclosure 126 can have a through hole 138, to evacuate the space inside the enclosure to minimize heat transfer by conduction and convection when the enclosure 126 is inside a vacuum chamber in a process tool. Furthermore, the materials of the outer enclosure 126 may be high specific heat materials selected to add thermal mass to the package without adding too much height. Examples of suitable materials include, but are not limited to, for example, sapphire, stainless steel, Kovar, an Inconel alloy or a ceramic material or combinations of two or more of these materials or materials having similar specific heat capacities to these materials or higher specific heat capacities.


Furthermore, the outer enclosure 126 is preferably made of strong material that can hold its shape under vacuum.


In another embodiment of the present invention, the construction of the insert 128 and cover piece 134 in the component package 100A may altered to slow down the increase in temperature of the electronic component 102. As shown in FIG. 1C, a thin insulated component package 100B may be configured similarly to the component package 100A of FIGS. 1A-1B. Specifically, the package 100B can include a thermally insulating outer enclosure 126, an insert 128 made is sized and shaped to fit within a cavity in the outer enclosure 126. The insert includes an inner cavity sized and shaped to receive a thin electronic component 102. In this embodiment, the insert can be made of alternating interdigitated layers of thermally absorbing material 142 and low thermal conductivity material or medium 144. A cover piece 134 for the insert can be similarly constructed. By way of example, the thermally absorbing material 142 may include Inconel, or Kovar and the low thermal conductivity material or medium 144 can include a ceramic material, e.g., a high temperature machinable thermally insulating refractory ceramic material, such as that described above or vacuum. Alternating thermally absorbing material and low thermal conductivity material or medium in the insert 128 can reduce the rate of temperature change of the electronic component 102.


One or more thermally insulated electronic component packages like that shown in FIGS. 1A-1C may be mounted on a substrate, such as a semiconductor wafer, with or without stand-offs to further insulate the package from the substrate. For example, as shown schematically in FIG. 2A, a process condition measurement device 200 may have one or more thin insulated component packages 100A of the type depicted in FIG. 1A mounted on a top surface of a substrate 201. The substrate may be the same size and shape as a standard substrate processed by a semiconductor wafer processing system. Examples of standard sized substrates include, but are not limited to 150 mm, 200 mm and 300 mm semiconductor wafers. By way of example, and not by way of limitation, an electronic component such as a battery 202 can be mounted within one of the packages 100A. The battery 202 may be electrically connected to a bus 204. There may alternatively be only one battery package or more than two batteries installed, depending upon the application and resulting power needs. The device 200 may include measurement electronics 205 that are powered by the batteries and/or exchange electronic signals through the bus 204. By way of example, and not by way of limitation, the measurement electronics 205 may include a processor module 207, a memory 209, a transceiver 211, and one or more process condition sensors, e.g., an electromagnetic sensor 213, a thermal sensor 215, and an optical or electrical sensor 217. In some embodiments, certain elements of the measurement electronics 205 (e.g., the processor module 207, memory 209, transceiver 211, thermal sensor 215, or optical sensor 217) may be packed in component packages of the types described herein.


The processor module 207 may be configured to execute instructions stored in the main memory 209 in order for the device 200 to properly measure process parameters when the device is placed within a substrate processing tool. The main memory 209 may be in the form of an integrated circuit, e.g., RAM, DRAM, ROM and the like. The transceiver 211 may be configured to communicate data and/or electrical power two or from the device 200.


As seen in FIG. 2B, two or more component packages 100A may be mounted directly on the top surface of the substrate 201. Alternatively, as shown in FIG. 2C, two or more component packages 100A may be mounted to the top surface of the substrate 201 using a kinematic structure 206 that mounts the outer enclosure via the kinematic mounts 133. This allows for a gap between the component packages 100A and the substrate 201 to further insulate the batteries from the substrate. The kinematic structure 206 may include slots or grooves to receive the kinematic mounts 133 e.g., pins as described above. Furthermore, as shown in FIG. 2D, two or more component packages 100A may be mounted into substrate cavities formed in the top surface of the substrate 201 to provide a low profile. The component packages 100A may be mounted via the kinematic mounts 133 to a kinematic structure 206 in the outer cavity.


As noted above, the use of sufficiently small diameter pins in holes in a side of the outer enclosure can provide for stability in mounting the component package 100A to the substrate 201 while reducing thermal contact with the substrate. As also noted above, the lid 136 can be mounted to the substrate 201 and cover the substrate 201 and the cavities into which the outer enclosures 126 are mounted. Alternatively, each cavity may have an individual lid. Furthermore, each component package 100A may alternatively be mounted into a cavity without a lid.


By appropriate selection of the thickness of the component 102, the outer enclosure 126, insert 128, and cover piece 134, the profile of the measurement device 200 may be made less than 2 mm above the surface of the substrate 201. Such a device can be used to do in-situ measurements of process conditions in a semiconductor process tool without mechanically interfering with the operation of the tool.


Many variations on the above-described embodiments are within the scope of embodiments of the present invention. For example, the thickness of the lower wall or sidewalls of the insert 128 can be varied depending on whether a source of heat is located above, below, or to a side of the component package. Similarly, the thickness of the cover piece 134 may vary, or the cover piece may be omitted entirely, depending on whether the heat source is located above or below the component package.


Although the present invention has been described in considerable detail with reference to certain preferred versions thereof, other versions are possible. For example, although a pump-down hole is shown in FIGS. 1B-1C, embodiments of the invention include constructions in which the pump-down hole is omitted. Therefore, the spirit and scope of the appended claims should not be limited to the description of the preferred versions contained herein. Instead, the scope of the invention should be determined with reference to the appended claims, along with their full scope of equivalents. All the features disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.


While the above is a complete description of the preferred embodiment of the present invention, it is possible to use various alternatives, modifications and equivalents. Therefore, the scope of the present invention should be determined not with reference to the above description but should, instead, be determined with reference to the appended claims, along with their full scope of equivalents. Any feature, whether preferred or not, may be combined with any other feature, whether preferred or not. In the claims that follow, the indefinite article “A”, or “An” refers to a quantity of one or more of the item following the article, except where expressly stated otherwise. The appended claims are not to be interpreted as including means-plus-function limitations, unless such a limitation is explicitly recited in a given claim using the phrase “means for.” Any element in a claim that does not explicitly state “means for” performing a specified function, is not to be interpreted as a “means” or “step” clause as specified in 35 USC §112, ¶ 6. In particular, the use of “step of” in the claims herein is not intended to invoke the provisions of 35 USC §112, ¶ 6.


The reader's attention is directed to all papers and documents which are filed concurrently with this specification and which are open to public inspection with this specification, and the contents of all such papers and documents incorporated herein by reference.

Claims
  • 1. A thermally insulated electronic component package, comprising: a thin electronic component;a thermally insulating outer enclosure;an insert made of a thermally insulating material that is sized and shaped to fit within the outer enclosure, wherein the insert includes an inner cavity sized and shaped to receive the thin electronic component, and wherein the insert is made of alternating interdigitating layers of low thermal conductivity material and thermally absorbing material; andone or more structures configured to mount the outer enclosure to a substrate.
  • 2. The thermally insulated electronic component package of claim 1 wherein the thin electronic component comprises a battery.
  • 3. The thermally insulated electronic component package of claim 1, wherein the thermally insulating outer enclosure is made of one or more high heat capacity materials.
  • 4. The thermally insulated electronic component package of claim 3, wherein the high heat capacity materials include stainless steel, an austenitic nickel-chromium-based superalloy, a nickel-cobalt ferrous alloy or a ceramic material.
  • 5. The thermally insulated electronic component package of claim 1 where in the outer enclosure is made of a low thermal conductivity material.
  • 6. The thermally insulated electronic component package of claim 1 wherein the outer enclosure is made of a low emissivity and high heat capacity material.
  • 7. The thermally insulated electronic component package of claim 1 wherein the enclosure is made of stainless steel, an austenitic nickel-chromium-based superalloy, a nickel-cobalt ferrous alloy, or a ceramic material.
  • 8. The thermally insulated electronic component package of claim 7 wherein the thickness of a wall of the enclosure is about 10 to 15 mil.
  • 9. The thermally insulated electronic component package of claim 1 wherein an inner and outer surface of the outer enclosure is coated with a thin film containing a low emissivity material.
  • 10. The thermally insulated electronic component package of claim 9 wherein the low emissivity material is gold.
  • 11. The thermally insulated electronic component package of claim 1 wherein one or more of the structures include one or more pins configured to fit into one or more corresponding holes in a side of the outer enclosure.
  • 12. The thermally insulated electronic component package of claim 1 wherein a total thickness of the enclosure about 5 to 6 mm or less.
  • 13. The thermally insulated electronic component package of claim 1 wherein the enclosure is evacuated and sealed.
  • 14. The thermally insulated electronic component package of claim 1, further comprising a cover piece sized and shaped to cover the electronic component and close the inner cavity.
  • 15. The thermally insulated electronic component package of claim 14 wherein the cover piece is made of the same material as the insert.
  • 16. The thermally insulated electronic component package of claim 1, further comprising a lid that is bonded to a top of a wall of the outer enclosure or to a substrate to which the thermally insulated electronic component package is mounted.
  • 17. The thermally insulated electronic component package of claim 16 wherein the lid is made of a material having similar thermal expansion characteristics to that of the enclosure.
  • 18. The thermally insulated electronic component package of claim 1 wherein the insert is made of a thermally insulating ceramic material.
  • 19. The thermally insulated electronic component package of claim 18 wherein the ceramic material is a machinable ceramic material.
  • 20. An electronic instrument suitable for process conditions in a high temperature environment, comprising: a substrate;one or more thermally insulated electronic component package having a thermally insulating outer enclosure configured to mount to the substrate;a plurality of stand-offs configured to provide support between the outer enclosure and the substrate, wherein a gap is present between a bottom surface of the enclosure and the substrate;an insert made of a thermally insulating material that is sized an shaped to fit within the outer enclosure, wherein the insert includes an inner cavity sized and shaped to receive a thin electronic component; anda thin electronic component disposed within the inner cavity.
  • 21. The instrument of claim 20 wherein the outer enclosure is mounted on a top surface of the substrate.
  • 22. The instrument of claim 20 wherein the substrate includes a substrate cavity and the outer enclosure is mounted in the substrate cavity.
  • 23. The instrument of claim 22 further comprising a lid configured to cover the substrate and the electronic component.
  • 24. The instrument of claim 23 wherein the lid piece is made of the same material as the substrate.
  • 25. The instrument of claim 20, further comprising a lid that is bonded to a top of the insert or to a top of a wall of the outer enclosure or to the substrate.
  • 26. The instrument of claim 25 wherein the lid is made of a material having similar thermal expansion characteristics to that of the outer enclosure or the substrate.
  • 27. The instrument of claim 21, further comprising one or more structures configured to mount the outer enclosure to a substrate.
  • 28. The instrument of claim 27 wherein one or more of the structures include one or more pins, each pin having a first end configured to fit into one or more corresponding holes in a side of the outer enclosure and one or more structures on the substrate, wherein each of the one or more structures is configured to receive a second end of a corresponding one of the pins.
CLAIM OF PRIORITY

This application is a continuation-in-part of and claims the priority benefit of U.S. patent application Ser. No. 11/302,763, filed Dec. 13, 2005 and published as U.S. Patent Application Publication Number 20060174720, the entire contents of which are incorporated herein by reference. This application also claims the priority benefit of U.S. patent application Ser. No. 12/642,695, filed Dec. 18, 2009 as U.S. patent application Ser. No. 12/642,695 and converted to a provisional application as U.S. Patent Application 61/274,116 on Jan. 7, 2010, the entire contents of which are incorporated herein by reference.

US Referenced Citations (77)
Number Name Date Kind
3589979 Finch et al. Jun 1971 A
4443523 Hasennauer Apr 1984 A
RE32369 Stockton et al. Mar 1987 E
4656454 Rosenberger Apr 1987 A
4680569 Yamaki et al. Jul 1987 A
4795975 Cox Jan 1989 A
5001934 Tuckey Mar 1991 A
5016086 Inoue et al. May 1991 A
5184107 Maurer Feb 1993 A
5187642 Garner et al. Feb 1993 A
5262944 Weisner et al. Nov 1993 A
5285559 Thompson et al. Feb 1994 A
5341684 Adams et al. Aug 1994 A
5435646 McArthur Jul 1995 A
5444637 Smesny et al. Aug 1995 A
5479197 Fujikawa et al. Dec 1995 A
5564889 Araki Oct 1996 A
5603656 Baer et al. Feb 1997 A
5629538 Lipphardt et al. May 1997 A
5669713 Schwartz et al. Sep 1997 A
5689878 Dahringer et al. Nov 1997 A
5790151 Mills Aug 1998 A
5792984 Bloom Aug 1998 A
5895859 Sawada et al. Apr 1999 A
5969639 Lauf et al. Oct 1999 A
5970313 Rowland et al. Oct 1999 A
6010538 Sun et al. Jan 2000 A
6033922 Rowland et al. Mar 2000 A
6075909 Ressl Jun 2000 A
6100506 Colelli, Jr. et al. Aug 2000 A
6104620 Dudas et al. Aug 2000 A
6164132 Matulek Dec 2000 A
6181727 Stowell et al. Jan 2001 B1
6190040 Renken et al. Feb 2001 B1
6201467 Winterer et al. Mar 2001 B1
6273544 Silverbrook Aug 2001 B1
6301097 Ellsworth et al. Oct 2001 B1
6313903 Ogata Nov 2001 B1
6325536 Renken et al. Dec 2001 B1
6326543 Lamp et al. Dec 2001 B1
6378378 Fisher Apr 2002 B1
6472240 Akram et al. Oct 2002 B2
6477447 Lin Nov 2002 B1
6542835 Mundt Apr 2003 B2
6553277 Yagisawa et al. Apr 2003 B1
6590777 Morino et al. Jul 2003 B2
6607135 Hirai et al. Aug 2003 B1
6651488 Larson, III et al. Nov 2003 B2
6655835 Mattoon et al. Dec 2003 B2
6665190 Clayton et al. Dec 2003 B2
6671660 Freed Dec 2003 B2
6677166 Hunter Jan 2004 B2
6691068 Freed Feb 2004 B1
6734027 Jonkers May 2004 B2
6738722 Polla et al. May 2004 B2
6741945 Polla et al. May 2004 B2
6759253 Usui et al. Jul 2004 B2
6789034 Freed Sep 2004 B2
6819559 Seeger et al. Nov 2004 B1
6889568 Renken May 2005 B2
6915589 Sun et al. Jul 2005 B2
6930879 Frisch et al. Aug 2005 B2
6966235 Paton Nov 2005 B1
6971036 Freed Nov 2005 B2
6995691 Parsons Feb 2006 B2
7005644 Ishikawa et al. Feb 2006 B2
7135852 Renken et al. Nov 2006 B2
7360463 Renken Apr 2008 B2
7385199 DeWames et al. Jun 2008 B2
7683270 Fernandez et al. Mar 2010 B2
7799614 Otremba et al. Sep 2010 B2
20010002119 Winterer et al. May 2001 A1
20010012639 Akram et al. Aug 2001 A1
20040031340 Renken Feb 2004 A1
20040074323 Renken Apr 2004 A1
20060174720 Renken Aug 2006 A1
20080192800 Asada Aug 2008 A1
Foreign Referenced Citations (15)
Number Date Country
0539804 May 1993 EP
0563713 Oct 1993 EP
0764977 Mar 1997 EP
0865922 Sep 1998 EP
1014437 Jun 2000 EP
2086807 May 1982 GB
2000355756 Dec 2000 JP
2002270765 Sep 2002 JP
2005156314 Jun 2005 JP
2005516400 Jun 2005 JP
WO0068986 Nov 2000 WO
WO0217030 Feb 2002 WO
WO0217030 Feb 2002 WO
03063245 Jul 2003 WO
WO03067183 Aug 2003 WO
Non-Patent Literature Citations (30)
Entry
International Search Report for International Patent Application No. PCT/US2010/059670 dated Aug. 2, 2011.
Office Action dated Jan. 25, 2010 issued for Korean Patent Application No. 2004-7011508.
Office Action dated Oct. 20, 2009 issued for Japanese Patent Application No. 2003-563004.
Final Office Action dated Mar. 29, 2007 for U.S. Appl. No. 10/685,550.
Notice of Allowance dated Dec. 17, 2007 for U.S. Appl. No. 10/685,550.
Notice of Allowance dated Sep. 7, 2004 for U.S. Appl. No. 10/056,906.
Office Action dated Aug. 22, 2007 of U.S. Appl. No. 10/685,550.
Office Action dated Jun. 18, 2003 for U.S. Appl. No. 10/056,906.
Final Office Action Dated Jan. 12, 2004 for U.S. Appl. No. 10/056,906.
Office Action dated Jun. 29, 2004 for U.S. Appl. No. 10/685,550.
Final Office Action dated Mar. 16, 2006 for U.S. Appl. No. 10/685,550.
Notice of Allowance and Fee(s) due dated Dec. 14, 2009 issued for U.S. Appl. No. 11/302,763.
U.S. Appl. No. 12/106,992 filed on Apr. 21, 2008.
Office Action dated Jun. 25, 2008 issued for U.S. Appl. No. 11/302,763.
Final Office Action dated Jan. 14, 2009 issued for U.S. Appl. No. 11/302,763.
Office Action dated Jun. 4, 2009 issued for U.S. Appl. No. 11/302,763.
U.S. Appl. No. 61/274,116, filed Dec. 18, 2009.
Baker et al.; “A Novel In Situ Monitoring Technique for Reactive Ion Etching Using a Surface Micromachined Sensor,” IEEE Transactions on Semiconductor Manufacturing, vol. 11, No. 2, May 1998, pp. 254-264.
Prov. U.S. Appl. No. 60/285,613, filed Apr. 19, 2001; Freed et al.; “Firmware, Methods, Apparatus, and Computer Program Products for Wafer Sensors”.
Prov. U.S. Appl. No. 60/285,439, filed Apr. 19, 2001; Freed et al.; “Methods Apparatus, and Computer Program Products for Obtaining Data for Process Operation, Optimization, Monitoring, and Control”.
Freed et al.; “Autonomous On-Wafer Sensors for Process Modeling, Diagnosis, and Control,” IEEE Transactions on Semiconductor Manufacturing, vol. 14, No. 3, Aug. 2001, pp. 255-264.
Freed; “Wafer-Mounted Sensor Arrays for Plasma Etch Processes”, Dissertation, Univ. of CA. Berkeley, Fall 2001.
International Search Report, corresponding to PCT/US03/00751, Aug. 1, 2003, 3 pages.
“Notification of Transmittal of the International Search Report or the Declaration”, corresponding PCT application No. PCT/US03/00751, International Searching Authority, European Patent Office, Jun. 8, 2003, 7 pages.
PTO, “Office Action,” corresponding U.S. Appl. No. 10/685,550, Sep. 25, 2006, 18 pages.
Rubitherm GmbH, “Rubitherm® RT, Phase Change Material based on n-Paraffins and Waxes,” Innovative PCM's and Thermal Technology, Rubitherm Phase Change Material, Version: Jun. 15, 2004, 2 pages.
Unsolicited e-mail from Steve Maxwell at steve—maxwell60@yahoo.com to info@phdr-law.com, dated Jan. 3, 2006, 1 page.
JPO First Office action issued date Feb. 15, 2011 for Japanese Patent Application No. 2006-357220.
Taiwan Office action and Taiwan IPO Search Report mailed date Oct. 15, 2012 issued for Taiwan Invention Patent Application No. 095146033.
Korean Office Action mailed date May 14, 2013, issued for Korean Patent Application No. 2006-0127027.
Related Publications (1)
Number Date Country
20100155098 A1 Jun 2010 US
Provisional Applications (1)
Number Date Country
61274116 Dec 2009 US
Continuation in Parts (1)
Number Date Country
Parent 11302763 Dec 2005 US
Child 12690882 US