Patent Grant
11574602
This application claims priority to and the benefit of Korean Patent Application No. 10-2020-0107184 filed on Aug. 25, 2020, the disclosure of which is incorporated herein by reference in its entirety.
The present disclosure relates to a display device and an electronic device including the same.
Electroluminescent display devices are roughly classified into inorganic light emitting display devices and organic light emitting display devices depending on materials of light emitting layers. Active matrix type organic light emitting display devices include organic light emitting diodes (hereinafter, referred to as “OLEDs”) that are self-luminescent, and advantageously have a high response speed, a high luminous efficiency, a high luminance, and a wide viewing angle. In the organic light emitting display devices, an OLED is formed in each pixel. The organic light emitting display devices have a high response speed, an excellent luminous efficiency, an excellent luminance, and an excellent viewing angle as well as excellent contrast ratio and color reproducibility because black gray scale may be expressed as complete black.
Multimedia functions of mobile devices are being improved. For example, cameras are basically built into smartphones, and the resolution of the cameras trends is increasing to a level of a conventional digital camera. However, front cameras of the smart phone restrict screen designs, making it difficult to design the screen. In order to reduce spaces occupied by the cameras, screen designs including notches or punch holes have been adopted in the smartphones. However, screen sizes are still limited due to the cameras, and thus full-screen displays cannot be implemented.
In order to implement the full-screen displays, a method has been proposed in which a sensing area in which low-resolution pixels are arranged in a screen of a display panel is provided and a camera is arranged at a position facing the sensing area below the display panel. The sensing area in the screen is operated as a transparent display for displaying an image. Such a sensing area has low transmittance and low luminance due to the pixels.
Optical compensation for each area is required to improve a brightness difference and a color difference between the low-resolution pixels and high-resolution pixels. The optical compensation for each area is to fix an analog gamma and to be corrected with a digital gamma. The analog gamma should be set high based on a sensing area that requires a high drive voltage, but loss of actual drive data bits in a display area occurs. A method capable of gamma correction in all areas only using the analog gamma is required.
The present disclosure is directed to solving all the above-described necessity and problems.
The present disclosure provides a display device, which may uniformize the image quality of a full-screen display having a sensing area, and an electronic device including the same.
It should be noted that objects of the present disclosure are not limited to the above-described objects, and other objects of the present disclosure will be apparent to those skilled in the art from the following descriptions.
A display device according to the present disclosure includes: a first data line group including data lines connected to pixels arranged at a first resolution in a first area of a screen; a second data line group including the data lines connected to pixels arranged at the first resolution and pixels arranged at a second resolution lower than the first resolution in a second area of the screen; a first gamma compensation voltage generation unit that divides a first reference voltage and outputs a gamma compensation voltage; a second gamma compensation voltage generation unit that divides a second reference voltage and outputs gamma compensation voltages that are different according to each resolution; a first data drive unit that converts pixel data, which is to be written in the pixels of the first area, into the gamma compensation voltage output from the first gamma compensation voltage generation unit and outputs a data voltage to the data lines of the first data line group; and a second data drive unit that converts pixel data, which is to be written in the pixels of the second area, into the gamma compensation voltage output from the second gamma compensation voltage generation unit and outputs a data voltage to the data lines of the second data line group.
According to the present disclosure, the image quality of a full-screen display having a sensing area can be uniformized.
According to the present disclosure, an individual analog gamma reference voltage can be set in the sensing area, and accordingly, all areas can be driven without loss of data bits.
According to the present disclosure, since an analog gamma reference signal varies in a boundary portion between a display area and the sensing area according to a scanning time, the boundary portion can be additionally compensated for.
The above and other objects, features and advantages of the present disclosure will become more apparent to those of ordinary skill in the art by describing exemplary embodiments thereof in detail with reference to the accompanying drawings, in which:
The advantages and features of the present disclosure and methods for accomplishing the same will be more clearly understood from embodiments described below with reference to the accompanying drawings. However, the present disclosure is not limited to the following embodiments but may be implemented in various different forms. Rather, the present embodiments will make the disclosure of the present disclosure complete and allow those skilled in the art to completely comprehend the scope of the present disclosure. The present disclosure is only defined within the scope of the accompanying claims.
The shapes, sizes, ratios, angles, numbers, and the like illustrated in the accompanying drawings for describing the embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Like reference numerals generally denote like elements throughout the present specification. Further, in describing the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure.
The terms such as “comprising,” “including,” “having,” and “consist of” used herein are generally intended to allow other components to be added unless the terms are used with the term “only.” Any references to singular may include plural unless expressly stated otherwise.
Components are interpreted to include an ordinary error range even if not expressly stated.
When the position relation between two components is described using the terms such as “on,” “above,” “below,” and “next,” one or more components may be positioned between the two components unless the terms are used with the term “immediately” or “directly.”
The terms “first,” “second,” and the like may be used to distinguish components from each other, but the functions or structures of the components are not limited by ordinal numbers or component names in front of the components.
The following embodiments can be partially or entirely bonded to or combined with each other and can be linked and operated in technically various ways. The embodiments can be carried out independently of or in association with each other.
Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.
In embodiments, a novel scheme is proposed in which a screen is classified into a first area including pixels arranged at a first resolution and a second area including pixels arranged at the first resolution and pixels arranged at a second resolution that is lower than the first resolution, a first gamma compensation voltage generated by dividing a first reference voltage is applied to the first area, and different second gamma compensation voltages generated by dividing a first voltage level and a second voltage level of a second reference voltage according to each resolution are applied to the second area.
In this case, when the first resolution is referred to as a high resolution, and the second resolution is referred to as a low resolution, an area in which pixels are arranged at the low resolution is named a sensing area. Here, the sensing area includes at least one of a first sensing area including a camera module and a second sensing area including a fingerprint recognition module, but the present disclosure is not limited thereto. Such a sensing area is an area designed to have a resolution lower than that of a display area.
Referring to
The display area DA and the first sensing area include a pixel array in which pixels in which pixel data is written are arranged. The number of pixels per unit area, that is, the PPI, of the first sensing area CA is lower than the PPI of the display area DA in order to secure the transmittance of the first sensing area CA.
The pixel array of the display area DA includes a pixel area (first pixel area) in which a plurality of pixels having a high PPI are arranged. The pixel array of the first sensing area CA includes a pixel area (second pixel area) in which a plurality of pixel groups PG spaced by the light transmitting part and thus having a relatively low PPI are arranged. In the first sensing area CA, external light may pass through the display panel 100 through the light transmitting part having a high light transmittance and may be received by an imaging element module below the display panel 100.
Since the display area DA and the first sensing area CA include pixels, an input image is reproduced on the display area DA and the first sensing area CA.
Each of the pixels of the display area DA and the first sensing area CA include sub-pixels having different colors to realize the color of the image. Sub-pixels include a red sub-pixel (hereinafter, referred to as an “R sub-pixel”), a green sub-pixel (hereinafter, referred to as a “G sub-pixel”), and a blue sub-pixel (hereinafter, referred to as a “B sub-pixel”). Although not illustrated, each of pixels P may further include a white sub-pixel (hereinafter, a “W sub-pixel”). Each of the sub-pixels may include a pixel circuit and a light emitting element OLED.
The first sensing area CA includes the pixels and the imaging element module disposed below the screen of the display panel 100. A lens 30 of the imaging element module displays an input image by writing pixel data of the input image in the pixels of the first sensing area CA in a display mode. The imaging element module captures an external image in an imaging mode and outputs a picture or moving image data. The lens 30 of the imaging element module faces the first sensing area CA. The external light is incident on the lens 30 of the imaging element module, and the lens 30 collects the light in an image sensor that is omitted in the drawings. The imaging element module captures an external image in the imaging mode and outputs a picture or moving image data.
In order to secure the transmittance, an image quality compensation algorithm for compensating for the luminance and color coordinates of pixels in the first sensing area CA may be applied due to pixels removed from the first sensing area CA.
In the present disclosure, since the low-resolution pixels are arranged in the first sensing area CA, a display area of the screen is not limited in relation to the imaging element module, and thus a full-screen display can be implemented.
The display panel 100 has a width in an X-axis direction, a length in a Y-axis direction, and a thickness in a Z-axis direction. The display panel 100 includes a circuit layer 12 disposed on a substrate 10 and a light emitting element layer 14 disposed on the circuit layer 12. A polarizing plate 18 may be disposed on the light emitting element layer 14, and a cover glass 20 may be disposed on the polarizing plate 18.
The circuit layer 12 may include a pixel circuit connected to wirings such as data lines, gate lines, and power lines, a gate drive part connected to the gate lines, and the like. The circuit layer 12 may include circuit elements such as a transistor implemented as a thin film transistor (TFT) and a capacitor. The wirings and circuit elements of the circuit layer 12 may be formed of a plurality of insulating layers, two or more metal layers separated with the insulating layers therebetween, and an active layer including a semiconductor material.
The light emitting element layer 14 may include a light emitting element driven by the pixel circuit. The light emitting element may be implemented as an organic light emitting diode (OLED). The OLED includes an organic compound layer formed between an anode and a cathode. The organic compound layer may include a hole injection layer HIL, a hole transport layer HTL, an emission layer EML, an electron transport layer ETL, and an electron injection layer EIL, but the present disclosure is not limited thereto. When a voltage is applied to the anode and the cathode of the OLED, holes passing through the hole transport layer HTL and electrons passing through the electron transport layer ETL are moved to the emission layer EML to form excitons, and thus visible light is emitted from the emission layer EML. The light emitting element layer 14 may be disposed on pixels that selectively transmit light having red, green, and blue wavelengths and may further include a color filter array.
The light emitting element layer 14 may be covered with a protective film, and the protective film may be covered with an encapsulation layer. The protective layer and the encapsulation layer may have a structure in which an organic film and an inorganic film are alternately stacked. The inorganic film blocks permeation of moisture or oxygen. The organic film planarizes the surface of the inorganic film. When the organic film and the inorganic film are stacked in multiple layers, a movement path of the moisture or oxygen is longer than that of a single layer, and thus the permeation of the moisture/oxygen affecting the light emitting element layer 14 can be effectively blocked.
The polarizing plate 18 may adhere to the encapsulation layer. The polarizing plate 18 improves outdoor visibility of the display device. The polarizing plate 18 reduces an amount of light reflected from the surface of the display panel 100, blocks the light reflected from metal of the circuit layer 12, and thus improves the brightness of pixels. The polarizing plate 18 may be implemented as a linear polarizing plate and a phase delay film bonded to each other, or a circular polarizing plate.
In the display panel of the present disclosure, each pixel area of the display area DA and the first sensing area CA includes a light shielding layer. The light shielding layer is removed from the light transmitting part of the first sensing area to define the light transmitting part. The light shielding layer includes an opening hole corresponding to a light transmitting part area. The light shielding layer is removed from the opening hole. The light shielding layer is formed of a metal or inorganic film having a lower absorption coefficient than that of the metal removed from the light transmitting part with respect to the wavelength of a laser beam used in a laser ablation process of removing a metal layer present in the light transmitting part.
Referring to
Referring to
The pixel group PG may include one or two pixels. Each of the pixels of the pixel group PG may include two to four sub-pixels. For example, one pixel in the pixel group PG may include R, G, and B sub-pixels or may include two sub-pixels and may further include a W sub-pixel. In an example of
A distance D3 between the light transmitting parts AG is smaller than a distance D1 between the pixel groups PG. A distance D2 between the sub-pixels is smaller than the distance D1 between the pixel groups PG.
The shape of the light transmitting parts AG is illustrated as a circular shape in
Referring to
The pixel array of the display panel 100 includes data lines DL, gate lines GL intersecting the data lines DL, and pixels P defined by the data lines DL and the gate lines GL and arranged in a matrix form. The pixel array further includes power lines such as a VDD line PL1, a Vini line PL2, and a VSS line PL3 illustrated in
As illustrated in
The screen on which the input image is reproduced on the display panel 100 includes the display area DA and the first sensing area CA.
Sub-pixels of each of the display area DA and the first sensing area CA include pixel circuits. The pixel circuit may include a drive element that supplies a current to the light emitting element OLED, a plurality of switch elements that sample a threshold voltage of the drive element and switch a current path of the pixel circuit, a capacitor that maintains a gate voltage of the drive element, and the like. The pixel circuit is disposed below the light emitting element OLED.
The first sensing area CA includes the light transmitting parts AG arranged between the pixel groups PG and an imaging element module 400 disposed below the first sensing area CA. The imaging element module 400 photoelectrically converts light incident through the first sensing area CA in the imaging mode using the image sensor, converts the pixel data of the image output from the image sensor into digital data, and outputs the captured image data.
The display panel drive unit writes the pixel data of the input image to the pixels P. The pixels P may be interpreted as a pixel group PG including a plurality of sub-pixels.
The display panel drive unit includes a data drive unit 306, which supplies a data voltage of the pixel data to the data lines DL, and a gate drive unit 120 that sequentially supplies a gate pulse to the gate lines GL. The data drive unit 306 may be integrated in a drive IC 300. The display panel drive unit may further include a touch sensor drive unit that is omitted in the drawings.
The drive IC 300 may adhere to the display panel 100. The drive IC 300 receives pixel data of the input image and a timing signal from a host system 200, supplies a data voltage of the pixel data to the pixels, and synchronizes the data drive unit 306 and the gate drive unit 120.
The drive IC 300 is connected to the data lines DL through data output channels to supply the data voltage of the pixel data to the data lines DL. The drive IC 300 may output a gate timing signal for controlling the gate drive unit 120 through gate timing signal output channels. The gate timing signal generated from a timing controller 303 may include a gate start pulse VST, a gate shift clock CLK, and the like. The gate start pulse VST and the gate shift clock CLK swing between a gate-on voltage VGL and a gate-off voltage VGH. The gate timing signals VST and CLK output from a level shifter 307 are applied to the gate drive unit 120 to control a shift operation of the gate drive unit 120.
The gate drive unit 120 may include a shift register formed on the circuit layer of the display panel 100 together with the pixel array. The shift register of the gate drive unit 120 sequentially supplies a gate signal to the gate lines GL under control of the timing controller 303. The gate signal may include a scan pulse and an EM pulse of a light emission signal. The shift register may include a scan drive unit that outputs the scan pulse and an EM drive unit that outputs the EM pulse. In
The drive IC 300 may be connected to the host system 200, a first memory 301, and the display panel 100. The drive IC 300 may include a data reception and calculation unit 308, the timing controller 303, the data drive unit 306, a gamma compensation voltage generation unit 305, a power supply unit 304, a second memory 302, and the like.
The data reception and calculation unit 308 includes a reception unit that receives the pixel data input as a digital signal from the host system 200, and a data calculation unit that processes the pixel data input through the reception unit to improve image quality. The data calculation unit may include a data decoding unit that decodes and restores compressed pixel data, an optical compensation unit that adds a preset optical compensation value to the pixel data, and the like. The optical compensation value may be set as a value for correcting the luminance of each pixel data on the basis of the luminance of the screen measured on the basis of a camera image captured in a manufacturing process.
The timing controller 303 provides, to the data drive unit 306, the pixel data of the input image received from the host system 200. The timing controller 303 generates a gate timing signal for controlling the gate drive unit 120 and a source timing signal for controlling the data drive unit 306 to control the operation timing of the gate drive unit 120 and the data drive unit 306.
The timing controller 303 according to the embodiment generates a reference voltage control signal CREF for controlling a reference voltage according to the PPI and provides the reference voltage control signal CREF to the power supply unit 304. Since the display area in which pixels are arranged at a high PPI and the first sensing area in which pixels are arranged at a low PPI are predefined, the timing controller 303 may control the reference voltage to be provided to the pixels arranged at the high PPI and the pixels arranged at the low PPI according to a scan direction while a scan is in progress.
For example, the second reference voltage varies between the first voltage level and the second voltage level. The timing controller 303 generates a first reference voltage control signal when the second reference voltage is changed from the first voltage level to the second voltage level and generates a second reference control signal when the second reference voltage is changed from the second voltage level to the first voltage level.
The power supply unit 304 generates, using a direct current (DC)-DC converter, power required for driving the pixel array of the display panel 100, the gate drive unit 120, and the drive IC 300. The DC-DC converter may include a charge pump, a regulator, a Buck converter, a boost converter, and the like. The power supply unit 304 may adjust a DC input voltage received from the host system 200 to generate a DC power such as the reference voltage, the gate-on voltage VGL, the gate-off voltage VGH, a pixel drive voltage VDD, a low-potential power supply voltage VSS, and an initialization voltage Vini. The reference voltage is supplied to the gamma compensation voltage generation unit 305. The reference voltage includes the first reference voltage and the second reference voltage. The first reference voltage is supplied to a first gamma compensation voltage generation unit 305a, and the second reference voltage is supplied to a second gamma compensation voltage generation unit 305b. The gate-on voltage VGL and the gate-off voltage VGH are supplied to the level shifter 307 and the gate drive unit 120. Pixel powers, such as the pixel drive voltage VDD, the low-potential power supply voltage VSS, and the initialization voltage Vini, are commonly supplied to the pixels P. The initialization voltage Vini is set to a DC voltage that is lower than the pixel drive voltage VDD and lower than a threshold voltage of the light emitting element OLED to initialize main nodes of the pixel circuits and suppress light emission of the light emitting element OLED.
The gamma compensation voltage generation unit 305 divides the reference voltage supplied from the power supply unit 304 through a divider circuit to generate a gray scale-specific gamma compensation voltage. The gamma compensation voltage is an analog voltage that is set for each gray scale of the pixel data. The gamma compensation voltage output from the gamma compensation voltage generation unit 305 is provided to the data drive unit 306.
The gamma compensation voltage generation unit 305 according to the embodiment includes the first gamma compensation voltage generation unit 305a and the second gamma compensation voltage generation unit 305b. The first gamma compensation voltage generation unit 305a receives the first reference voltage to generate the first gamma compensation voltage for each gray scale, and the second gamma compensation voltage generation unit 305b receives the second reference voltage to generate the second gamma compensation voltage for each gray scale.
In this case, since a second data line group includes data lines connected to the pixels arranged at the high PPI and the pixels arranged at the low PPI in the second area of the screen, the second gamma compensation voltage generation unit 305b divides the second reference voltage to generate the second gamma compensation voltages that are different according to each PPI. For example, the second gamma compensation voltage generation unit 305b divides the first voltage level of the second reference voltage at the high PPI in the second area to generate a 2-1st gamma compensation voltage and divides the second voltage level of the second reference voltage at the low PPI to generate a 2-2nd gamma compensation voltage.
The first gamma compensation voltage generation unit 305a and the second gamma compensation voltage generation unit 305b may be independently controlled.
The data drive unit 306 converts digital data including the pixel data received from the timing controller 303 into a gamma compensation voltage through a digital-to-analog converter (DAC) and outputs the data voltage. The data voltage output from the data drive unit 306 is supplied to the data lines DL of the pixel array through an output buffer connected to a data channel of the drive IC 300.
The data drive unit 306 according to the embodiment includes a first data drive unit 306a and a second data drive unit 306b. Each channel of the first data drive unit 306a and the second data drive unit 306b includes a DAC and an output buffer. The first data drive unit 306a converts, through the DAC, the digital data including the pixel data received from the timing controller 303 into the first gamma compensation voltage generated from the first gamma compensation voltage generation unit 305a and supplies the data voltage to a first data line group of the pixel array through the output buffer. While scanning the pixels arranged at the high PPI in the second area, the second data drive unit 306b supplies, to the second data line group of the pixel array through the output buffer, the data voltage obtained by converting, through the DAC, the digital data including the pixel data received from the timing controller 303 into a 2-1st gamma compensation voltage generated from the second gamma compensation voltage generation unit 305b. While scanning the pixels arranged at the low PPI in the second area, the second data drive unit 306b supplies, to the second data line group of the pixel array through the output buffer, the data voltage obtained by converting, through the DAC, the digital data including the pixel data received from the timing controller 303 into a 2-2nd gamma compensation voltage generated from the second gamma compensation voltage generation unit 305b.
When power is input to the drive IC 300, the second memory 302 stores a compensation value, register setting data, and the like received from the first memory 301. The compensation value may be applied to various algorithms for improving image quality. The compensation value may include an optical compensation value. The register setting data defines operations of the data drive unit 306, the timing controller 303, the gamma compensation voltage generation unit 305, and the like. The first memory 301 may include a flash memory. The second memory 302 may include a static random access memory (SRAM).
The host system 200 may be implemented as an application processor (AP). The host system 200 may transmit pixel data of the input image to the drive IC 300 through a mobile industry processor interface (MIPI). The host system 200 may be connected to the drive IC 300 through a flexible printed circuit (FPC).
Meanwhile, the display panel 600 may be implemented as a flexible panel that may be applied to a flexible display. In the flexible display, the size of the screen may be changed by winding, folding, and bending the flexible panel, and the flexible display may be easily manufactured in various designs. The flexible display may be implemented as a rollable display, a foldable display, a bendable display, a slidable display, and the like. The flexible panel may be manufactured as a so-called “plastic OLED panel.” The plastic OLED panel may include a back plate and a pixel array on an organic thin film bonded to the back plate. The touch sensor array may be formed on the pixel array.
The back plate may be a polyethylene terephthalate (PET) substrate. The pixel array and the touch sensor array may be formed on the organic thin film. The back plate may block permeation of moisture toward the organic thin film so that the pixel array is not exposed to the moisture. The organic thin film may be a polyimide (PI) substrate. A multi-layered buffer film may be formed of an insulating material that is not illustrated on the organic thin film. The circuit layer 12 and the light emitting element layer 14 may be stacked on the organic thin film.
In the display device of the present disclosure, the pixel circuit, the gate drive unit, and the like arranged on the circuit layer 12 may include a plurality of transistors. The transistors may be implemented as an oxide TFT including an oxide semiconductor, a low temperature poly silicon (LTPS) TFT including an LTPS, and the like. The transistors may be implemented as a p-channel TFT or an n-channel TFT. In the embodiment, an example in which the transistors of the pixel circuit are implemented as the p-channel TFTs is mainly described, but the present disclosure is not limited thereto.
The transistor is a three-electrode element including a gate, a source, and a drain. The source is an electrode through which a carrier is supplied to the transistor. In the transistor, the carrier starts to flow from the source. The drain is an electrode through which the carrier moves to the outside of the transistor. In the transistor, the carrier flows from the source to the drain. In an n-channel transistor, since the carrier is an electron, a source voltage is lower than a drain voltage so that the electron may flow from the source to the drain. In the n-channel transistor, a current flows from the drain to the source. In a p-channel transistor PMOS, since the carrier is a hole, the source voltage is higher than the drain voltage so that the hole flows from the source to the drain. In the p-channel transistor, since the hole flows from the source to the drain, the current flows from the source to the drain. It should be noted that the source and the drain of the transistor are not fixed. For example, the source and the drain may be changed according to an applied voltage. Thus, the present disclosure is not limited in relation to the source and the drain of the transistor. In the following description, the source and the drain of the transistor will be referred to as first and second electrodes.
The gate pulse swings between the gate-on voltage and the gate-off voltage. The gate-on voltage is set to a voltage higher than a threshold voltage of the transistor, and the gate-off voltage is set to a voltage lower than the threshold voltage of the transistor. The transistor is turned on in response to the gate-on voltage and is turned off in response to the gate-off voltage. In the n-channel transistor, the gate-on voltage may be a gate high voltage VGH, and the gate-off voltage may be a gate low voltage VGL. In the p-channel transistor, the gate-on voltage may be the gate low voltage VGL, and the gate-off voltage may be the gate high voltage VGH.
The drive element of the pixel circuit may be implemented as a transistor. In the drive element, electrical characteristics between all pixels should be uniform but may be different due to process deviations and element characteristic deviations and may vary as a display driving time elapses. In order to compensate for the electrical characteristic deviations, the display device may include an internal compensation circuit and an external compensation circuit. The internal compensation circuit samples a threshold voltage Vth and/or mobility μ of the drive element, which is added to the pixel circuit in each of the sub-pixels and changes according to electrical characteristics of the drive element and compensates for the change in real time. The external compensation circuit transmits, to an external compensation unit, the threshold voltage and/or mobility of the drive element detected through a sensing line connected to each of the sub-pixels. A compensation unit of the external compensation circuit compensates for changes in electric characteristics of the drive element by modulating the pixel data of the input image by reflecting the sensing result. The voltage of the pixel that changes according to electrical characteristics of an external compensation drive element is detected, and an external circuit modulates the data of the input image on the basis of the detected voltage, thereby compensating for electrical characteristic deviation of the drive element between the pixels.
Referring to
As illustrated in
During the initialization period Tini, a (N−1)th scanning pulse SCAN(N−1) is generated as a pulse of the gate-on voltage VGL, and a voltage of each of a Nth scanning pulse SCAN(N) and a light emission pulse EM(N) is the gate-off voltage VGH. During the sampling period Tsam, the Nth scanning pulse SCAN(N) is generated as the pulse of the gate-on voltage VGL, and a voltage of each of the (N−1)th scanning pulse SCAN(N−01) and the light emission pulse EM(N) is the gate-off voltage VGH. During at least a part of the light emission period Tem, the light emission pulse EM(N) is generated as the gate-on voltage VGL, and a voltage of each of the (N−1)th scanning pulse SCAN(N−1) and the Nth scanning pulse SCAN(N) is generated as the gate-off voltage VGH.
During the initialization, the fifth switch element M5 is turned on according to the gate-on voltage VGL of the (N−1)th scanning pulse SCAN(N−1) so as to initialize the pixel circuit. During the sampling period Tsam, the first and second switch elements M1 and M2 are turned on according to the gate-on voltage VGL of the Nth scanning pulse SCAN(N), and thus a threshold voltage of the drive element DT is sampled and stored in a storage capacitor Cst1. At the same time, the sixth switch element M6 is turned on during the sampling period Tsam to lower the voltage of a fourth node n4 to a reference voltage Vref so as to suppress light emission of the light emitting element OLED. During the light emission period Tem, the third and fourth switch elements M3 and M4 are turned on, and thus the light emitting element OLED emits light. In the light emission period Tem, in order to precisely express the luminance of a low gray scale with a duty ratio of the light emission pulse EM(N), the light emission pulse EM(N) swings at a predetermined duty ratio between the gate-on voltage VGL and the gate-off voltage VGH, and thus the third and fourth switch elements M3 and M4 may be repeatedly turned on and off.
The light emitting element OLED may be implemented as an OLED or an inorganic light emitting diode. Hereinafter, an example in which the light emitting element OLED is implemented as an OLED will be described.
The light emitting element OLED may include an organic compound layer formed between an anode and a cathode. The organic compound layer may include a hole injection layer HIL, a hole transport layer HTL, an emission layer EML, an electron transport layer ETL, and an electron injection layer EIL, but the present disclosure is not limited thereto. When a voltage is applied to an anode electrode and a cathode electrode of the OLED, holes passing through the hole transport layer HTL and electrons passing through the electron transport layer ETL are moved to the emission layer EML to form excitons, and thus visible light is emitted from the emission layer EML.
The anode electrode of the light emitting element OLED is connected to the fourth node n4 between the fourth and sixth switch elements M4 and M6. The fourth node n4 is connected to the anode of the light emitting element OLED, a second electrode of the fourth switch element M4, and a second electrode of the sixth switch element M6. The cathode electrode of the light emitting element OLED is connected to a VSS line PL3 to which the low-potential power supply voltage VSS is applied. The light emitting element OLED emits light with a current Ids that flows due to a gate-source voltage Vgs of the drive element DT. A current path of the light emitting element OLED is switched by the third and fourth switch elements M3 and M4.
The storage capacitor Cst1 is connected between the VDD line PL1 and a first node n1. A data voltage Vdata compensated for by the threshold voltage Vth of the drive element DT is charged to the storage capacitor Cst1. Since the data voltage in each of the sub-pixels is compensated for by the threshold voltage Vth of the drive element DT, deviations in characteristics of the drive element DT are compensated for in the sub-pixels.
The first switch element M1 is turned on in response to the gate-on voltage VGL of the Nth scanning pulse SCAN(N) to connect a second node n2 and a third node n3. The second node n2 is connected to a gate electrode of the drive element DT, a first electrode of the storage capacitor Cst1, and a first electrode of the first switch element M1. The third node n3 is connected to a second electrode of the drive element DT, a second electrode of the first switch element M1, and a first electrode of the fourth switch element M4. A gate electrode of the first switch element M1 is connected to a first gate line GL1 to receive the Nth scanning pulse SCAN(N). The first electrode of the first switch element M1 is connected to the second node n2, and the second electrode of the first switch element M1 is connected to the third node n3.
Since the first switch element M1 is turned on only during a very short horizontal period 1H in which the Nth scanning pulse SCAN(N) is generated as the gate-on voltage VGL in one frame period and thus maintains an OFF state for approximately one frame period, a leakage current may occur in the OFF state of the first switch element M1. In order to suppress the leakage current of the first switch element M1, as illustrated in
The second switch element M2 is turned on in response to the gate-on voltage VGL of the Nth scanning pulse SCAN(N) to supply the data voltage Vdata to the first node n1. A gate electrode of the second switch element M2 is connected to the first gate line GL1 to receive the Nth scanning pulse SCAN(N). A first electrode of the second switch element M2 is connected to the first node n1. A second electrode of the second switch element M2 is connected to the data lines DL to which the data voltage Vdata is applied. The first node n1 is connected to the first electrode of the second switch element M2, a second electrode of the third switch element M3, and a first electrode of the drive element DT.
The third switch element M3 is turned on in response to the gate-on voltage VGL of the light emission pulse EM(N) to connect the VDD line PL1 to the first node n1. A gate electrode of the third switch element M3 is connected to a third gate line GL3 to receive the light emission pulse EM(N). A first electrode of the third switch element M3 is connected to the VDD line PL1. The second electrode of the third switch element M3 is connected to the first node n1.
The fourth switch element M4 is turned on in response to the gate-on voltage VGL of the light emission pulse EM(N) to connect the third node n3 to the anode of the light emitting element OLED. A gate electrode of the fourth switch element M4 is connected to the third gate line GL3 to receive the light emission pulse EM(N). The first electrode of the fourth switch element M4 is connected to the third node, and the second electrode thereof is connected to the fourth node n4.
The fifth switch element M5 is turned on in response to the gate-on voltage VGL of the (N−1)th scanning pulse SCAN(N−1) to connect the second node to the Vini line PL2. A gate electrode of the fifth switch element M5 is connected to the second gate line GL2 to receive the (N−1)th scanning pulse SCAN(N−1). A first electrode of the fifth switch element M5 is connected to the second node n2, and a second electrode thereof is connected to the Vini line PL2. In order to suppress the leakage current of the fifth switch element M5, as illustrated in
The sixth switch element M6 is turned on in response to the gate-on voltage VGL of the Nth scanning pulse SCAN(N) to connect the Vini line PL2 to the fourth node n4. A gate electrode of the sixth switch element M6 is connected to the first gate line GL1 to receive the Nth scanning pulse SCAN(N). A first electrode of the sixth switch element M6 is connected to the Vini line PL2, and the second electrode thereof is connected to the fourth node n4.
The drive element DT drives the light emitting element OLED by adjusting the current Ids flowing in the light emitting element OLED according to the gate-source voltage Vgs. The drive element DT includes a gate connected to the second node n2, the first electrode connected to the first node, and the second electrode connected to the third node n3.
During the initialization period Tini, as illustrated in
During the sampling period Tsam, the Nth scanning pulse SCAN(N) is generated as the gate-on voltage VGL. The pulse of the Nth scanning pulse SCAN(N) is synchronized with the data voltage Vdata of a Nth pixel line. During the sampling period Tsam, the (N−1)th scanning pulse SCAN(N−1) and the light emission pulse EM(N) maintain the gate-off voltage VGH. Thus, during the sampling period Tsam, the first and second switch elements M1 and M2 are turned on.
During the sampling period Tsam, a gate voltage DTG of the drive element DT is increased by a current flowing through the first and second switch elements M1 and M2. When the drive element DT is turned off, the gate node voltage DTG is Vdata−|Vth|. In this case, the voltage of the first node n1 is Vdata−|Vth|. During the sampling period Tsam, the gate-source voltage Vgs of the drive element DT is |Vgs|=Vdata−(Vdata−|Vth|)=|Vth|.
During the light emission period Tem, the light emission pulse EM(N) may be generated as the gate-on voltage VGL. During the light emission period Tem, in order to improve low gray scale expression, the light emission pulse EM(N) is turned on and off at a predetermined duty ratio and thus may swing between the gate-on voltage VGL and the gate-off voltage VGH. Thus, during at least a part of the light emission period Tem, the light emission pulse EM(N) may be generated as the gate-on voltage VGL.
When the light emission pulse EM(N) is the gate-on voltage VGL, a current flows between the VDD and the light emitting element OLED, and thus the light emitting element OLED may emit light. During the light emission period Tem, the (N−1)th and Nth scanning pulses SCAN(N−1) and SCAN(N) maintain the gate-off voltage VGH. During the light emission period Tem, the third and fourth switch elements M3 and M4 are repeatedly turned on and off according to the voltage of the light emission signal EM. When the light emission pulse EM(N) is the gate-on voltage VGL, the third and fourth switch elements M3 and M4 are turned on, and thus the current flows in the light emitting element OLED. In this case, Vgs of the drive element DT is |Vgs|=VDD−(Vdata−|Vth|), and the current flowing in the light emitting element OLED is K(VDD−Vdata)2. K denotes a constant value determined by the charge mobility, the parasitic capacitance, the channel capacity, and the like of the drive element DT.
Referring to
Here, the first data line group DL1 includes data lines connected to the pixels arranged at the high PPI in the first area, and the second data line group DL2 includes data lines connected to the pixels arranged at the high PPI and the pixels arranged at the low PPI in the second area.
Here, an example case in which the first sensing area CA is formed in the middle of the display area DA has been described, but the present disclosure is not limited thereto, and the first sensing area CA may be formed in various locations.
Since the PPI of the first sensing area CA is larger than the PPI of the display area DA, the luminance of the first sensing area CA may be lower than the luminance of the display area DA when the pixels of the display area DA and the pixels of the first sensing area CA are driven in a dynamic range of the same data voltage in the same gray scale. Thus, in the embodiment, an attempt is made to increase the luminance of the pixels in the first sensing area CA by expanding the dynamic range of the data voltage applied to the pixels of the first sensing area CA.
Referring to
Referring to
Referring to
In the embodiment, an example case in which the pixel circuit is implemented as a p-type transistor is described, and thus the gamma compensation voltage of the high-gray scale data voltage may be implemented as a negative gamma compensation voltage.
For example, when a transistor that drives the light emitting elements of the pixels is implemented as a p-channel metal oxide semiconductor field effect transistor (MOSFET), and when the data voltage is applied to a gate of the transistor, the negative gamma compensation voltage is generated. Thus, as the gray scale of pixel data RGB becomes larger, the gamma compensation voltage becomes smaller.
In this case, the first reference voltage and the second reference voltage may have different dynamic ranges. For example, the dynamic range of the second reference voltage is set to be larger than the dynamic range of the first reference voltage.
In the embodiment, an analog reference voltage may be varied so that a constant slope is provided over time at a boundary portion of the first sensing area CA, thereby additionally compensating for a boundary portion of a photographing area.
Referring to
For example, an area in which the reference voltage varies may be the display area DA, the first sensing area CA, and an area including the display area DA and the first sensing area CA.
The fact that the analog reference voltage has a constant slope over time in the boundary portion means that the dynamic range of the data voltage applied to pixels adjacent to the boundary portion, that is, the pixels in the display area or the pixels in the first sensing area, is gradually expanded. Thus, the luminance gradually increases at the boundary portion between the display area DA and the first sensing area CA.
Referring to
The analog reference voltage varies in an area in which the pixels are arranged at the high PPI.
Referring to
The analog reference voltage varies in an area in which the pixels are arranged at the low PPI.
Referring to
The analog reference voltage is varied over an area in which the pixels are arranged at the high PPI and an area in which the pixels are arranged at the low PPI.
In this case, a section in which the analog reference voltage varies may be the boundary area, but the present disclosure is not limited thereto. Since the purpose of the compensation of the boundary portion is to reduce the recognition of the boundary portion in an image, an optimum variable shape can be obtained through experiment cognitive evaluation. For example, it may be designed that a section in which the analog reference voltage varies is started or terminated at the boundary portion as well as the analog reference voltage increasing rapidly or stepwise instead of the constant slope.
In this way, in the second data line group, a reference voltage may vary according to each PPI. To this end, in the embodiment, the gamma compensation voltage generation unit connected to the respective data line groups, that is, the first data line group and the second data line group, is separately configured.
Referring to
For example, when a transistor that drives the light emitting elements, that is, an OLED, of the pixels is implemented as an n-channel MOSFET, and when the data voltage is applied to a gate of the transistor, the positive gamma compensation voltage is generated. Thus, as the gray scale of the pixel data RGB becomes larger, the gamma compensation voltage becomes smaller.
In this case, the section in which the analog reference voltage varies may be the boundary portion, but the present disclosure is not limited thereto.
Such a drive IC that provides the gamma compensation voltage of the entire gray scale is applied to a mobile device and a television (TV). A configuration of the drive IC is applied to the mobile device and the TV in different forms. In the mobile device, the gamma reference voltage is generated inside the drive IC by external control, and the compensation voltage for the entire gray scale is generated on the basis of the generated gamma reference voltage. In the TV, the gamma reference voltage generated by an external device is used to generate the compensation voltage for the entire gray scale in the drive IC. In this case, in the mobile device, a high-gray scale data voltage is changed by an external device using a code, and in the TV, the high-gray scale data voltage is changed and provided by an external device.
Referring to
The first circuit unit 51 divides the reference voltage VREFL input from a power supply unit 136 and determines the first gamma reference voltage GMA1, the eighth gamma reference voltage GMA8, and the ninth gamma reference voltage GMA9 on the basis of the divided voltages. The voltage levels of the gamma reference voltages GMA1, GMA8, and GMA9 may be adjusted according to register setting values RGMA1, RGMA8, and RGMA9. The first circuit unit 51 includes a first voltage divider circuit RS1, voltage selection units MUX11 to MUX13, and a plurality of buffers BUF11 to BUF13.
The first voltage divider circuit RS1 receives the gamma reference voltage VREFL from the power supply unit 136. The first voltage divider circuit RS1 divides the gamma reference voltage VREFL using an R string circuit including resistors connected in series.
The voltage selection units include a multiplexer MUX11 that selects the first gamma reference voltage GMA1 from the voltages divided by the first voltage divider circuit RS1 according to the register setting value RGMA1, a multiplexer MUX13 that selects the eighth gamma reference voltage GMA8 from the voltages divided by the first voltage divider circuit RS1 according to the register setting value RGMA8, and a multiplexer MUX12 that selects the ninth gamma reference voltage GMA9 from voltages divided by the first voltage divider circuit RS1 according to the register setting value RGMA9.
The first gamma reference voltage GMA1 is the uppermost gamma compensation voltage. The ninth gamma reference voltage GMA9 is the lowermost gamma compensation voltage. The eighth gamma reference voltage GMA8 is a gamma tab voltage that is higher than the ninth gamma reference voltage GMA9.
The second circuit unit 52 receives the first gamma reference voltage GMA1 and the eighth gamma reference voltage GMA8 input from the first circuit unit 51, divides the first gamma reference voltage GMA1, and determines the second to eighth gamma reference voltages GMA2 to GMA8. The voltage levels of the gamma reference voltages GMA2 to GMA7 may be adjusted according to the register setting values RGMA2 to RGMA7.
The second circuit unit 52 includes a second voltage divider circuit RS2, voltage selection units MUX21 to MUX27, and a plurality of buffers BUF21 to BUF27.
The second voltage divider circuit RS2 is divided into 2-1st to 2-6th voltage divider circuits RS21 to RS26. Each of the 2-1st to 2-6th voltage divider circuits RS21 to RS26 divides an input voltage using the R string circuit including resistors connected in series. The voltage selection units MUX21 to MUX26 include a 2-1st multiplexer MUX21 connected between the 2-1st voltage divider circuit RS21 and the 2-1st buffer BUF21, a 2-2nd multiplexer MUX22 connected between the 2-2nd voltage divider circuit RS22 and the 2-2nd buffer BUF22, a 2-3rd multiplexer MUX23 connected between the 2-3rd voltage divider circuit RS23 and the 2-3rd buffer BUF23, a 2-4th multiplexer MUX24 connected between the 2-4th voltage divider circuit RS24 and the 2-4th buffer BUF24, a 2-5th multiplexer MUX25 connected between the 2-5th voltage divider circuit RS25 and the 2-5th buffer BUF25, and a 2-6th multiplexer MUX26 connected between the 2-6th voltage divider circuit RS26 and the 2-6th buffer BUF26.
The 2-1st voltage divider circuit RS21 receives the first gamma reference voltage GMA1 and the eighth gamma reference voltage GMA8, divides the first gamma reference voltage GMA1, and outputs different voltages through nodes between resistors. The 2-1st multiplexer MUX21 selects, as the second gamma reference voltage GMA2, one of the voltages divided by the 2-1st voltage divider circuit RS21 according to the register setting RGMA2. The 2-1st buffer BUF21 supplies the second gamma reference voltage GMA2 input from the 2-1st multiplexer MUX21 to a node between a 3-1st voltage divider circuit RS31 and a 3-2nd voltage divider circuit RS32.
The 2-2nd voltage divider circuit RS22 receives the second gamma reference voltage GMA2 and the eighth gamma reference voltage GMA8, divides the second gamma reference voltage GMA2, and outputs different voltages through nodes between resistors. The 2-2nd multiplexer MUX22 selects, as the third gamma reference voltage GMA3, one of the voltages divided by the 2-2nd voltage divider circuit RS22 according to the register setting RGMA3. The 2-2nd buffer BUF22 supplies the third gamma reference voltage GMA3 input from the 2-2nd multiplexer MUX22 to a node between a 3-2nd voltage divider circuit RS32 and a 3-3rd voltage divider circuit RS33.
The 2-6th voltage divider circuit RS26 receives the sixth gamma reference voltage GMA6 and the eighth gamma reference voltage GMA8, divides the sixth gamma reference voltage GMA6, and outputs different voltages through nodes between resistors. The 2-6th multiplexer MUX26 selects, as the seventh gamma reference voltage GMA7, one of the voltages divided by the 2-6th voltage divider circuit RS26 according to the register setting RGMA7. The 2-6th buffer BUF26 supplies the seventh gamma reference voltage GMA7 input from the 2-6th multiplexer MUX26 to a node between a 3-6th voltage divider circuit RS36 and a 3-7th voltage divider circuit RS37.
The third circuit unit 53 receives the gamma reference voltages GMA1 to GMA9, divides the gamma reference voltages GMA1 to GMA9 and outputs gamma compensation voltages of the entire gray scale that may be expressed in the pixel data of the input image. The third circuit unit 53 includes a third voltage divider circuit RS3.
Each of the 3-1st to 3-8th voltage divider circuits RS31 to RS38 divides an input voltage using the R string circuit including resistors connected in series. The 3-1st voltage divider circuit RS31 divides the first gamma reference voltage GMA1 and the second gamma reference voltage GMA2 and outputs gray scale-specific gamma compensation voltages between the first gamma reference voltage GMA1 and the second gamma reference voltage GMA2. The 3-2nd voltage divider circuit RS32 divides the second gamma reference voltage GMA2 and the third gamma reference voltage GMA3 and outputs gray scale-specific gamma compensation voltages between the second gamma reference voltage GMA2 and the third gamma reference voltage GMA3. The 3-6th voltage divider circuit RS36 divides the sixth gamma reference voltage GMA6 and the seventh gamma reference voltage GMA7 and outputs gray scale-specific compensation voltages between the sixth gamma reference voltage GMA6 and the seventh gamma reference voltage GMA7. The 3-7th voltage divider circuit RS37 divides the seventh gamma reference voltage GMA7 and the eighth gamma reference voltage GMA8 and outputs gray scale-specific compensation voltages between the seventh gamma reference voltage GMA7 and the eighth gamma reference voltage GMA8. The 3-8th voltage divider circuit RS38 divides the eighth gamma reference voltage GMA8 and the ninth gamma reference voltage GMA9 and outputs gray scale-specific gamma compensation voltages between the eighth gamma reference voltage GMA8 and the ninth gamma reference voltage GMA9.
In this case, when the pixel circuit is implemented as a p-type transistor, the gamma reference voltage VREFH may be commonly used, and when the pixel circuit is implemented as an n-type transistor, the gamma reference voltage VREFL may be commonly used.
Referring to
The gamma compensation voltage generation unit according to the embodiment is configured by connecting the gamma compensation voltage generation unit illustrated in
Here, the first gamma compensation voltage generation unit 305a receives a first reference voltage VREFL1 from the power supply unit 304 to generate a gamma reference voltage and generates a gray scale-specific first gamma compensation voltage using the gamma reference voltage, and the second gamma compensation voltage generation unit 305b receives a second reference voltage VREFL2 from the power supply unit 304 to generate a gamma reference voltage and generates gray scale-specific second gamma compensation voltages different according to each PPI using the gamma reference voltage.
The second gamma compensation voltage generation unit 305b divides the first voltage level of the second reference voltage to generate the gamma reference voltage and generates a gray scale-specific 2-1st gamma compensation voltage using the gamma reference voltage.
The second gamma compensation voltage generation unit 305b divides the second voltage level of the second reference voltage to generate the gamma reference voltage and generates a gray scale-specific 2-2nd gamma compensation voltage using the gamma reference voltage.
Referring to
The first circuit unit 51 and the second circuit unit 52 are provided outside the drive IC 300, and the third circuit unit 53 is provided inside the drive IC 300. Thus, the first circuit unit 51 and the second circuit unit 52 outside the drive IC 300 generate the gamma reference voltages GMA1 to GMA9 to provide the generated gamma reference voltages GMA1 to GMA9 to the third circuit unit 53 inside the drive IC 300, and the third circuit unit 53 inside the drive IC 300 divides the supplied gamma reference voltages GMA1 to GMA9 to generate the gamma compensation voltage for the entire gray scale.
Referring to
The gamma compensation voltage generation units 305a and 305b according to the embodiment are configured by connecting the gamma compensation voltage generation unit illustrated in
Here, the third circuit unit 53a of the first gamma compensation voltage generation unit 305a receives a gamma reference voltage from the outside of the drive IC 30 to generate a gray scale-specific first gamma compensation voltage, and the third circuit unit 53b of the second gamma compensation voltage generation unit 305b receives a gamma reference voltage from the outside of the drive IC 300 to generate gray scale-specific second gamma compensation voltages different according to each PPI.
The second gamma compensation voltage generation unit 305b divides the first voltage level of the second reference voltage to generate the gamma reference voltage and generates a gray scale-specific 2-1st gamma compensation voltage using the gamma reference voltage.
The second gamma compensation voltage generation unit 305b divides the second voltage level of the second reference voltage to generate the gamma reference voltage and generates a gray scale-specific 2-2nd gamma compensation voltage using the gamma reference voltage.
Referring to
The first DAC DAC1 converts digital data including the pixel data received from the timing controller 303 into a first gamma compensation voltage to output a data voltage. The first output buffer BUF1 is connected to an output node of the first DAC DAC1 to supply the data voltage output from the first DAC DAC1 to the data lines DL of the pixel array.
The second DAC DAC2 converts digital data including the pixel data received from the timing controller 303 into the first gamma compensation voltage to output a data voltage or converts the digital data into the second gamma compensation voltage to output the data voltage. The second output buffer BUF2 is connected to an output node of the second DAC DAC2 to supply the data voltage output from the second DAC DAC2 to the data lines DL of the pixel array.
Referring to
In the display area DA and the second sensing area SA, each sub-pixel of display pixels includes a pixel circuit. The pixel circuit may include a drive element that supplies a current to the light emitting element OLED, a plurality of switch elements that sample a threshold voltage of the drive element and switch a current path of the pixel circuit, a capacitor that maintains a gate voltage of the drive element, and the like.
The second sensing area SA includes pixels in which the pixel data is written and sensor pixels S spaced apart from each other at a predetermined interval with the pixels interposed therebetween. The sensor pixels S include photosensors and a photosensor drive circuit that drives the photosensors. The display pixels in the second sensing area SA emit light according to the data voltage of the pixel data in the display mode to display input data but emit light with high luminance according to a voltage of a light source driving data and are thus driven as light sources in a fingerprint recognition mode. The light source driving data is data irrelevant to the pixel data of the input image.
Referring to
The pixel group PG may include one or two pixels. Each of the pixels of the pixel group PG may include two to four sub-pixels. For example, one pixel in the pixel group PG may include R, G, and B sub-pixels or may include two sub-pixels and may further include a W sub-pixel. The first pixel PIX1 may be configured as R and G sub-pixels, and the second pixel PIX2 may be configured as B and G sub-pixels. Each of the photosensors S includes an organic/inorganic photo diode. Distances D4 between the adjacent photosensors S in four directions X, Y, Θx, and Θy are substantially the same. The X axis and the Y axis denote two orthogonal directions. Θx and Θy denote inclined axis directions shifted by 45 degrees from the X axis and Y axis, respectively.
Referring to
Referring to
In this way, it may be seen that in the second sensing area SA of the display device to which the fingerprint recognition module is applied, the photosensors S are arranged between the pixel groups PG and the adjacent pixel groups GP, and in the display mode in which the input image displayed, since only the pixels emit light, the pixels are arranged at the low PPI to correspond to a structure of the first sensing area CA in which the light transmitting parts AG are arranged between the pixel group PG and the adjacent pixel groups PG.
Thus, as proposed in the present disclosure, the screen may be divided into the first area including the pixels arranged at the high resolution and the second area including the pixels arranged at the high resolution and the pixels arranged at the low resolution, the first gamma compensation voltage generated by dividing the first reference voltage may be applied to the first area, and the different second gamma compensation voltages generated by dividing the first voltage level and the second voltage level of the second reference voltage according to each resolution may be applied to the second area.
Referring to
Sub-pixels of each of the display area, the first sensing area CA, and the second sensing area SA include pixel circuits. The pixel circuit may include the drive element that supplies a current to the light emitting element OLED, the plurality of switch elements that sample a threshold voltage of the drive element and switch a current path of the pixel circuit, the capacitor that maintains a gate voltage of the drive element, and the like.
The first sensing area CA includes the light transmitting parts AG arranged between the pixel groups PG and an imaging element module disposed below the first sensing area CA. The imaging element module photoelectrically converts light incident through the first sensing area CA in the imaging mode using the image sensor, converts the pixel data of the image output from the image sensor into digital data, and outputs the captured image data.
The second sensing area SA includes pixels in which the pixel data is written and sensor pixels spaced apart from each other at a predetermined interval with the pixels interposed therebetween. The sensor pixels include photosensors and a photosensor drive circuit that drives the photosensors. The display pixels in the second sensing area SA emit light according to the data voltage of the pixel data in the display mode to display the input data but emit light with high luminance according to the voltage of the light source driving data and are thus driven as light sources in the fingerprint recognition mode.
In this way, different gamma compensation voltages according to resolutions according to the embodiment of the present disclosure can be applied even to the display device to which both the imaging element module and the fingerprint recognition module are applied.
Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be embodied in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above-described embodiments are illustrative in all aspects and do not limit the present disclosure. The protective scope of the present disclosure should be construed based on the following claims, and all the technical concepts in the equivalent scope thereof should be construed as falling within the scope of the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2020-0107184 | Aug 2020 | KR | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 20160118000 | Kim | Apr 2016 | A1 |
| 20200135147 | Tang | Apr 2020 | A1 |
| 20200152134 | Lee | May 2020 | A1 |
| 20200234634 | Li | Jul 2020 | A1 |
| 20200279534 | Ji | Sep 2020 | A1 |
| 20210134242 | Hei | May 2021 | A1 |
| 20220139336 | Jeon | May 2022 | A1 |
| Number | Date | Country | |
|---|---|---|---|
| 20220068219 A1 | Mar 2022 | US |
