Claims
- 1. A process for the formation of an array of field emitters, comprising the steps of:
- (a) providing an electrically insulative substrate having a base surface supporting an array of post protuberances each having a sidewall extending outwardly from said base surface to a post top surface;
- (b) depositing a conformal gate metal material layer over said electrically insulative substrate;
- (c) depositing a first electrically insulative material conformal layer over said gate metal material layer;
- (d) depositing a sacrificial material conformal layer over said first electrically insulative layer;
- (e) removing that portion of said sacrificial layer which is located over said first electrically insulative layer at said post top surface of said post protuberances by chemical mechanical polishing (CMP);
- (f) removing that portion of said first electrically insulative material layer which is located adjacent said post top surface of said post protuberances and within a region adjacent to and extending toward said base surface region along each said post sidewall;
- (g) removing remaining said sacrificial layer,
- (h) depositing a second electrically insulative layer over exposed said first electrically conductive material layer and removing said first electrically insulative material layer,
- (i) depositing an emitter material conformal layer over said second electrically insulative layer,
- (j) removing that portion of said emitter material layer adjacent said post top surface of said post protuberances to define an emitter rim by chemical-mechanical polishing; and
- (k) removing a select portion of said second electrically insulative material layer intermediate said emitter material layer and said gate material layer adjacent said sidewall of said post protuberances.
- 2. The process of claim 1 in which:
- said gate material is recalcitrant to etching by first and second etchants;
- said first electrically insulative material exhibits etchability by said first etchant and is recalcitrant to etching by said second etchant; and
- said step (f) is carried out by etching with a said first etchant.
- 3. The process of claim 2 in which:
- said sacrificial material exhibits etchability by said second etchant and is calcitrant to etching by said first etchant; and
- said step (g) is carried out by etching with a said second etchant.
- 4. The process of claim 2 in which:
- said second electrically insulative material is etchable by a said first etchant;
- said emitter material is recalcitrant to etching by said first and second etchants; and
- said step (k) is carried out by etching with a said first etchant.
- 5. The process of claim 1 in which:
- said step (d) is carried out by depositing said first electrically insulative material layer at a first thickness; and
- said step (h) is carried out by depositing said second electrically insulative material layer at a second thickness less than said first thickness.
- 6. The process of claim 1 in which said step (a) includes the steps of:
- (a1) depositing a photoresist upon a surface of said electrically insulative substrate;
- (a2) defining a photoresist region for each said post protuberance;
- (a3) stripping said photoresist; and
- (a4) etching said substrate to produce said base surface and said array of post protuberances.
Parent Case Info
This application is a division of application Ser. No. 08/908,144, filed Aug. 6, 1997, now U.S. Pat. No. 5,930,590.
US Referenced Citations (2)
Number |
Name |
Date |
Kind |
5038070 |
Bardai et al. |
Aug 1991 |
|
5874808 |
Busta et al. |
Feb 1999 |
|
Divisions (1)
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Number |
Date |
Country |
Parent |
908144 |
Aug 1997 |
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