Patent Application
20220181210
This invention relates to a method for removing a bar of one or more devices using supporting plates.
Currently, various methods are used for removing devices from a foreign or hetero-substrate, such as wet etching, laser ablation, sacrificial layers, etc. However, such methods may not be appropriate for homo-substrates.
For example, some device manufacturers have used III-nitride substrates, such as GaN substrates, to produce III-nitride-based devices, such as laser diodes (LDs) and light-emitting diodes (LEDs), for lighting, optical storage, electronics devices and sensors etc. However, the cost of GaN substrates has prevented their wider use in fabricating III-nitride-based devices.
Moreover, it is easier to remove a foreign or hetero-substrate from epitaxial layers at a hetero-interface using laser ablation or other techniques. However, III-nitride-based semiconductor layers deposited on GaN substrates lack a hetero-interface, which makes it difficult to remove the GaN substrates from the TI-nitride-based semiconductor layers.
Consequently, there is a need for a technique that removes III-nitride substrates or layers from III-nitride-based semiconductor layers in an easy manner.
In one previous technique, a GaN layer is spalled by a stressor layer of metal under tensile strain. See, e.g., Applied Physics Express 6 (2013) 112301 and U.S. Pat. No. 8,450,184, both of which are incorporated by reference herein. Specifically, this technique uses spalling in the middle of the GaN layer.
However, surface morphology on a spalling plane is rough and this technique cannot be controlled at the spalling position. Moreover, this removal method may damage the semiconductor layers due to excess bending in the layer that is being removed, which may result in cracks in unintended directions.
Thus, it is necessary to reduce any such damages and determine the removing position. When it comes to a mass-production, it is important to determine the removing position, because varying the removing position may reduce the yield of the mass-production.
Another conventional technique is the use of photoelectrochemical (PEC) etching of sacrificial layers to remove device structures from GaN substrates, but this takes a long time and involves several complicated processes.
Thus, there is a need in the art for improved methods of removing III-nitride substrates from III-nitride-based semiconductor layers, especially where GaN thin films are grown on GaN substrates.
To overcome the limitations in the prior art described above, and to overcome other limitations that will become apparent upon reading and understanding this specification, the present invention discloses a method for removing a bar of one or more device using supporting plates.
Specifically, this invention performs the following steps:
Step 1: Fabricate bars comprised of devices on a substrate.
Step 2: Determine a removing position for the bars.
Step 3: Bond supporting plates to the bars.
Step 4: Apply stress to the supporting plates in a vertical direction to the bars to remove the bars at the removing position.
Step 5: Implement device processes after the removal of the bars.
Step 6: Mount the devices with the supporting plates to a stem and stage of a module.
This invention has many advantages in terms of removing bars of devices from the homo- and hetero-substrates. This invention can be adapted to many kinds of opto-electronic devices.
Referring now to the drawings in which like reference numbers represent corresponding parts throughout:
In the following description of the preferred embodiment, reference is made to a specific embodiment in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention.
Overview
The present invention describes a method for removing a bar comprised of one or more devices from a substrate by bonding supporting plates to the bars. Specifically, this invention performs the following steps:
Step 1: Fabricate one or more bars comprised of one or more devices on a substrate.
There are several methods of fabricating the bars. Moreover, this step may include various processes to fabricate the devices on the bars.
Step 2: Determine a removing position for each of the bars.
Step 3: Bond one or more supporting plates to the bars.
Step 4: Apply stress to the supporting plates in a vertical direction to the bar (i.e., orthogonal to the surface of the bar), which removes the bars at the removing positions.
Step 5: Implement additional device processes, if necessary, after removal of the bars, such as disposing an n-electrode on the back side of the bars, making facets for laser diode devices, and so on. These processes are not always necessary because every process may be completed before the removal of the bars.
Step 6: Mount the devices with the supporting plates to a stem and stage of a module. If the supporting plates have a high thermal conductivity, then the supporting plates can be mounted directly to the stem and stage of the module. On the other hand, if thermal conductivity of the supporting plates is low, then a side of the devices can contact the stem and stage of the module in order to maintain a high thermal conductivity.
Removing the bars using the above steps provides a number of advantages when fabricating devices:
Therefore, this invention has many kinds of advantages in terms of removing bars from homo-substrates and hetero-substrates, such as gallium arsenide, indium phosphide, gallium antimonide, etc. Moreover, the removed bars can be easily and quickly processed after the removal because the supporting plates prevent the bars from breaking during processing. Bonding the supporting plates to the bars can assist injunction-down mounting.
The present invention can be used to grow and fabricate an number of different devices, including light-emitting diodes (LEDs), laser diodes (LDs), vertical cavity surface emitting devices (VCSELs), Schottky barrier diodes (SBDs), metal-oxide-semiconductor field-effect-transistors (MOSFETs), or other devices.
Process Steps
The steps of the present invention are described in more detail below:
Step 1: Fabricate a Bar Comprised of One or More Devices on a Substrate.
Several methods may be used in fabricating a bar comprised of one or more devices on a substrate.
Case 1:
The basic configuration of the resulting structure is shown in
A more detailed description of the steps used by the present invention in fabricating the bar 115 of devices is provided below:
Process 1: Depositing the growth restrict mask 102 on the substrate 101 with the remaining surface exposed by striped opening areas 103 in the growth restrict mask 102, as shown in
Process 2: Growing the III-nitride ELO layers 105A on the substrate 101 using the growth restrict mask 102, such that the growth extends in a direction parallel to the striped opening areas 103 of the growth restrict mask 102, and the I-nitride ELO layers 105A do not coalesce, as shown in
Process 3: Removing the substrate 101 with the III-nitride ELO layers 105A from the MOCVD reactor, wherein at least a part of the growth restrict mask 102 is removed by dry or wet etching method with an etchant such as hydrofluoride (HF) or buffered HF (BHF), as shown in
Process 4: Growing the regrowth layers 105B on the III-nitride ELO layers 105A in order to form void regions 107 and flatten the surface of the layers, as shown in
Process 5: Growing the III-nitride device layers 106 on the regrowth layers 105B, as shown in
Process 6: Fabricating the device at the flat surface region by conventional methods, wherein the ridge structure, p-electrode, pad-electrode etc., are disposed on the 11n-nitride device layers 106, which comprise island-like III-nitride semiconductor layers, at pre-determined positions, as shown in
Process 7: Etching at least a part of the I-nitride device layers 106, the regrowth layers 105B, and the III-nitride ELO layers 105A, by a conventional dry etch method, as shown in etching region 114 in
By doing this, bars 115 of devices can be obtained. Also, the breaking point 113, which is a removing position 113, can be obtained utilizing the growth restrict mask 102, as shown in
Case 2:
Process 1: Depositing the growth restrict mask 102 on the substrate 101 with the remaining surface exposed by striped opening areas 103 in the growth restrict mask 102, as shown in
Process 2: Growing the In-nitride ELO layers 105A on the substrate 101 using the growth restrict mask 102, such that the growth extends in a direction parallel to the striped opening areas 103 of the growth restrict mask 102, and the Ill-nitride ELO layers 105A do not coalesce, as shown in
Process 3: Removing the substrate 101 with the III-nitride ELO layers 105A from the MOCVD reactor, wherein at least a part of the growth restrict mask 102 is removed by dry or wet etching with an etchant such as HF or BHF, as shown in
Process 4: Growing the I-nitride device layers 106, as shown in
Process 5: Fabricating the device at the flat surface region by conventional methods, wherein the ridge structure, p-electrode, pad-electrode, etc., are disposed on the III-nitride device layers 106 at pre-determined positions, as shown in
By doing this, bars 115 of devices can be obtained. Also, the breaking point 113, which is a removing position 113, can be obtained utilizing the growth restrict mask 102, as shown in
Case 3:
This case is illustrated in
Process 1: Providing a III-nitride substrate 101; growing one or more InAlGaN-based layers 501-505 on the III-nitride substrate 101, as shown in
Process 2: Fabricating the device structure 507 on the III-nitride device layers 506, which includes p-type layers, active layers and n-type layers and so on, as shown in
Process 3: Etching a part of the InAlGaN-based layers 501-505 by a conventional dry etch method, as shown by etching region 114 in
Process 4: Etching a part of the sacrificial layers 502 to make a depressed region at the edge of the sacrificial layers 502 by wet etching method. Conventional methods can be used, including etchants such as KOH, NaOH, aqua regia, etc.
A photo-electro-chemical (PEC) etching method can be used as well. If a PEC etching method is used, the sacrificial layers 502 should include Indium to facilitate the etching, such as InAlGaN sacrificial layers 502, which have a band-gap larger than a wavelength of an ultraviolet (UV) light source, which can be used when using PEC etching. For example, a 405 nm UV light can be used and the band-gap of the sacrificial layers 502 is larger than 3.06 eV. In this case, the sacrificial layers 502 can absorb the UV light to generate the electrons and holes during PEC etching.
By doing this, bars 115 can be obtained, and the removing position 113 is made to utilize the depressed region at the edge of the sacrificial layers 502.
Step 2: Determine a Removing Position for Each of the Bars
In the present, there are several methods to determine the removing position 113.
One method is to form a region that is narrower than the width Wb of the bar 115, as shown in
Moreover,
Another method, as shown in
Still another method is to form a region where stress is applied most strongly from the supporting plates 116, as shown in
The present invention can utilize these methods of determining the removing position 113, as set forth above. The present invention can also combine these methods.
Step 3: Bonding One or More Supporting Plates to the Bars
Step 3 can be divided into at least two parts. A first part is to fabricate a device structure on the bars 115, and a second part is to bond the supporting plates 116 with the bars 115.
<Fabricating a Device Structure Section>
Fabricating the device on the surface of the bar 115, which is comprised of U-nitride device layers 106, can be done by conventional methods, with a ridge structure, p-electrode, pad-electrode, etc. In the present invention, many kinds of devices can be fabricated on bars 115 by conventional methods using conventional structures.
<Bonding Section>
Various bonding techniques can be used with the present invention, which are applicable for the fabrication of devices by removing bars 115, as described below. This includes diffusion bonding, eutectic bonding (Au—Sn solder, Si—Au), and transient liquid phase bonding (Pd—In bonding). These bonding methods can be adapted for any devices, such as laser diodes, LEDs, electronics devices, sensors and so on.
Bonding supporting plates 116 to the bars 115 aims to transfer the stress applied by the supporting plates 116 to the removing position 113 effectively to facilitate removal of the bar 115. Enhancing the height of the bar 115 is of critical importance to removing the bar 115 at the removing position 113. Moreover, there are no problems if the bonding strength between the bar 115 and the supporting plates 116 is stronger than the strength of removing the bar 115 at the removing position 113. Within this range, any bonding materials can be used, such as solders, adhesives, metals and so on.
Following are various cases for bonding methods that can be adapted to the present invention.
Case 1: Solder
In this case, conventional solder, such as Au—Sn, Sn—Ag—Cu, etc., can be used, as shown in
In the example shown in
The examples shown in
In the LED case, the electrode of LED 901 comprises an Ag layer that directly contacts a p-type layer of the LED to reflect emitted light. The Ni, Ti and Pt layers are used to adhere and prevent interdiffusion. The supporting plate 116 and the LED bar 115 are bonded at 250-300° C., as shown in
The use of Pd—In can provide some advantages to the devices. If removed bars 115 comprise LED devices, those devices require high reflectivity at a bonding portion. For example, low temperature transient liquid-phase Pd—In bonding is implemented at around 200° C. The Pd layer is disposed on the surface of the top of bars 115 and the Pd—In layer is disposed on the supporting plates 116. These structures are then bonded with each other at low temperature. A Pd—In3 intermetallic compound is formed by interdiffusion during heating, which improves the bonding strength due to a high melting temperature over 600° C.
As another candidate, Au and Si eutectic bonding may be used between GaN and Si substrates at 400° C., with a process time of 30 min under 5 MPa.
Ag—Au and Ag—Al diffusion bonding is performed at 150° C. In the LED case, Ni (1 nm: thin layer) may be used to enhance reflectivity in Ni/Ag/Au layers as an LED's p-electrode, which is bonded to Au with an Si sub-mount.
Case 2: Adhesive
In this case, adhesives can be used to bond bars 115 and supporting plates 116. The adhesives can be epoxies or polymetric adhesives. Candidate materials include the following: polyimide, 2-part epoxies, benzocyclobutene (BCB: C8H6) and UV-curable photopolymer such as SU-8. For example, benzocyclobutene (BCB: C8H6) is heated at 200° C. for 60 min when bonding.
Applicators of different adhesives are designed according to the adhesive being used and the size of the area to which the adhesive will be applied.
Case 3; Au—Au Bonding by a Surface-Activation Method
In this case, the bar 115 and the supporting plate 116 can be bonded without solder. Thus, the feature of this bonding is a high thermal conductivity. This is similar to case 1, except for the bonding material 117. In this case, the bonding material 117 is gold (Au) and the supporting plate 116 is preferably Silicon (Si). The bar 115 and the supporting plate 116 are bonded without solder using gold at 300-400° C.
It is preferable to perform an activation of the bonding surfaces before Au—Au bonding is performed. The activation of the bonding surfaces is achieved using a plasma process of Ar and/or O2. The bars 115 are then bonded to the supporting plates 116 at 150-300° C. under pressure.
Case 4: Reflow Bonding
In this case, conventional reflow bonding is used for the sake of self-alignment.
If conductive bonding materials are used, they should cover at least the side facets of the bar 115 with an insulating layers, such as SiO2, Al2O3, Zr2O, etc., to prevent the leakage of current. Preferably, the insulating layer covers the side facet totally.
<Supporting Plates Material>
The following refer the types of materials used for the supporting plates 116.
Case 1: Single Crystal Supporting Plate
In this case, the supporting plate 116 is a single crystal, such as SiC, Si, AlN, GaN, etc. When Si is used as the supporting plate 116, it has the following advantages:
1. high thermal conductivity,
2. low resistivity,
3. easier microfabrication,
4. utilizing an atomically flat surface of Si, Au—Au bonding can be used without solder, and
5. low cost.
Thus, using an Si supporting plate 116 is suitable for the present invention. Other materials such as SIC, AlN and GaN etc. can be used as a supporting plate 116.
Case 2: Metal Supporting Plate
In this case, the supporting plate 116 is metal, such as Cu, CuW, Al, stainless steel, etc. This has the benefit of high thermal conductivity.
Case 3: Ceramic Supporting Plate
When insulation is necessary for a supporting plate 116, good candidates are ceramic materials, such as Al2O3, as well as AlN, SiC, etc. A ceramic supporting plate 116 can also obtain high thermal conductivity.
Generally, many semiconductor lasers adopted this type of sub-mount on a stem, such as a TO-can package, for the reasons of low cost, insulation and a high thermal conductivity.
In the present invention, it does not matter whether the supporting plate 116 is conductive or not. A supporting plate 116 with via holes filled with Ag, etc., can also be used to improve the thermal conductivity and reduce electrical resistivity.
A supporting plate 116 made of ceramics is hard and durable, which makes it is easy to handle without breaking, especially when the supporting plates 116 have a large ratio of longitude length and lateral length. Hardness and robustness are very important elements to supporting plates 116.
<Supporting Plates Shapes>
The following refers the shapes of the supporting plates 116.
Case 1: Separated Supporting Plates
This case uses separated supporting plates 116, wherein the supporting plate 116 is a fin. In a separated fin-type supporting plate 116, the fins are separated individually and placed on bars 115. The fins may be arranged one by one on bars 115, or a plurality of the fins may be arranged on the bars 115 at the same time. Then, pressure is applied to the fins by the plates 116, and the bars 115 and plates 116 are heated for bonding. By doing this, the bonding process completes.
This type of supporting plate 116 has an advantage in that, even when the bars 115 have different heights, these supporting plates 116 can easily bond to the bars 115 due to their having flexibility.
It may happen that the bars 115 have different heights when the bars 115 are grown using the ELO technique. In this case, the separated fin-type supporting plates 116 is preferable.
Case 2: Holding Supporting Plates
This case uses holding-type supporting plates 116, wherein the supporting plate 116 is a fin. In holding-type supporting plates 116, the fins 1101 are arranged on a film 1102, as shown in
Case 2-1: Different Materials
This kind of holding-type supporting plates 116 is comprised of different materials for the fin 1101 and the film 1102. Fins 1101 have been adhered to the film 1102, after which the fins 1101 can be removed.
The film 1102 can be a heat-resistant film, such as a fluoro-resin film, polyimide film, etc. The film 1102 also can be heat-resistant, which has a thermal expansion co-efficient close to the substrate 101 with bars 115, for the sake of a precise bonding position.
If the film 1102 is a flexible film, it is effective even if the heights of the bars 115 are different.
Case 2-2: Same Material
This kind of holding-type supporting plates 116 is comprised of the same materials for the fin 1101 and the film 1102, as shown in
In this case, the advantages are that it is easy to handle the fins 1101 and to precisely arrange the fins 1101 with respect to the corresponding bars 115.
For example, making a film 1102 with fins 1101 from a Silicon substrate can be relatively easily achieved using a dry etching and a wet etching method, such as the structure shown in
However, since the fins 1101 and the film 1102 have less flexibility, the thickness p of the film 1102, as shown in
The fins 1101 and the film 1102 are arranged on the substrate 101 with bars 115, as shown in
The film 1102 and fins 1101 are removed, as shown in
Step 4: Apply a Stress to the Supporting Plates to Remove the Bars at the Removing Positions
Step 4 applies a stress to the supporting plates 116, which may occur in a variety of ways, to remove the bars at the removing positions.
Case 1: Separated Supporting Plates
This case includes separated supporting plates 116, wherein the supporting plates 116 are fins. As shown in
Process 1: Attaching a polymer film 111 to the bar 115 of the device, as shown in
Process 2: Applying pressure to the polymer film 111 and the substrate 101, as shown in
Process 3: Reducing the temperature of the polymer film 111 and the substrate 101 while the pressure is applied.
Process 4: Utilizing the difference in the thermal coefficient between the polymer film 111 and the substrate 101 for removing the bar 115 of the device.
The stress can be created from the difference in the thermal expansion co-efficiency, and can be applied to the supporting plates 116, which can remove the bars 115 from the substrate 101 without contacting the polymer film 111 to the bars 115. By doing this, it can effectively apply the stress at the removing position.
Various methods may be used to reduce the temperature. For example, the substrate 101 and the polymer film 111 can be put into liquid N2 (for example, at 77° K) at the same time while applying pressure. The temperature of the substrate 101 and the polymer film 111 can also be controlled with a piezoelectric transducer. Moreover, the plate 116 that applies the pressure to the polymer film 111 can be cooled to a low temperature before and/or during contact with the polymer film 111. By doing this, the polymer film 111 is cooled and can apply pressure to the bar 115 due to a large thermal expansion coefficient.
When reducing the temperature, the substrate 101 and the polymer film 111 may be wetted by atmospheric moisture. In this case, the temperature reduction can be conducted in a dry air atmosphere or a dry N2 atmosphere, which avoids the substrate 101 and the polymer film 111 getting wet.
Thereafter, the temperature increases, for example, to room temperature, and the pressure is no longer applied to the film 111. At that time, the bar 115 has been already removed from the substrate 101, and the polymer film 111 is then separated from the substrate 101.
Using the separated supporting plates 116 can improve flexibility and obtain a working area that provides a space to be able to move the supporting plates 116. These are critical advantages for the removal.
Another way is shown in
Case 2: Holding-Type Supporting Plate
This case includes a holding-type supporting plate 116, wherein the supporting plate 116 is a fin 1102.
Case 2-1: Different Materials
In the case of different materials, the film 1101 and fins 1102 are arranged on the substrate 101 with bars 115, as shown in
The film 1102 is removed, as shown in
Case 2-2: Same Materials
In the case of the same materials, the fins 1101 and film 1102 are same materials, such as Silicon, etc., as shown in
When a holding plate is a supporting plate, it applies stress to the holding plate, as shown in
This also describes a preferable method that can be used when removing. As shown in
Moreover, other methods can be used in order to remove a holding plate.
<Utilizing the Cleavability of the GaN Crystal>
It is preferable that, when removing the bar 115, it utilizes the cleavability of a GaN crystal, especially along an m-plane and c-plane, which are known as cleavage planes.
Utilizing the cleavage plane for the removal of bars 115 can remove the bars 115 without excess stress, which is much preferable.
Moreover, it has been discovered that bars 115 may be removed by utilizing the cleavability of GaN without using a cleavage plane. As shown in
The present invention can utilize this phenomena. In other words, utilizing the cleavability of the cleavage plane, such as c-plane and m-plane, in other plane that is not a cleavage plane, such as (30-31), (30-3-1), (20-21), (20-2-1), (10-11), (10-1-1), etc., provides a big advantage in removing the bars 115. Thus, it is much preferred to let a part of the substrate 101 surface after the removal appear as a cleavage plane.
This is a very useful and a powerful method that can be utilized for the removal of other planes, such as (11-22) (1-10-2), (1-102), and so on.
Step 5: Implement Additional Device Processes after the Removal of the Bars
Step 5 implements device processes after the removal of the bars 115. However, some or all of these device processes can be implemented before the removal of the bars 115.
For example, the processes after the removal may include an n-electrode deposition to the back side of the bars 115, forming the facet by cleaving, coating of the facet, and so on.
<Disposing the n-Electrode at the Separate Area>
After removing the bar 115 from the substrate 101, as shown in
Then, as shown in
Typically, the n-electrode is comprised of the following materials: Ti, Hf, Cr, Al, Mo, W, Au. For example, the n-electrode may be comprised of Ti—Al—Pt—Au (with a thickness of 30-100-30-500 nm), but is not limited to those materials. The deposition of these materials may be performed by electron beam evaporation, sputter, thermal heat evaporation, etc.
In the case of forming the n-electrode 1403 of back side of the bar 115 after removing the bar 115 from the substrate 101, the n-electrode 1403 is preferably formed on the area including the separate area 1401, which is shown in
The n-electrode 1403 also can be disposed on the top surface, which is the same surface made for a p-electrode.
<Forming the Facet by Cleaving>
Using the supporting plates 116 when removing the bars 115 makes available many methods to form a facet. In other words, the supporting plate 116 can be used when making the facet it, as described in more detail below.
<Dividing Support Regions>
The aim of this step is to prepare to divide the bar 115 of the device before the bar 115 is removed from the substrate 101. As shown in
The dividing support region 1501 is a line scribed by a diamond tipped scriber or laser scriber; or a trench 1502 formed by dry-etching, such as Reactive Ion Etching (RIE) or Inductively Coupled Plasma (ICP), but is not limited to those methods. The dividing support region 1501 is formed on both sides of the bar 115 or on one side of the bar 115. The depth of the dividing support region 1501 is preferably 1 μm or more.
A number of methods can be used to divide the bar 115 into the devices, as described below. The dividing support region 1501 is weaker than any other part. The dividing support region 1501 avoids breaking the bar 115 at unintentional positions, so that it can precisely determine the device length, as shown in
Also as shown in
Moreover, the dividing support regions 1501 can also be formed on the back side of the bar 115 where there is no current injection region 1503 like the top side of the bar 115. Thus, the dividing support regions 1501 can be formed in a variety of ways.
On the other hand, the bar 115 can be divided into one or more devices without the dividing support region 1501, trench 1502 or dividing support regions 1601, 1602, 1603, 1604. Nonetheless, it is much preferred to utilize a dividing support region 1501, trench 1502 or dividing support regions 1601, 1602, 1603, 1604. Furthermore, any combination of different types of dividing support regions 1501, 1601, 1602, 1603, 1604 or trenches 1502 may be used.
<Different Types of Supporting Plates>
There are two types of supporting plates 116: without or with a depressed region 1701, as shown in
Supporting plates 116 can also help remove the bar 115 from a substrate 101 and divide the bar 115 into devices in a bonding situation. In this way, supporting plates 116 have many advantages.
There are a number of methods to divide the bar 115 into devices utilizing supporting plates 115, which are described below.
———Method 1———
Moreover, the bar 115 after the removal does not include substantially the substrate 101. The bar 115, which is made by MOCVD, MBE, etc., is of high crystal quality, while the substrate 101 often has some irregular portions, such as particles, dips, etc. When the substrate 101 and bar 115 are cleaved at the same time in a conventional method, the irregular portion of the substrate 101 may prevent the bar 115 from cleaving well in a straight manner.
Another way of making a facet is shown in
The result of this method is a device unit 1802 comprised of the device with the supporting plate 116.
———Method 2———
In a second method, the supporting plate 116 has depressed regions 1901, as shown in
The result of this method is a device unit 1802 comprised of the device with the supporting plate 116.
———Method 3———
A third method is a variation on the second method without a depressed region, as shown in
———Method 4———
A fourth method uses a dry etch method to cleave and/or divide the bar 115, as shown in
———Method 4′———
A variation on the fourth method is shown in
———Method 5———
A fifth method is shown in
On the other hand, if the dividing supporting region 1501 is formed at the opposite side (top) of the bar 115, the stress applied bends the bar 115 into a concave shape, as shown in
———Method 6———
The sixth method is almost the same as the fifth method. However, the way of applying the stress is different from the fifth method. In the fifth method, the stress is applied the bar 115 mechanically by a collet 1801 and plate 116. On the other hand, in the sixth method, the stress is applied to the bar 115 using the differences in the thermal expansion co-efficient between the bar 115 and supporting plate 116, as shown in
In the case of decreasing temperatures, if the thermal expansion co-efficiency of the bar 115 is larger than of the supporting plate 116, the bar 115 and supporting plate 116 become a concave shape, as shown in
<The Edge of the Open Area>
As shown in
As another measure, using CMP is an informative method after the growth of the In-nitride ELO layers 105A. In the present invention, the ELO III-nitride layer 105A is the thickest layer among the layers in the bar 115. Thus, the difference of the thickness between the edge portion and the center portion of the bar 115 becomes larger. Therefore, after the growth of the ELO III-nitride layers 105A, the substrate 101 with the III-nitride ELO layer 105A is polished by CMP to level the surface. The III-nitride device layers 106 are not as thick as compared to the III-nitride ELO layers 105A. After the growth of the III-nitride device layers 106, the difference of the thickness between the edge portion and the center portion of the bar 115 does not cause problems when fabricating the device.
<Facet Coating Process>
The next step of device processing comprises coating the facets. While a laser diode device is lasing, the light in the device that penetrates through the facets of device to the outside of the device is absorbed by non-radiative recombination centers at the facets, so that the facet temperature increases continuously. Consequently, the temperature increase can lead to catastrophic optical damage (COD) of the facet.
A facet coating can reduce the non-radiative recombination center. To prevent COD, it is necessary to coat the facet using dielectric layers, such as AlN, AlON, Al2O3, SiN, SiON, SiO2, ZrO2, TiO2, Ta2O5 and the like. Generally, the coating film is a multilayer structure comprised of the above materials. The structure and thickness of the layers is determined by a predetermined reflectivity.
In the present invention, the bar 115 is typically divided into multiple device units 1802 to obtain the cleaving facets. The method of coating the facets needs to be performed on a number of device units 1802 at the same time in an easy manner. In facets coating process, the device units 1802 are mounted on a spacer plate 2601 in a low horizontal position before coating, as shown in
By doing this, a number of device units 1802 can be coated simultaneously. In one embodiment, the facet coating is conducted at least two times—once for the front facet and once for the rear facet of each device unit 1802.
The length of the spacer plate 2601 is set to be almost the cavity length of the laser diode device, which makes it easy and quick to perform the coating multiple times. Once the spacer plate 2601 is set in the coating holder 2602, both facets can be coated without setting the spacer plate 2601 in the coating holder 2602 again. In one embodiment, the first coating performed on the front facet which emits the laser light, and the second coating is performed on the rear facet which reflects the laser light. The coating holder 2602 is reversed before the second coating in the facility that deposits the coating film. This reduces the lead time of the process substantially.
As shown in
Step 6: Mount the Devices with a Supporting Plate to a Stem and Stage of a Module
In step 6, the devices with the supporting plate 116 are mounted to a stem and stage of a module, and then subjected to a screening or aging test.
Screening the Device
This step distinguishes between defective and non-defective devices. First, various characteristics of the devices are checked under a given condition; such as output power, voltage, current, resistivity, far field pattern (FFP), slope-efficiency and the like. At this point, the chips have already been mounted on a heat sink plate, so it is easy to check these characteristics.
As shown in
The heat stage 2804 maintains the temperature of the device unit 1802 with the heat sink plate during the screening test, for example, 60 degrees, 80 degrees and so on. Photodetectors 2805 are used to measure light 2806 output power, which identifies non-defective device units 1802 that have a constant output power or detects defective device units 1802.
In particularly, in the case of a III-nitride base semiconductor laser diode device, it is known that when the laser diode is oscillated in a moisture-containing atmosphere, it deteriorates. This deterioration is caused by moisture and siloxane in the air, so the III-nitride-based semiconductor laser diode needs to be sealed in dry air during the aging test. Consequently, when the III-nitride-based laser diode is shipped from a device manufacturer, the laser diode is already sealed in a dry air atmosphere.
Prior Art on the Screening or Aging Tests
Generally speaking, the screening or ageing tests are conducted before shipping, in order to screen out defective products. For example, the screening condition is conducted according to the specifications of the laser device, such as a high temperature and a high power.
Moreover, the aging test is conducted with the device mounted on/into the package, with the package sealed in dry air and/or dry nitrogen before screening. This fact makes the flexibility of packaging and mounting of the laser device restrictive.
In the prior art, if defective production happens, the defective products are discarded in the whole TO-can package, which is a great loss for production. This makes it difficult to reduce the production costs of laser diodes. There is a need to detect defective products at an earlier step.
Benefits and Advantages
The present invention method has the following advantages.
Coating the facets of the device using a heat sink plate, on which can be mounted a plurality of the devices in a low horizontal position and then, after the coating process, dividing the coated bar into the devices with a sub-mount using the trenches, allows the device with the sub-mount to be checked in the screening test in a dry air or nitrogen atmosphere.
When doing the screening test, the devices already has two contacts, namely the p-electrode and the solder on the heat sink plate, or in the case of flip-chip bonding, the n-electrode and the solder on the heat sink plate. Moreover, the present invention can select defective products using the screening test, when the device is only comprised of the chip and the sub-mount. Therefore, in the case of discarding the defective products, the present invention can reduce the loss more than the prior art, which has great value.
In the case of screening of high power laser diode devices, there are two electrode pads with solder 2807, 2808 on the heat stage 2804. One part of solder is connected to the n-electrode with a wire, another part of solder is connected to the p-electrode through a conductive supporting plate. Moreover, it is much preferable that the n-electrode are connected by two or more wires to the solder parts 2808. By doing this, the probes for applying the current to the device, which can avoid contacting the p-electrode and n-electrode directly, which, in the case of applying high current for screening of a high-power laser diode, is critical. The probes do not contact directly to the electrodes, which could break the contacted parts, in particular in the case of applying a high current density.
Mounting the Devices on or into Packages
As shown in
The solder (Au—Sn, Sn—Ag—Cu and the like) or the bonding metal (Au—Au bonding), which are disposed at the bottom of the package 2901, are bonded by the wires to the solder on the package 2901, such as AlN, SIC, CuW, Cu, Al and the like. The pins of the package 2901 are connected to the solder on the plate 116 by the wires. By doing this, current from an outside supply can be applied to the device 2903.
As shown in
Furthermore, this is more preferable than solder bonding between the package 3002 and the devices 3001, which is performed by metal bonding, such as Au—Au, Au—In, etc., bonding. This method requires a flatness at the surface of package 3002 and at the back side of the devices 3001. If the supporting plate 116 is made of the silicon, it is easy to realize a surface that is atomically flat, which is preferable. Without the solder, this configuration accomplishes a high thermal conductivity and low temperature bonding, which are major advantages for the device process.
Moreover, a phosphor 3006 can be positioned outside and/or inside the package 3002. The device 3001 can be mounted in the package 3002 using various configurations because of its compact nature. Moreover, when Silicon is selected as the material of the supporting plate 116, this makes it possible to obtain a variety of shapes, sizes and surface conditions of the supporting plate 116, since silicon has a high processability. Of course, the present invention can use many types of materials, such as metals, ceramics, semiconductors, and so on.
By doing this, this module can be used as a light bulb or a head light of an automobile.
As set forth herein, these processes provide improved methods for obtaining a laser diode device, including VCSELs. In addition, once the device is removed from the substrate 101, the substrate 101 can be recycled a number of times, which accomplishes the goals of eco-friendly production and low-cost modules. These device units may be utilized as lighting devices such as light bulbs, data storage equipment, optical communications equipment such as Li-Fi, etc.
It is difficult to create a single type of package that can be used with a plurality of different types of laser diode devices. However, this method can overcome this issue by using the device units, due to being able to perform an aging test without the packaging. Therefore, it is easy to mount different types of devices in a single type of package.
III-Nitride Substrate
As long as a III-nitride substrate 101 enables growth of a III-nitride-based semiconductor layer through a growth restrict mask 102, any GaN substrate that is sliced on a {0001}, {11-22}, {1-100}, {20-21}, {20-2-1}, {30-31}, {30-3-1}, {10-11}, {10-1-1}plane, etc., or other plane, from a bulk GaN and AlN crystal can be used.
Hetero-Substrate
Moreover, the present invention can also use a hetero-substrate 101 for the device. For example, a GaN template or other III-nitride-based semiconductor layer may be grown on a hetero-substrate 101, such as sapphire, Si, GaAs, SiC, etc., for use in the present invention. The GaN template or other III-nitride-based semiconductor layer is typically grown on the hetero-substrate 101 to a thickness of about 2-6 μm, and then the growth restrict mask 102 is disposed on the GaN template or other I-nitride-based semiconductor layer.
Growth Restrict Mask
The growth restrict mask 102 comprises a dielectric layer, such as SiO2, SiN, SiON, Al2O3, AlN, AlON, MgF, ZrO2, etc., or a refractory metal or precious metal, such as W, Mo, Ta, Nb, Rh, Ir, Ru, Os, Pt, etc. The growth restrict mask 102 may be a laminate structure selected from the above materials. It may also be a multiple-stacking layer structure chosen from the above materials.
In one embodiment, the thickness of the growth restrict mask 102 is about 0.05-3 μm. The width of the mask 102 is preferably larger than 20 μm, and more preferably, the width is larger than 40 μm. This is designed to avoid interfering adjacent supporting plates 116 to each other. The growth restrict mask 102 is deposited by sputter, electron beam evaporation, plasma-enhanced chemical vaper deposition (PECVD), ion beam deposition (IBD), etc., but is not limited to those methods.
As shown in
Typical Dimensions of the Mask
Typically, the growth restrict mask 102 used in the present invention has dimensions indicated as follows. The length of the opening area 103 is, for example, 200 to 35000 μm; the width Wo is, for example, 2 to 180 μm. In one embodiment, the growth restrict mask 102 is formed as shown in
Direction of the Growth Restrict Mask
On an c-plane free standing GaN substrate 101, the striped openings 103 are arranged in a first direction parallel to the 11-20 direction (a-axis) of the substrate 101 and a second direction parallel to the 10-10 direction (m-axis) of the substrate 101, periodically at a first interval and a second interval, respectively, and extend in the second direction.
On a m-plane free standing GaN substrate 101, the striped openings 103 are arranged in a first direction parallel to the 11-20 direction (a-axis) of the substrate 101 and a second direction parallel to the 0001 direction (c-axis) of the substrate 101, periodically at a first interval and a second interval, respectively, and extend in the second direction.
On a semi-polar (20-21) or (20-2-1) GaN substrate 101, the opening areas 103 are arranged in a direction parallel to [-1014] and [10-14], respectively.
Alternatively, a hetero-substrate 101 can be used. When a c-plane GaN template is grown on a c-plane sapphire substrate 101, the opening area 103 is in the same direction as the c-plane GaN template; when an m-plane GaN template is grown on an m-plane sapphire substrate 101, the opening area 103 is same direction as the m-plane GaN template. By doing this, an m-plane cleaving plane can be used for dividing the bar 115 of the device with the c-plane GaN template, and a c-plane cleaving plane can be used for dividing the bar 115 of the device with the m-plane GaN template; which is much preferable.
The width of the striped opening 103 is typically constant in the second direction, but may be changed in the second direction as necessary. It preferably be chosen the direction to be able to obtain the smooth surface easily after the growth of the III-nitride ELO layers 105A.
III-Nitride Semiconductor Layers
The III-nitride ELO layer 105A, the III-nitride regrowth layer 105B, and the III-nitride device layers 106 generally comprise (Al, In, Ga, B)N layers, and may include dopants as well as other impurities, such as Mg, Si, Zn, O, C, H, etc.
The III-nitride device layers 106 generally comprise more than two layers, including at least one layer among an n-type layer, an undoped layer and a p-type layer. The III-nitride device layers 106 specifically comprise a GaN layer, an AlGaN layer, an AlGaInN layer, an InGaN layer, etc. In the semiconductor device, a number of electrodes according to the types of the semiconductor device are disposed at predetermined positions.
Merits of Epitaxial Lateral Overgrowth
The crystallinity of the III-nitride layers 105A grown using epitaxial lateral overgrowth (ELO) upon a III-nitride substrate 101 from a striped opening 103 of the growth restrict mask 102 is very high.
Furthermore, two advantages may be obtained using a III-nitride substrate 101. One advantage is that a high-quality III-nitride ELO layer 105A can be obtained, such as with a very low defects density, as compared to using a sapphire substrate.
Another advantage in using a similar or the same material for both the epilayer and the substrate is that it can reduce strain in the epitaxial layer. Also, thanks to a similar or the same thermal expansion, the method can reduce the amount of bending of the substrate during epitaxial growth. The effect, as above, is that the production yield can be high, in order to improve the uniformity of temperature.
The use of a hetero-substrate, such as sapphire (m-plane, c-plane), LiAlO, SiC, Si, etc., for the growth of the III-nitride-based semiconductor layers is that these substrates are low-cost substrates. This is an important advantage for mass production.
When it comes to the quality of the device, the use of a free standing III-nitride substrate is much preferable, due to the above reasons. On the other hand, the use of a hetero-substrate makes it easy to remove the III-nitride-based semiconductor layers, due to a weaker bonding strength at the cleaving point.
Supporting Plates
In the present invention, there are two types of the supporting plates 116. These types of supporting plates 116 are identified type A and type B. In type A, the supporting plate 116 is predesigned to be suitable for removal of one bar 115. In type B, the supporting plate 116 has a plurality of fins, each of which corresponds to a bar 115 being removed.
Polymer Film
The polymer film 111 is used in order to remove the device units from a III-nitride substrate 101 or from a GaN template used with a hetero-substrate 101, as shown in
When the UV-sensitive dicing tape is exposed the UV light, the stickiness of the tape is drastically reduced. After removing the III-nitride device layers 106 from the substrate 101, the UV-sensitive dicing tape is exposed by the UV light, which makes it is easy to remove.
Devices
The semiconductor device is, for example, a Schottky diode, a light-emitting diode (LED), a laser diode (LD), a vertical cavity surface emitting laser (VCSEL), a photodiode, a transistor, sensor etc., but is not limited to these devices. This invention is particularly useful for micro-LEDs and laser diodes, such as edge-emitting lasers and vertical cavity surface-emitting lasers. This invention is especially useful for a semiconductor laser which has cleaved facets.
A I-nitride base semiconductor laser device and a method for manufacturing thereof, according to a first embodiment are explained.
In the first embodiment, as shown in
In this embodiment, the base substrate 101 is an m-plane substrate made of the ELO III-nitride-based semiconductor, which has a mis-cut orientation toward c-axis with −1.0 degree. As shown in the images of
The growth conditions of the ELO III-nitride layer can be the same MOCVD growth conditions. For example, the growth of the GaN layer is at a temperature of 950-1200° C. and a pressure of 15 kPa. For the growth of a GaN layer, trimethylgallium (TMG) and ammonia (NH3) are used as the raw gas, and the carrier gas is only hydrogen (H2), with silane (SiH4) as a dopant gas. The growth time is 4-8 hours.
The growth gas flow rate is following; TMG is 12 sccm, NH3 is 8 sim, carrier gas is 3 slm, and SiH4 is 1.0 sccm; and the V/III ratio is about 7700. This can obtain a 20 μm thick III-nitride ELO layer 105A.
After the growth of the III-nitride ELO layer 105A, the substrate 101 with the layer 105A is removed from the MOCVD equipment in order to remove the growth restrict mask 102. The growth restrict mask 102 is removed by a wet etching, using an etchant such as HF, BHF and so on. Then, the III-nitride device layers 106 can be grown on the substrate 101, as shown in
For the growth of an AlGaN layer, triethylaluminium (TMA) is used as the raw gas; and for the growth of an InGaN layer, trimethylindium (TMI) is used as the raw gas. Under these conditions, the following layers have been grown on the III-nitride ELO layers 105A.
The ridge stripe structure, which is comprised of a p-GaN cladding layer, SiO2 current limiting layer, and p-electrode, provides optical confinement in a horizontal direction. The width of the ridge stripe structure is of the order of 1.0 to 40 μm, and typically is 10 μm. The nitride semiconductor laser diode has the following layers, laid one on top of another in the order mentioned, on a III-nitride ELO layer (GaN layer) 105A, an InGaN/GaN 3 MQW active layer (10 nm×10 nm: 3 MQW), an AlGaN-EBL (electron blocking layer) layer, a p-GaN guiding layer, an ITO cladding layer and a p-electrode. Note that these nitride semiconductor layers may be formed of any nitride-based III-V group compound semiconductor grown in the above order.
The process for the fabrication of the device is implemented on a wafer-scale. It can use conventional methods, such as a photolithography, deposition by sputter and electron beam (EB), etching by ICP and RIE, etc. Eventually, it can obtain a diode laser structure on the substrate 101, as shown in
As shown in
There are some options in the way of removing the bar 115, as shown in
In the case of
As shown in
In this case, the cleavage facet is made using Method 2 as set forth in Step 5. First, the facet is made, then the supporting plate 116 is separated using the separate portion 1902. As shown in
Only the device units 1802 that pass the screening test are mounted on the package, as shown in
As shown in
In this embodiment, the plane of the I-nitride substrate 101 is semi-polar (20-21). When using a semi-polar substrate 101, the present invention may not be able to obtain a cleavage plane at the facet of the laser diode device. In that case, a dry etching process can be used for making laser facets. As shown in
In this embodiment, the fabrication of a VCSEL is explained as shown in
When dividing the bar 115 into device units, any method as set forth can be used.
However, even if other substrates 101 are used, polishing the back side of the bar 115 by CMP, etc., makes it flat.
LEDs and micro-LEDs are explained in this embodiment. The III-nitride device layers 106 are grown on the ELO III-nitride layer 105A, which is grown on a c-plane GaN substrate 101. The opening area 103, which is not depicted, is a hexagonal shape, and the diameter of the opening area is 3-250 micron meter. A high reflective p-type electrode 901 is disposed on the III-nitride device layers 106.
As shown in
Eventually, the device units from this process are arranged and packaged for use.
In a fifth embodiment, a sapphire substrate is used as the hetero-substrate 101. This structure is almost the same as the first embodiment, except for using the sapphire substrate 101 and a buffer layer on the sapphire substrate 101. A buffer layer is generally used with III-nitride-based semiconductor layers grown on a sapphire substrate 101. In this embodiment, the buffer layer includes both a buffer layer and n-GaN layer or undoped GaN layer. The buffer layer is grown at a low temperature of about 500-700° C. Thereafter, an n-GaN layer or undoped GaN layer is grown at a higher temperature of about 900-1200° C. The total thickness is about 1-3 μm. Then, the growth restrict mask 102 is disposed on the n-GaN layer or undoped GaN layer. The rest of process to complete the device is the same as the first embodiment, especially after the removal of the bar 115 from the sapphire substrate 101.
On the other hand, it is not necessary to use a buffer layer. For example, the growth restrict mask 102 can be disposed on the hetero-substrate directly. After that, the III-nitride ELO layer 105A, regrowth layer 105B and/or III-nitride device layers 106 can be grown. In this case, the interface between the hetero-substrate 101 surface and the bottom surface of the III-nitride ELO layer 105A can be separated easily due to the hetero-interface, which includes a lot of defects.
Employing the present invention, an atomically smooth facet for resonance can be obtained, even using a hetero-substrate 101, because the facet is formed after removing the epi-layer from the hetero-substrate 101. In this case, the type of substrate 101 does not affect the cleaving facet. On the other hand, the use of the hetero substrate 101 has a large impact for mass production.
For example, the substrate 101 used can be a low cost and large size substrate, such as sapphire, GaAs, and Si, as compared to a free-standing GaN substrate. This results in low cost devices. Moreover, sapphire and GaAs substrates are well known as low thermal conductivity materials, so devices made using these substrates have thermal problems. However, using the present invention, since the device is removed from the hetero-substrate 101, it can avoid these thermal problems.
Furthermore, in the case using the ELO growth method for removing the bar 115 of the devices, this method can drastically reduce dislocation density and stacking faults density, which has become a critical issue in the case of using hetero-substrates.
Therefore, this invention can solve many of the problems resulting from the use of hetero-substrates.
Process Steps
Block 4301 represents the step of providing a base substrate 101. In one embodiment, the base substrate 101 is a III-nitride based substrate 101, such as a GaN-based substrate 101, or a hetero-substrate 101, such as a sapphire substrate 101. This step may also include an optional step of depositing a template layer on or above the substrate 101, wherein the template layer may comprise a buffer layer or an intermediate layer, such as a GaN underlayer.
Block 4302 represents the step of depositing a growth restrict mask 102 on or above the substrate 101, i.e., on the substrate 101 itself or on the template layer. The growth restrict mask 102 is patterned to include a plurality of striped opening areas 103.
Block 4303 represents the step of growing one or more III-nitride layers 105A on or above the growth restrict mask 102 using epitaxial lateral overgrowth (ELO), followed by one or more I-nitride regrowth layers 105B. This step includes stopping the growth of the ELO III-nitride layers 105A before adjacent ones of the ELO III-nitride layers 105A coalesce to each other.
Block 4304 represents the step of growing one or more III-nitride device layers 106 on or above the ELO III-nitride layer 105A and III-nitride regrowth layer 105B, thereby fabricating a bar 115 on the substrate 101. Additional device fabrication may take place before and/or after the bar 115 is removed from the substrate 101.
Block 4305 represents the step of bonding the supporting plates 116 to the bar 115. The supporting plate 116 is used to make a cleavage facet for one or more of the device structures after the bars 115 are removed from the substrate 101. The supporting plate 116 may have a width Wsp that is wider than a width Wb of the bars 115. The supporting plate 116 also may have a height Wh that is larger than a width Wb of the bars 115.
Block 4306 represents the steps of applying stress to the supporting plates 116 to remove the bar 115 from the substrate 101 at a removing position 113. This step also includes determining the removing position 113 for the bar 115. A polymer film 111 may contact the supporting plate 116 to apply the stress. The stress is applied to the supporting plates 116 orthogonal, e.g., in a vertical direction, to a surface of the bar 115 to remove the bar 115 from the substrate 101 at the removing position 113.
Block 4307 represents the step of fabricating the bars 115 into devices after the bar 115 is removed from the substrate 101.
Block 4308 represents the step of dividing the bar 115 into one or more devices by cleaving at the dividing support regions 1501 formed along the bar 115.
Block 4309 represents the step of mounting the devices with the supporting plates 116 in a module, wherein the devices are mounted to a stem and stage of the module. The supporting plates 116 may be mounted directly to the stem and stage when the supporting plates 116 have a high thermal conductivity. A side of the device may contact the stem and stage when the supporting plates 116 have a low thermal conductivity.
Block 4310 represents the resulting product of the method, namely, one or more III-nitride based semiconductor devices fabricated according to this method, as well as a substrate 101 that has been removed from the devices and is available for recycling and reuse.
The devices may comprise one or more ELO III-nitride layers 105A grown on or above a growth restrict mask 102 on a substrate 101, wherein the growth of the ELO III-nitride layers 105A is stopped before adjacent ones of the ELO III-nitride layers 105A coalesce to each other. The devices may further comprise one or more III-nitride regrowth layers 105B and one or more additional III-nitride device layers 106 grown on or above the ELO III-nitride layers 105A and the substrate 101.
Modifications and Alternatives
A number of modifications and alternatives can be made without departing from the scope of the present invention.
For example, the present invention may be used with III-nitride substrates of various orientations. Specifically, the substrates may be c-plane polar, basal nonpolar m-plane {1 0-1 0} families; and semipolar plane families that have at least two nonzero h, i, or k Miller indices and a nonzero 1 Miller index, such as the {2 0-2-1} planes. Semipolar substrates of (20-2-1) are especially useful, because of the wide area of flattened ELO growth.
In another example, the present invention is described as being used to fabricate different opto-electronic device structures, such as a light-emitting diode (LED), laser diode (LD), Schottky barrier diode (SBD), or metal-oxide-semiconductor field-effect-transistor (MOSFET). The present invention may also be used to fabricate other opto-electronic devices, such as micro-LEDs, vertical cavity surface emitting lasers (VCSELs), edge-emitting laser diodes (EELDs), and solar cells.
Benefits and Advantages
A number of benefits and advantages are derived from the present invention's method for removing devices from a substrate using supporting plates, including the following:
1. Thin layer devices having a wide width of their contact area with a substrate can be removed from the substrate.
2. Bars can be removed while avoiding breaking the bars after the removal.
3. It is easy to handle the bars after removal.
4. Bonding the supporting plates completes the process of junction-down mounting on the wafer at the same time.
5. The supporting plates can be utilized for making the facets for laser diodes.
These advantages improve yield and shorten processing times.
This concludes the description of the preferred embodiment of the present invention. The foregoing description of one or more embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.
This application claims the benefit under 35 U.S.C. Section 119(e) of the following co-pending and commonly-assigned application: U.S. Provisional Application Ser. No. 62/817,216, filed on Mar. 12, 2019, by Takeshi Kamikawa, Srinivas Gandrothula and Masahiro Araki, entitled “METHOD FOR REMOVING A BAR OF ONE OR MORE DEVICES USING SUPPORTING PLATES,” attorneys' docket number G&C 30794.0724USP1 (UC 2019-416-1); which application is incorporated by reference herein. This application is related to the following co-pending and commonly-assigned applications: U.S. Utility patent application Ser. No. 16/608,071, filed on Oct. 24, 2019, by Takeshi Kamikawa, Srinivas Gandrothula, Hongjian Li and Daniel A. Cohen, entitled “METHOD OF REMOVING A SUBSTRATE,” attorney's docket number 30794.0653USWO (UC 2017-621-1), which application claims the benefit under 35 U.S.C. Section 365(c) of co-pending and commonly-assigned PCT International Patent Application No. PCT/US18/31393, filed on May 7, 2018, by Takeshi Kamikawa, Srinivas Gandrothula, Hongjian Li and Daniel A. Cohen, entitled “METHOD OF REMOVING A SUBSTRATE,” attorney's docket number 30794.0653WOU1 (UC 2017-621-2), which application claims the benefit under 35 U.S.C. Section 119(e) of co-pending and commonly-assigned U.S. Provisional Patent Application No. 62/502,205, filed on May 5, 2017, by Takeshi Kamikawa, Srinivas Gandrothula, Hongjian Li and Daniel A. Cohen, entitled “METHOD OF REMOVING A SUBSTRATE,” attorney's docket number 30794.0653USP1 (UC 2017-621-1); U.S. Utility patent application Ser. No. 16/642,298, filed on Feb. 20, 2020, by Takeshi Kamikawa, Srinivas Gandrothula and Hongjian Li, entitled “METHOD OF REMOVING A SUBSTRATE WITH A CLEAVING TECHNIQUE,” attorney's docket number 30794.0659USWO (UC 2018-086-2), which application claims the benefit under 35 U.S.C. Section 365(c) of co-pending and commonly-assigned PCT International Patent Application No. PCT/US18/51375, filed on Sep. 17, 2018, by Takeshi Kamikawa, Srinivas Gandrothula and Hongjian Li, entitled “METHOD OF REMOVING A SUBSTRATE WITH A CLEAVING TECHNIQUE,” attorney's docket number 30794.0659WOU1 (UC 2018-086-2), which application claims the benefit under 35 U.S.C. Section 119(e) of co-pending and commonly-assigned U.S. Provisional Patent Application No. 62/559,378, filed on Sep. 15, 2017, by Takeshi Kamikawa, Srinivas Gandrothula and Hongjian Li, entitled “METHOD OF REMOVING A SUBSTRATE WITH A CLEAVING TECHNIQUE,” attorney's docket number 30794.0659USP1 (UC 2018-086-1); PCT International Patent Application No. PCT/US19/25187, filed on Apr. 1, 2019, by Takeshi Kamikawa, Srinivas Gandrothula and Hongjian Li, entitled “METHOD OF FABRICATING NONPOLAR AND SEMIPOLAR DEVICES USING EPITAXIAL LATERAL OVERGROWTH,” attorney's docket number 30794.0680WOU1 (UC 2018-427-2), which application claims the benefit under 35 U.S.C. Section 119(e) of co-pending and commonly-assigned U.S. Provisional Patent Application Ser. No. 62/650,487, filed on Mar. 30, 2018, by Takeshi Kamikawa, Srinivas Gandrothula, and Hongjian Li, entitled “METHOD OF FABRICATING NONPOLAR AND SEMIPOLAR DEVICES BY USING LATERAL OVERGROWTH,” attorney docket number G&C 30794.0680USP1 (UC 2018-427-1); PCT International Patent Application No. PCT/US19/32936, filed on May 17, 2019, by Takeshi Kamikawa and Srinivas Gandrothula, entitled “METHOD FOR DIVIDING A BAR OF ONE OR MORE DEVICES,” attorney's docket number 30794.0681WOU1 (UC 2018-605-2), which application claims the benefit under 35 U.S.C. Section 119(e) of co-pending and commonly-assigned U.S. Provisional Application Ser. No. 62/672,913, filed on May 17, 2018, by Takeshi Kamikawa and Srinivas Gandrothula, entitled “METHOD FOR DIVIDING A BAR OF ONE OR MORE DEVICES,” attorneys' docket number G&C 30794.0681USP1 (UC 2018-605-1); PCT International Patent Application No. PCT/US19/34686, filed on May 30, 2019, by Srinivas Gandrothula and Takeshi Kamikawa, entitled “METHOD OF REMOVING SEMICONDUCTING LAYERS FROM A SEMICONDUCTING SUBSTRATE,” attorney's docket number 30794.0682WOU1 (UC 2018-614-2), which application claims the benefit under 35 U.S.C. Section 119(e) of co-pending and commonly-assigned U.S. Provisional Application Ser. No. 62/677,833, filed on May 30, 2018, by Srinivas Gandrothula and Takeshi Kamikawa, entitled “METHOD OF REMOVING SEMICONDUCTING LAYERS FROM A SEMICONDUCTING SUBSTRATE,” attorneys' docket number G&C 30794.0682USP1 (UC 2018-614-1); PCT International Patent Application No. PCT/US19/59086, filed on Oct. 31, 2019, by Takeshi Kamikawa and Srinivas Gandrothula, entitled “METHOD OF OBTAINING A SMOOTH SURFACE WITH EPITAXIAL LATERAL OVERGROWTH,” attorney's docket number 30794.0693WOU1 (UC 2019-166-2), which application claims the benefit under 35 U.S.C. Section 119(e) of co-pending and commonly-assigned U.S. Provisional Application Ser. No. 62/753,225, filed on Oct. 31, 2018, by Takeshi Kamikawa and Srinivas Gandrothula, entitled “METHOD OF OBTAINING A SMOOTH SURFACE WITH EPITAXIAL LATERAL OVERGROWTH,” attorneys' docket number G&C 30794.0693USP1 (UC 2019-166-1); PCT International Patent Application No. PCT/US20/13934, filed on Jan. 16, 2020, by Takeshi Kamikawa, Srinivas Gandrothula and Masahiro Araki, entitled “METHOD FOR REMOVAL OF DEVICES USING A TRENCH,” attorney's docket number 30794.0713WOU1 (UC 2019-398-2), which application claims the benefit under 35 U.S.C. Section 119(e) of co-pending and commonly-assigned U.S. Provisional Application Ser. No. 62/793,253, filed on Jan. 16, 2019, by Takeshi Kamikawa, Srinivas Gandrothula and Masahiro Araki, entitled “METHOD FOR REMOVAL OF DEVICES USING A TRENCH,” attorneys' docket number G&C 30794.0713USP1 (UC 2019-398-1); and PCT International Patent Application No. PCT/US20/20647, filed on Mar. 2, 2020, by Takeshi Kamikawa and Srinivas Gandrothula, entitled “METHOD FOR FLATTENING A SURFACE ON AN EPITAXIAL LATERAL GROWTH LAYER,” attorney's docket number 30794.0720WOU1 (UC 2019-409-2), which application claims the benefit under 35 U.S.C. Section 119(e) of co-pending and commonly-assigned U.S. Provisional Application Ser. No. 62/812,453, filed on Mar. 1, 2019, by Takeshi Kamikawa and Srinivas Gandrothula, entitled “METHOD FOR FLATTENING A SURFACE ON AN EPITAXIAL LATERAL GROWTH LAYER,” attorneys' docket number G&C 30794.0720USP1 (UC 2019-409-1); all of which applications are incorporated by reference herein.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/US20/22430 | 3/12/2020 | WO | 00 |
| Number | Date | Country | |
|---|---|---|---|
| 62817216 | Mar 2019 | US |
