Claims
- 1. A method of fabricating an integrated circuit including a metal-oxide-semiconductor field effect transistor (MOSFET) with reduced leakage current, said method comprising the steps of:
- providing an integrated MOSFET which includes:
- a drain region;
- a drain terminal connected to a first portion of said drain region, wherein said drain terminal includes opposing sides and opposing edges;
- a source region;
- a source terminal connected to a first portion of said source region, wherein said source terminal includes opposing sides and opposing edges;
- a channel region between said drain and source regions;
- a gate terminal disposed opposite said channel, wherein said gate terminal includes opposing sides and opposing edges;
- depositing a nonsilicide layer on a second portion of said drain region; and
- depositing a silicide layer on said drain terminal and on said gate terminal, wherein said silicide layer on said drain terminal is narrower than said drain terminal.
- 2. A method of fabricating an integrated circuit including a metal-oxide-semiconductor field effect transistor (MOSFET) with reduced leakage current, said method comprising the steps of:
- providing an integrated MOSFET which includes:
- a drain region;
- a drain terminal connected to a first portion of said drain region, wherein said drain terminal includes opposing sides and opposing edges;
- a source region;
- a source terminal connected to a first portion of said source region, wherein said source terminal includes opposing sides and opposing edges;
- a channel region between said drain and source regions;
- a gate terminal disposed opposite said channel, wherein said gate terminal includes opposing sides and opposing edges;
- depositing a nonsilicide layer on a second portion of said drain region; and
- depositing a silicide layer on said drain terminal and on said gate terminal, wherein said silicide layer on said gate terminal is narrower than said gate terminal.
- 3. A method of fabricating an integrated circuit including a metal-oxide-semiconductor field effect transistor (MOSFET) with reduced leakage current, said method comprising the steps of:
- providing an integrated MOSFET which includes:
- a drain region;
- a drain terminal connected to a first portion of said drain region, wherein said drain terminal includes opposing sides and opposing edges;
- a source region;
- a source terminal connected to a first portion of said source region, wherein said source terminal includes opposing sides and opposing edges;
- a channel region between said drain and source regions;
- a gate terminal disposed opposite said channel, wherein said gate terminal includes opposing sides and opposing edges;
- depositing a nonsilicide layer on a second portion of said drain region; and
- depositing a silicide layer on said drain terminal, said gate terminal and said source terminal, wherein said silicide layer on said source terminal is narrower than said source terminal.
- 4. A method as recited in claim 1, wherein said step of depositing a silicide layer which is narrower than said drain terminal comprises depositing a silicide layer between said opposing drain terminal edges without extending to one thereof.
- 5. A method as recited in claim 2, wherein said step of depositing a silicide layer which is narrower than said gate terminal comprises depositing a silicide layer between said opposing gate terminal edges without extending to one thereof.
- 6. A method as recited in claim 3, wherein said step of depositing a silicide layer which is narrower than said source terminal comprises depositing a silicide layer between said opposing source terminal edges without extending to one thereof.
Parent Case Info
This is a divisional of application Ser. No. 08/389,720, filed Feb. 16, 1995.
US Referenced Citations (11)
Foreign Referenced Citations (1)
Number |
Date |
Country |
0 420 748 A1 |
Apr 1991 |
EPX |
Divisions (1)
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Number |
Date |
Country |
Parent |
389720 |
Feb 1995 |
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