A claim of priority is made to Korean Patent Application No. 10-2007-0098588, filed on Oct. 1, 2007, the subject matter of which is hereby incorporated by reference.
1. Technical Field
The present invention relates to multiport semiconductor memory devices, and more particularly, to a semiconductor memory device having a shared memory area accessed through multipath, and a multiprocessor system having the same.
2. Description
Universally, remarkable developments are being made in consumer electronic systems. For example, in recent mobile communication systems, such as portable multimedia player (PMP), handheld phone (HHP), or personal digital assistant (PDA), etc., manufacturers are producing products having multiprocessor systems, which incorporate processors in one system to obtain higher speeds and smoother operations.
For example, a portable telephone 1 shown in
In such a multiprocessor system, a semiconductor memory which stores processing data may be changed significantly in view of operation or function. For example, multiple access ports are included, which may require simultaneously inputting/outputting data through the access ports.
In general, a semiconductor memory device having multiple access ports is called a multiport memory. More particularly, a memory device having two access ports is called a dual-port memory. A typical dual-port memory may be an image processing video memory having a random access memory (RAM) port accessible in a random sequence and a serial access memory (SAM) port accessible only in a serial sequence.
A multipath accessible semiconductor memory device is distinguishable from a multiport memory. Unlike the configuration of the video memory, a multipath accessible semiconductor memory device includes a dynamic random access memory (DRAM), which has a shared memory area accessible by respective processors through multiple access ports. A memory cell array of the device does not have a SAM port, but is constructed of a DRAM cell.
An example of a conventional memory adequate for a multiprocessor system is disclosed by MATTER et al. (U.S. Patent Application Publication No. 2003/0093628), published May 15, 2003. MATTER et al. generally discloses technology for accessing a shared memory area by multiple processors, in which a memory array includes first, second and third portions. The first portion of the memory array is accessed only by a first processor, the second portion is accessed only by a second processor, and the third portion is a shared memory area accessed by both the first and second processors.
In contrast, a general multiprocessor system, having a nonvolatile memory that stores processor boot codes, e.g., a flash memory, is adapted each to a processor. A DRAM is also adapted as a volatile memory for every corresponding processor. That is, the DRAM and the flash memory are each adapted to one processor. The configuration of the processor system is therefore complicated and costly.
Therefore, a multiprocessor system adaptable to a mobile communication device was developed, as shown in
As shown in
The flash memory 320 may be a NOR flash memory, having a NOR structure for a cell array configuration, or a NAND flash memory, having a NAND structure for a cell array configuration. The NOR flash memory or the NAND flash memory is a nonvolatile memory for which memory cells, e.g., constructed of MOS transistors having floating gates, are formed in an array. Such nonvolatile memory stores data that is not deleted, even when power is turned OFF, such as boot codes of handheld instruments, preservation data, and the like.
In addition, the multipath accessible DRAM 420 functions as a main memory for a data process of the processors 120 and 220. The multipath accessible DRAM 420 shown in
In the multiport DRAM 420 of
Mailboxes 252 and 253 are storage areas included in an internal register, separate from the memory cell array within the multiport DRAM 420. The mailboxes 252 and 253 are constructed of latch type storage cells different from the memory cells of the DRAM 420, and thus do not require refresh operations.
For example, when a data interface between the first and second processors 120 and 220 is obtained through the multiport DRAM 420, the first and second processors 120 and 220 can write messages to a counterpart processor of a receiving party using the mailboxes 252 and 253. The counterpart processor of the receiving party reads the written message, recognizes the message of the transmitting processor and performs its corresponding operation.
As described above, when processors perform data communications through a DRAM interface using the mailboxes 252 and 253, a host interface may be eliminated or reduced, resulting in a more compact size of the system structure. They also benefit from an operational advantage of the system. Accordingly, it is valid that the first processor 120, which is not directly connected to the flash memory 320, indirectly accesses the flash memory 320 through the multiport DRAM 420.
As described above, in the multiprocessor system of
As mentioned above, the multipath accessible DRAM 420 shown in
Presently, there is no standardized communication protocol for data communications using an interface of the DRAM 420 in the multiprocessor system referred to in
Therefore, a protocol between processors is needed to regulate memory access to efficiently use a DRAM as a multiport semiconductor memory device. In addition, a memory control algorithm of processors should be standardized for manufacturers to reduce the capacity of messages written to mailboxes and to increase the development of systems. In other words, there is not a standardized communication protocol for data communications through a multiport semiconductor memory device in the conventional art, causing increased time and costs for developing systems and system/development components.
Accordingly, embodiments of the invention provide a multiport semiconductor memory device having a protocol-defined area and a multiprocessor system employing the same, as well as a method of accessing the same. The multiport semiconductor memory device includes an area to efficiently regulate a protocol between processors for accessing a memory.
Embodiments of the invention provide a multiport semiconductor memory device and a multiprocessor system employing the same, which are capable of standardizing a memory control algorithm to reduce the message capacity written to mailboxes and to enhance system development by manufacturers. The multiport semiconductor memory device, according to embodiments of the invention, can assign a protocol-defined area usable as a mailbox within a shared memory area, and can provide a standard protocol necessary for controlling memories by processors.
According to an embodiment of the invention, a multiprocessor system includes a first processor for performing a first task, a second processor for performing a second task, and a multiport semiconductor memory device having a protocol-defined area for defining a protocol related to data communication between the first processor and the second processor. The protocol-defined area is located in at least one shared memory area accessible in common by the first processor and the second processor through a first port and a second port, respectively, and is assigned as a predetermined memory capacity to a portion of a memory cell array.
The multiport semiconductor memory device may further include an internal register accessible in response to an address of the shared memory area to provide a data interface function between the first and second processors. The internal register may be located outside the memory cell array. The internal register may include a semaphore area for storing a control authority for the shared memory area, and multiple mailbox areas for storing a message for one of the first and second processors corresponding to a data transmission direction.
The protocol-defined area may be configured to store a portion of the message, which had to be stored in at least one of the plurality of mailbox areas, in DRAM memory cells, in substitution for the at least one mailbox area. The message may be stored in at least one of the plurality of mailbox areas. Also, the protocol-defined area may store a command set, and/or the protocol-defined area may store a command, address or flag data for a data communication protocol between the first and second processors.
The system may further include a NAND type flash memory accessible by the second processor, the NAND type flash memory having a NAND type memory cell structure.
The multiport semiconductor memory device may further include at least one dedicated memory area accessible by one of the first processor or the second processor within the memory cell array.
The first task of the first processor may be a modulation/demodulation function. The second task of the second processor may be a multimedia information processing function.
The multiprocessor system may be one of vehicle-use mobile phone, a portable phone, a portable multimedia player (PMP), a PlayStation Portable® (PSP®), or a personal digital assistant (PDA), for example. The predetermined memory capacity may be a unit of a memory bank.
According to another embodiment of the invention, a multiport semiconductor memory device operationally connected between a first processor performing a first task and a second processor performing a second task includes at least one shared memory area and an internal register. The at least one shared memory area is respectively accessible through different ports by the first processor and the second processor and assigned as a predetermined memory capacity to a portion of a memory cell array. The at least one shared memory area includes a disable area disabled in response to a specific address and a protocol-defined area for defining a specification related to a data communication between the first processor and the second processor. The internal register is accessible in response to the specific address of the shared memory area to provide a data interface between the first processor and the second processor. The internal register is located outside the memory cell array.
The first processor may be a communication processor and the second processor may be an application processor. The internal register may include a semaphore area for storing a control authority for the shared memory area and multiple mailbox areas for storing a message to be applied to one of the first processor and the second processor corresponding to a data transmission direction.
The protocol-defined area may store a portion of a message, which had to be stored in at least one of the plurality of mailbox areas, in DRAM memory cells, in substitution for the at least one mailbox area. The protocol-defined area may store a command, address or flag data for a data communication protocol between the first and second processors.
The device may further include at least one dedicated memory area accessible by one of the first processor or the second processor within the memory cell array.
According to another embodiment of the invention, a method is provided for driving a multiport semiconductor memory device in a multiprocessor system, the multiprocessor system including the multiport semiconductor memory device operationally connected between a first processor performing a first task and a second processor performing a second task, and a nonvolatile semiconductor memory device operationally connected to the second processor. The method includes arranging a protocol-defined area and a disable area within a memory cell array, the protocol-defined area defining a specification related to a data communication between the first and second processors and being accessible in common through different ports within the multiport semiconductor memory device, and the disable area being disabled in response to a specific address; preparing an internal register outside the memory cell array to be accessible in response to the specific address; and regularly writing a message to a pre-defined area by one of the first and second processors occupying the protocol-defined area, and then performing the data communication.
According to another embodiment of the invention, a method is provided for accessing a multiport semiconductor memory device in a multiprocessor system, the multiprocessor system including the multiport semiconductor memory device operationally connected between a first processor performing a first task and a second processor performing a second task, and a nonvolatile semiconductor memory device operationally connected to the second processor. The method includes preparing at least one shared memory area accessible in common by the first and second processors through different ports within the multiport semiconductor memory device and assigned as a predetermined memory capacity to a portion of a memory cell array. The shared memory area includes a disable area disabled in response to a specific address and a protocol-defined area for defining a specification related to a data communication between the first and second processors. The method further includes arranging an internal register outside the memory cell array accessible in response to a specific address of the shared memory area; writing a message to a pre-defined area by one of the first and second processors accessing the protocol-defined area and writing data to a data storage area of the shared memory area, and then indicating a write event to a mailbox of the internal register; and reading the mailbox by the other one of the first and second processors to retrieve the message written to the protocol-defined area, and then reading data written to the data storage area of the shared memory area.
As described above, according to embodiments of the invention, a protocol-defined area usable as a mailbox within a shared memory area is assigned, and a standard protocol necessary for controlling memories by processors is provided, thereby standardizing a memory control algorithm for system manufacturing.
The embodiments of the present invention will be described with reference to the attached drawings, which are given by way of illustration only and thus are not limiting of the present invention, wherein:
The present invention will now be described more fully with reference to
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. For purposes of clarity, a detailed description of other examples, publication methods, procedures, general dynamic random access memories and circuits as known functions and systems are not specifically described.
Representative embodiments of the invention include a multiport semiconductor memory device having a protocol-defined area and a multiprocessor system employing the same, and a method of accessing the same, as described below, referring to the accompanied drawings.
Generally, according to various embodiments, a portion of shared memory area accessible in common by processors is predetermined to be a protocol-defined area. Information for the communication between processors, e.g., commands, addresses, etc., is stored in the predetermined area. Therefore, the protocol-defined area may be utilized as an internal register, and data communications between processors through a multiport semiconductor memory device may be performed according to a predetermined standard or protocol. Accordingly, a standardized oneDRAM™ control algorithm, for example, may be provided to the processors and a mailbox size of the OneDRAM™ may be reduced. Additionally, a standardized protocol among processor manufacturers is provided, making system development easier.
Referring to
In the multiprocessor system of
More particularly, in the multiport DRAM 400 of
In an embodiment, the four memory areas 10, 11, 12 and 13 may be individually configured as DRAM unit banks. Each bank may have a memory storage capacity of 64 Mb, 128 Mb, 256 Mb, 512 Mb or 1024 Mb, for example.
In
For example, when a data interface between the first and second processors 100 and 200 is obtained through the multiport DRAM 400, the first and second processors 100 and 200 can write a message matching a format through the protocol-defined area 110, and can transmit a message write result to the counterpart processor through the mailboxes 52 and 53.
With reference to
According to an embodiment of the invention, area B is the protocol-defined area 110 within the second bank 11, which may be defined as an area of about 2 Kbytes, similar to the disable area 121. Data for commands, addresses, messages, etc., are written in cells comprised of DRAM cells.
Within the protocol-defined area 110, a DRAM/Flash area 11a may be assigned two bits, for example, and contains data indicating a command of DRAM or flash memory. For example, data “11” stored in the DRAM/Flash area 11a indicates a command to access the DRAM, and data “00” stored the DRAM/Flash area 11a indicates a command to access the flash memory. A Read/Write (R/W) area 11b may be assigned one bit, for example, and contains data indicating read/write operations of the shared memory area. For example, data “1” stored in the R/W area 11b indicates a command to read data from the shared memory area, and data “0” stored in the R/W area 11b indicates a command to write data to the shared memory area.
Start address (Add.S) area 11c indicates a start address of the shared memory area, and may be assigned 26 bits, for example. Destination address area (Add.D) 11d indicates a destination address of the shared memory area, and may be assigned 26 bits, for example. Data size (DS) area 11e indicates size of the data to be transmitted, and may be assigned 10 bits, for example. Read/program (R/PGM) area 11f indicates read/program operations of the flash memory, and may be assigned one bit, for example. Flash start address (FAdd.S) area 11g indicates a start address to read/program data from/to the flash memory, and may be assigned 30 bits, for example. Flash destination address (FAdd.D) area 11h indicates a destination address to read/program data from/to the flash memory, and may be assigned 30 bits, for example. Flash data size (FDS) area 11i indicates a size of data to be read/programmed from/to flash memory, and may be assigned 10 bits, for example. Reserve (RSV) area 11j is a spare area, which may be additionally defined, if necessary.
When a standardized protocol is provided, as described above with reference to
Further, the storage capacity of mailboxes assigned within an internal register may be substantially reduced by establishing arrangement of the protocol-defined area 110. Most contents of messages to be transferred are stored in the protocol-defined area 110. Therefore, each of the mailboxes is used to store information on whether a message exists. The mailboxes assigned 32 bits thus can be reduced up to 2 bits.
In addition, boundaries may be regulated for access operations of a OneDRAM™, for example. Therefore, it is available to define test items to ensure test coverage.
Consequently, a protocol-defined area, which may be used as a mailbox in the shared memory area, has a standardized protocol necessary for controlling memories by processors. Accordingly, processor manufacturers benefit from a standardized memory control algorithm, and system development is simplified.
In
In
Control authority for the shared memory area (second bank 11), is written in the semaphore area 51, which is a familiar term to processing system developers. In the first and second mailbox areas 52 and 53, a message may be written according to a predetermined transmission direction. The message may include, for example, authority requests, commands, transmission data indicating an address of a shared memory in which an address, data size or data is stored, and/or commands, etc., given to counterpart processors. The first and second mailbox areas 52 and 53 are the same as the mailboxes 52 and 53 of
As shown, the disable area 121 and the protocol-defined area 110, defining a specification related to a data communication between processors to realize the invention, are assigned to the shared memory area (second bank 11).
A control unit 30 controls a path to operationally connect the second bank 11 to the first processor 100 or the second processor 200. A signal line R1, connected between the first port 60 and the control unit 30, transfers a first external signal applied through bus B1 from the first processor 100. A signal line R2, connected between the second port 61 and the control unit 30, transfers a second external signal applied through bus B2 from the second processor 200. The first and second external signals may include a row address strobe signal RASB, a write enable signal WEB and a bank selection address BA individually applied through the first and second ports 60 and 61. Signal lines C1 and C2, respectively connected between the control unit 30 and multiplexers 40 and 41, transfer path decision signals MA and MB to operationally connect the second bank 11 to the first or second port 60 or 61.
Referring to
When a row address strobe signal RASB_A, RASB_B is first input through one of the ports, the gating part 30a assigns the shared memory area (second bank 11) to that port. For example, when the row address strobe signals RASB_A, RASB_B are applied simultaneously, the processor having priority through a system specification may access the shared memory area (second bank 11).
The control unit 30 also include inverters 30b, 30c, 30j and 30k, a latch LA constructed of NAND gates 30d and 30e, delay devices 30f and 30g, and NAND gates 30h and 30i, with a wiring structure shown in
Referring to
The protocol-defined area 110 includes regulated portions, which are predetermined to effectively provide a communication standard, as described above with reference to
Referring to
In
Multipath data access during normal operation of the first processor 100 will now be described with reference to
In
A word line WL, as shown in
A column selection gate 6, including column selection transistors T1 and T2, is coupled to a column selection line CSL transferring a decoded column signal of column decoder 74. The column decoder 74 applies a decoded column signal to the column selection line CSL and the register 50 in response to a selection column address SCADD of column address multiplexer 70.
In
When the path decision signal MA output from control unit 30 is in an active state, read data transferred to the global input/output line pair GIO, GIOB is transferred to the input/output sense amplifier and driver 22 through the second multiplexer 40. The input/output sense amplifier and driver 22 amplifies data having a level weakened in the course of the transfer procedure through several data paths. The read data output from the input/output sense amplifier and driver 22 is transferred to the first port 60 through multiplexer and driver 26. Meanwhile, the path decision signal MB is in an inactive state, thus the second multiplexer 41 is disabled. Accordingly, an access operation of the second processor 200 to the shared memory area (second bank 11) is intercepted. However, the second processor 200 can still access the dedicated memory areas B (third and fourth banks 12 and 13) through the second port 61.
When the path decision signal MA output from the control unit 30 is in an active state, write data applied through first port 60 is transferred to the global input/output line pair GIO, GIOB, sequentially passing through the multiplexer and driver 26, the input/output sense amplifier and driver 22 and the second multiplexer 40. When the first multiplexer (F-MUX) 7 is activated, the write data is transferred to the local input/output line pair LIO, LIOB and then stored in a selected memory cell 4.
Output buffer and driver 60-1 and input buffer 60-2, as shown in
The first and second processors 100 and 200 commonly use circuit devices and lines that are adapted between global input/output line pair GIO, GIOB and memory cell 4 in an access operation. The first and second processors 100 and 200 independently use input/output related circuit devices and lines adapted between respective ports 60, 61 and the second multiplexers 40, 41. Further, the first and second processors 100 and 200 share, through the first and second ports 60 and 61, respectively, the global input/output line pair GIO, GIOB of the second bank 11, the local input/output line pair LIO, LIOB operationally connected to the global input/output line pair GIO, GIOB, the bit line pair BL, BLB operationally connected to the local input/output line pair LIO, LIOB through the column selection signal CSL, the bit line sense amplifier 5 on the bit line pair BL, BLB to sense and amplify data of bit line, and the memory cell 4, the access transistor AT of which is connected to the bit line BL.
As described above, in the semiconductor memory device of the exemplary embodiment shown in
Operation of a multiport semiconductor memory device, including a protocol-defined area defining a specification related to data communications between processors, is described with reference to
Referring again to
Accordingly, the second processor 200 applies a read command S7 to the second port 61 (
Then, when a read command S10 is given after an active command S9 of the second processor 200, the data S2 previously written to memory cells of the protocol-defined area 110 is read as read data S11 after time point t3. Thus, by analyzing the read data S11, the second processor 200 recognizes how much data has been written by the first processor 100, and at which addresses of the shared memory area. The second processor 200 then applies read command S12 to the second port 61 (
Accordingly, transfer data of the first processor 100, written to the data storage area 116 of
As described above, a protocol-defined area usable as a mailbox is assigned within shared memory. Also, a standard protocol is provided for processors to control memories, thereby standardizing a memory control algorithm for processor manufacturers, which simplifies development of systems.
It is understood that the multiprocessor system according to embodiments of the present invention is not limited to two processors, the number of which may be increased to three or more. Further, in the multiprocessor system, each processor may be a microprocessor, CPU, digital signal processor, micro controller, reduced-command set computer, complex command set computer, or the like. The scope of the invention is therefore not limited to the number of processors in the system. Further, the scope of the invention is not limited to any special combination of processors.
It will be apparent to those skilled in the art that modifications and variations can be made in the present invention without deviating from the spirit or scope of the invention. Thus, it is intended that the present invention cover any such modifications and variations. For example, the configuration for a shared memory bank of a multiport semiconductor memory or the configuration of circuit and access method may be diversely changed.
In addition, an internal determination format of a protocol-defined area may be changed or the number of determination format areas may increase or decrease. Further, although the nonvolatile memory is depicted as flash memory and the volatile memory is depicted as a multiport DRAM in the examples provided above, other volatile and nonvolatile memories, such as phase-change random access memory (PRAM) or a static random access memory (SRAM), may be incorporated. Accordingly, these and other modifications are within the spirit and scope of the invention.
In the drawings and specification, there have been disclosed exemplary embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense and not for purposes of limitation. While the present invention has been described with reference to exemplary embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present invention. Therefore, it should be understood that the above embodiments are not limiting, but illustrative.
Number | Date | Country | Kind |
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10-20070098588 | Oct 2007 | KR | national |