This application is based on and claims the benefit of priority from the prior Japanese Patent Application No. 2006-294184, filed on Oct. 30, 2006, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This invention relates to a non-volatile semiconductor memory system having a non-volatile semiconductor memory device and a controller for controlling read/write thereof.
2. Description of the Related Art
A NAND-type flash memory is known as one of electrically rewritable and non-volatile semiconductor memories (EEPROMs). The NAND-type flash memory has features as follows: unit cell area thereof is smaller than that of NOR-type one; and it is easy to increase the capacity. Further, although the read/write speed for each cell is slower than that of NOR-type one, increasing a cell range (i.e., physical page length), in which data are simultaneously read/written between the cell array and a page buffer, it becomes possible to perform read/write at a substantially high rate.
To make the above-described features effective, NAND-type flash memories are used as various recoding media such as a file memory, a memory card and the like.
In the NAND-type flash memory, a set of NAND cell units arranged in the word line direction is defined as a block, which serves as a data erase unit. To rewrite data in a block, it is in need of writing data after erasing the block in a lump.
However, there will be often happened such a situation that the head address of a to-be-rewritten data file area is located midway in a block while another data file, which is not to be rewritten, is written in the same block. To collectively erase the above-described block, it is necessary to do a copy-write operation for caching the “another data file”, which is not to be rewritten, to a spare block (for example, refer to JP-P2006-040264A).
According to an aspect of the present invention, there is provided a non-volatile semiconductor memory system including:
a non-volatile semiconductor memory device having a data storage area defined by a plurality of blocks, each block serving as an erase unit; and
a memory controller configured to control read/write of the non-volatile semiconductor memory device, wherein
the non-volatile semiconductor memory device is write-controlled in such a manner that a data unit is written into a data area from the head address of a block with a capacity of integer times the block capacity.
According to another aspect of the present invention, there is provided a data write method of a non-volatile semiconductor memory system, the data storage area of which is formed of multiple blocks each serving as an erase unit, including:
writing real data of a data unit in a certain area of the non-volatile semiconductor memory in such a manner that the certain area is so embedded from the head address of a block with the real data as to leave an unwritten area in another block; and
writing dummy data in the unwritten area, thereby resulting in that the data unit containing the real data and the dummy data occupies a data area with a capacity of integer times the block capacity.
Illustrative embodiments of this invention will be explained with reference to the accompanying drawings below.
The flash memory chip 21 may be often formed of multiple chips, for example, two chips Chip 1 and Chip 2, as shown in
In other words, a host device accesses the flash memory with not a physical block address (PBA) base but a logic block address (LBA) base. Therefore, this flash memory system 20 will be referred to as an LBA-NAND memory hereinafter.
The memory controller 22 is a one-chip controller including: a NAND flash interface 23 serving for data transferring between the memory chip 21 and itself; a host interface 25 serving for data transferring between itself and a host device; a buffer RAM for temporally storing read/write data and so on; an MPU 24 for controlling the data transferring; and a hardware sequencer 27 used, for example, for sequence-controlling read/write of firmware (FW) in the NAND-type flash memory 21.
Firmware (FW) required of the memory controller 22 is automatically read out from the flash memory chip 21 to be transferred to the buffer RAM (data register) in an initial setup mode, which is automatically executed just after power on. This data read control will be performed with the hardware sequencer 27 in the memory controller 22.
Note here it is not essential for the LBA-NAND memory system in accordance with this embodiment that memory chip 21 and memory controller 22 are formed as independent chips of each other.
Memory cell array 1 is, as shown in
One end of the NAND cell unit NU is coupled to a bit line BLe or BLo via a select gate transistor 51; and the other end to a cell source line CELSRC via another select gate transistor S2. Control gates of the memory cells M0-M31 are coupled to word lines WL0-WL31, respectively; and gates of the select gate transistors S1 and S2 to select gate lines SGD and SGS, respectively.
A set of NAND cell units arranged in the direction of the word lines constitutes a block, which serves as the minimum unit of data erase. As shown in
Disposed at one end of the bit lines BLe and BLo is a sense amplifier, which serves for reading and writing cell data while disposed at one end of the word lines is a row decoder 2, which serves for selectively driving word lines and select gate lines. In
Command, address and data are input via I/O control circuit 13; and chip enable signal /CE, write enable signal /WE, read enable signal /RE and other external control signals are input to a logic control circuit 14 and serve as timing control signals. The input command will be decoded at command register 8.
Control circuit 6 is configured to control data transferring and perform sequence control of write/erase/read. Status register 11 is prepared to output a Ready/Busy state of the LBA-NAND memory 20 to a Ready/Busy terminal. In addition to the status register 11, another status register 12 is prepared to teach some states of memory 20 (Pass/Fail, Ready/Busy and the like) to the host device via a certain I/O port.
The input address is transferred to the row decoder 2 (including pre-row decoder 2a and main row decoder 2b) and column decoder 4 via address register 5. The input write data is loaded in the sense amplifier circuit 3 (including sense amplifier 3a and data register 3b) via I/O control circuit 13 while read data is output outside via the control circuit 6 and I/O control circuit 13.
To generate various high voltages necessary for operation modes, a high voltage generating circuit 10 is prepared. This high voltage generating circuit 10 generates high voltages in response to instructions supplied from the controller 6.
In the above-described LBA-NAND flash memory system in accordance with this embodiment, a data unit to be written is always controlled to occupy a data area with an integer times block capacity (i.e., block size D), the head address of which is one of a block. This write area control will be explained below.
As a result, as sequentially written file data B, real data B1 thereof may be written from the head address of the block BLKi to a halfway location in block BLKj. The remaining fractional pages of the block BLKj will be embedded with dummy data B2 like the case of file data A.
It is decided in accordance with types of the file data how the above-described dummy data should be used. For example, the following two cases, CASE1 and CASE2, will be explained in detail.
CASE1: this is such a case that the file data is one selected from, for example, music data, movie data and the like, and the host device (or system) is able to optionally decide the data size. In case the final address of recording data has not reached the final address of a block, the host system transfers and records dummy data to completely fill the block. For example, history information data of the recording data may be used as the dummy data. Alternatively, it is permissible to leave the remaining area empty as it is, and record only information such as an “END OF FILE” mark at the final address of the block, so that the remaining area is dealt with an effective area (i.e., the unwritten area is set as an write-forbidden area). Further, in case of movie data recoding, data of a few or several seconds may be written as the dummy data that is written after operating the stop button.
CASE2: this is such a case that it is difficult to change the data size, for example, such a case that the file data is to be written in a file on a personal computer (PC). In this case, the host system calculates the remaining address space from the final address of the file data to that of a block, and writes dummy data in the remaining address apace. In this case, a kind of text data linked to the written data, temporary random data and the like may be used as the dummy data. This dummy data will be registered as “effective data” on the PC. Alternatively, it is effective to register the remaining address space as “effective data area” on the PC without writing any actual file data in the remaining address space. In detail, it is permissible to regard the remaining address space as an area which is used by the host system or a bad cluster.
As described above, every data unit, which includes read data and dummy data if necessary attached to the real data, is always written from the head address of a block to occupy a data area with integer times block capacity. According to this write control scheme, there is not happened such a situation that different files are written in a block. Therefore, to erase unnecessary file data, collective block erase may be performed without executing a copy-write operation for caching other file data, which are not to be erased. As a result, the high-speed performance of the host device will not be spoiled.
Note here that the real data in one data unit is to-be-written data in accordance with a write sequence with sector count value and sector address (initial value) input as described later.
It is effective that the areas of dummy data A2 and B2 are not embedded with these dummy data, but set to be write-forbidden areas as being left empty. The write-forbidden areas may be set in such a way as to, for example, prepare a protect register for storing write-forbidden addresses (at least the head addresses thereof) corresponding to the write-forbidden areas. Further, the dummy data writing or write-forbidden area setting may be performed in response to instructions of the host device using the memory system. Alternatively, it is also effective that memory controller 22 in the flash memory system 20 automatically executes the dummy data writing or the write-forbidden area setting after the real data writing.
In the LBA-NAND memory in accordance with this embodiment, one sector (for example, 512Byte) serves as a data transfer unit for data reading/writing, and SSFDC (Solid State Floppy Disk Card) format is used as data transfer format. By use of a sector count scheme, a command being issued once, it is possible to continue data read/write for multiple sectors.
For example, to write N sector data, the host sequentially inputs a write command, sector count numbers (for example, first sector count (1Byte) and second sector count (1Byte)), logical sector address (initial value), write data of N sectors, and a write-start command. In accordance with this command sequence, the memory controller executes continuously N-sector data write.
In this write scheme, the host does not control the physical address of the flash memory. Therefore, to write a file data in the flash memory from the head address of a block, it is required of the host to get the head address of a block in a spare area in the flash memory.
Explaining in detail, write command CMD1 is input, following it specific command CMD2 (1Byte) and dummy data(1Byte) are input in place of the first and second sector counts to be normally input, and then write sector address (3Byte) and execute command CMD3(1Byte) are successively input.
In response to the specific command CMD2 and execute command CMD3, controller 22 in the LBA-NAND memory searches a physical write-start address corresponding to the input logical sector address (initial value). To confirm it, the host gets the write-start address corresponding to the input sector address as a “returned address value”.
In
Following the above-described previous process for getting the write-start address, the host issues, as shown in
At this time, the specific write sequence of the host will be expressed as, for example, shown in
Note here,
After writing, it is detected whether the noticed end address is identical with a block end address or not (step S4). If YES, this write sequence ends. If NO, dummy data is written into the remaining area (fractional pages) in the final block of the data write area (step S5).
Explaining in detail, when receiving the judgment “NO” at step S4, the host calculates data amount corresponding to the fractional pages; inputs sector count, sector address (the end address +1) and dummy data defined by the calculated data amount; and executes dummy data write as well as the normal sector write. That is, the memory controller 22 executes dummy data write in the fractional pages in the block under the condition that the physical address corresponding to the noticed end address +1 serves as the write-start address (step S5).
As a result, in the LBA-NAND memory, the successive empty area is always defined as starting from the head address of a block.
Note here that the fractional page area may be set to be a write-forbidden area as being empty as it is without executing the specific dummy data write as described above. Additionally, it is possible to use such a scheme that the memory controller in the flash memory system 20 automatically executes the dummy data writing or the write-forbidden area setting without instructions of the host device.
In the above-described embodiment, as shown in
To achieve the scheme shown in
This invention is not limited to the above-described embodiment. It will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit, scope, and teaching of the invention.
Number | Date | Country | Kind |
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2006-294184 | Oct 2006 | JP | national |