This application claims priority under 35 U.S.C. §119 to Korean Patent Application 10-2006-0112737 filed on Nov. 15, 2006, in the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference.
Related art semiconductor devices with integrated circuits such as CPUs, memories, gate arrays, etc., may be combined within various electronic products such as personal computers, servers, workstations, etc. As operating speed of electronic products increases, swing width of signal interfaced between the semiconductor devices may decrease. This may reduce signal transfer delay. However, as signal swing decreases, influence of external noise may increase, and/or signal reflection due to impedance mismatch may be more prominent at interface terminals. Impedance mismatch may be generated by external noise, changes in power source voltage, changes in operating temperature, changes in manufacturing processes, etc. When impedance mismatch occurs, transmitting data at relatively high speeds may be more difficult and/or input/output signals may be distorted. When such a distorted signal is transmitted, setup/hold time failures and/or errors in determining input levels may become more frequent at the receiver. For example, in electronic products employing related art DRAM's, bus frequency may increase more rapidly. An ODT circuit has a termination structure in which a bus is terminated on an input/output port of a memory installed on a memory module. The ODT circuit is an impedance matching circuit and may be implemented within an integrated circuit.
In a conventional semiconductor memory device such as DDR (Double Data Rate) type SDRAM, a related art method of connecting a resistive element having a fixed resistance value to a pad may be used to match impedance. However, a related art ODT circuit having fixed resistance value has only a set resistance value making various termination operations more difficult.
In the related art, the ODT within the memory chip may be limited to only single-ended signals, and termination resistance for termination control of differential signals may exist on a system PCB or module PCB.
Example embodiments relate to semiconductor integrated circuits capable of performing impedance matching of signals, for example, an on-die termination circuit for semiconductor memory devices.
Example embodiments provide on-die termination (ODT) circuits for semiconductor memory devices. At least one example embodiment may perform termination control on a pair of differential mode signals within a memory chip.
According to example embodiments, an ODT on a semiconductor memory device circuit may include a switching circuit having switching devices and termination resistance devices, connected in parallel between differential signal lines having one pair of applied differential mode signals. In response to an applied control signal, the switching devices may connect the termination resistance devices with the differential signal lines during operation.
According to example embodiments, an ODT circuit on a semiconductor memory device may include a switching circuit having a series combination of a first and a second group termination resistance devices connected in parallel between differential signal lines having one pair of applied differential mode signals. In response to an applied control signal, a switching device may connect the first and second group termination resistance devices with the differential signal lines during operation.
According to another example embodiment, an ODT circuit on a semiconductor memory device may include a mode register set (MRS) circuit. The MRS circuit may include a mode register and/or a plurality of inverters and may generate at least one switching control signal in response to a received external control signal.
According to some example embodiments, the semiconductor memory device may include a clock buffer and/or data output buffer along with the ODT circuit.
According to example embodiments, programmable impedance matching on differential mode signals may be obtained within a memory.
Example embodiments will become more apparent by describing in detail the attached drawings. The accompanying drawings are intended to depict example embodiments and should not be interpreted to limit the intended scope of the claims.
Detailed example embodiments are disclosed herein. However, specific structural and functional details disclosed herein are merely representative for purposes of describing example embodiments. Example embodiments may, however, be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
Accordingly, while example embodiments are capable of various modifications and alternative forms, embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that there is no intent to limit example embodiments to the particular forms disclosed, but to the contrary, example embodiments are to cover all modifications, equivalents, and alternatives falling within the scope of example embodiments. Like numbers refer to like elements throughout the description of the figures.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of example embodiments. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it may be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between”, “adjacent” versus “directly adjacent”, etc.).
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises”, “comprising,”, “includes” and/or “including”, when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It should also be noted that in some alternative implementations, the functions/acts noted may occur out of the order noted in the figures. For example, two figures shown in succession may in fact be executed substantially concurrently or may sometimes be executed in the reverse order, depending upon the functionality/acts involved.
Referring to
The semiconductor memory device 100 may include ODT circuit 50 and receiver 60.
In example operation, signals S and S may be output from the controller 10 to the ODT circuit 50. The signals S and S may be a pair of differential mode signals, which may be opposite in phase as shown in signal waveforms provided on the lower part of
The ODT circuit 50 may perform on-die termination control through an internal termination resistance according to a state of the control signal CON. For example, impedance matching for the pair of differential mode signals S and S may be performed, and the impedance matched pair of differential mode signals S and S may be applied to the receiver 60. The pair of differential mode signals S and S may be external clock signals applied to the semiconductor memory device and the receiver 60 may be a clock buffer.
Referring to
In
Referring to
In response to the applied switching control signals M1, M2, M3 and M4, the transmission gate may connect (e.g. in series) a termination resistance device from the first group and a termination resistance device from the second group to the differential signal lines 68S and 68/S.
A mode register set (MRS). circuit 65 may be configured to receive the external control signal CON and generate a plurality of switching control signals M1, M2, M3 and/or M4. The MRS circuit 65 may be connected to the switching circuit 62 and may include a mode register 63 and/or plurality of inverters I1-I4.
An example on-die termination control will be described referring to
The above described ODT circuit is configured so that termination control of a differential signal may be performed according to an external signal to improve amplification magnitude and/or performance of differential signals in a relatively high speed system.
Another example on-die termination control will be described referring to
As described above, an ODT circuit may be configured so that a termination control of the differential signal may be performed by an external controller.
Signals S and /S may be input to the ODT circuit 50. The signals S and /S may be differential mode signals output by the transmitter 40. Similar to
The ODT circuit of
According to example embodiments, an ODT circuit may be implemented within memory devices, and resistance values of the termination resistance devices coupled between differential signals may be controlled by an external signal. These values may also be connected using appropriate software programs, which may lower the overall system costs relative to the conventional art.
In ODT circuits according to example embodiments, programmable impedance matching on differential mode signals may be implemented inside a memory device. Accordingly, software programming may be obtained, which may lower overall system costs, as compared to the related art.
Example embodiments having thus been described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the intended spirit and scope of example embodiments, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.
Number | Date | Country | Kind |
---|---|---|---|
10-2006-0112737 | Nov 2006 | KR | national |