Patent Application
20200211469
This application claims priority to and the benefit of Korean Patent Application No. 10-2018-0171982, filed on Dec. 28, 2018 in the Korean Intellectual Property Office (KIPO), the content of which is incorporated herein in its entirety by reference.
Exemplary embodiments of the present inventive concept relate to display devices, and more particularly to organic light emitting diode (OLED) display devices supporting partial driving modes.
An organic light emitting diode (OLED) display device is suitable for a flexible display device because the OLED display device does not require a backlight unit and has high flexibility. Recently, various flexible display devices, such as a foldable display device, a rollable display device, a stretchable display device, etc. have been developed. Among these various flexible display devices, the foldable display device provides portable convenience when it is folded and displays a large screen when it is unfolded, and therefore attracting much attention as next-generation technology in the display field.
In some foldable display devices, for example, in an out-folding display device, where a display panel is folded such that a portion of the display panel is located in the rear, a partial driving mode, where a partial panel region located in the front of the out-folding display device is driven and another (or remaining) partial panel region located in the rear of the out-folding display device is not driven may be used. However, even if data signals are not applied to the partial panel region that is not driven in the partial driving mode, the non-driven partial panel region may undesirably emit light due to remaining currents or leakage currents.
Some example embodiments provide an organic light emitting diode (OLED) display device capable of preventing or reducing a partial panel region that is not driven in a partial driving mode from undesirably emitting light.
According to example embodiments, there is provided an OLED display device including a display panel including a first partial panel region and a second partial panel region, a scan driver configured to sequentially apply scan signals to the first and second partial panel regions in a normal driving mode where both of the first and second partial panel regions are driven, and to sequentially apply the scan signals to a driven one of the first and second partial panel regions in a partial driving mode, where the driven one of the first and second partial panel regions is driven and a non-driven one of the first and second partial panel regions is not driven, and a data driver configured to apply data signals to the first and second partial panel regions in the normal driving mode, and to apply the data signals to the driven one of the first and second partial panel regions in the partial driving mode. In the partial driving mode, the scan driver is configured to sequentially apply diode initialization signals to the driven one of the first and second partial panel regions, and to concurrently apply the diode initialization signals to the non-driven one of the first and second partial panel regions.
In example embodiments, in the partial driving mode, OLEDs of pixels included in the non-driven one of the first and second partial panel regions may be initialized in response to the concurrently applied diode initialization signals.
In example embodiments, in the partial driving mode, pixels included in the non-driven one of the first and second partial panel regions may form leakage current paths from a power supply voltage line to an initialization voltage line in response to the concurrently applied diode initialization signals.
In example embodiments, each of the first and second partial panel regions may include a plurality of pixels. Each of the plurality of pixels may include a diode initialization transistor having a gate for receiving a corresponding one of the diode initialization signals, a first terminal connected to an initialization voltage line, and a second terminal connected to an anode of an OLED. In the partial driving mode, the diode initialization transistors of the plurality of pixels included in the non-driven one of the first and second partial panel regions may be turned on in response to the concurrently applied diode initialization signals.
In example embodiments, the turned-on diode initialization transistors of the plurality of pixels included in the non-driven one of the first and second partial panel regions may form discharge paths for discharging parasitic capacitors of OLEDs of the plurality of pixels included in the non-driven one of the first and second partial panel regions to the initialization voltage line, and may form leakage current paths for allowing leakage currents of driving transistors to flow to the initialization voltage line.
In example embodiments, in the partial driving mode, the diode initialization signals applied to the non-driven one of the first and second partial panel regions may concurrently have an on-level for at least one horizontal time.
In example embodiments, in the partial driving mode, the diode initialization signals applied to the non-driven one of the first and second partial panel regions may sequentially have an on-level in a first frame period of the partial driving mode, and may be maintained as the on-level until a driving mode of the OLED display device is changed to the normal driving mode.
In example embodiments, the first partial panel region may include first through N-th pixel rows, the second partial panel region may include (N+1)-th through (N+M)-th pixel rows, and the scan signals may include first through (N+M)-th scan signals, where each of N and M is an integer greater than 1. The scan driver may include a first scan stage configured to apply the first scan signal to the first pixel row in response to a first scan start signal, second through N-th scan stages configured to apply the second through N-th scan signals to the second through N-th pixel rows in response to the first through (N−1)-th scan signals, a scan input control circuit configured to selectively output a second scan start signal or the N-th scan signal in response to a mode control signal, an (N+1)-th scan stage configured to apply the (N+1)-th scan signal to the (N+1)-th pixel row in response to an output signal of the scan input control circuit, and (N+2)-th through (N+M)-th scan stages configured to apply the (N+2)-th through (N+M)-th scan signals to the (N+2)-th through (N+M)-th pixel rows in response to the (N+1)-th through (N+M−1)-th scan signals.
In example embodiments, the scan input control circuit may include a first scan input control transistor configured to output the N-th scan signal received from the N-th scan stage in response to the mode control signal having an on-level in the normal driving mode, and a second scan input control transistor configured to output the second scan start signal in response to an inverted mode control signal having the on-level in the partial driving mode.
In example embodiments, in the normal driving mode, the mode control signal may have an on-level, the first scan start signal may include a scan start pulse in each frame period, and the second scan start signal may have an off-level. In the partial driving mode, when the first partial panel region is driven and the second partial panel region is not driven, the mode control signal may have the off-level, the first scan start signal may include the scan start pulse in each frame period, and the second scan start signal may have the off-level. In the partial driving mode, when the first partial panel region is not driven and the second partial panel region is driven, the mode control signal may have the off-level, the first scan start signal may have the off-level, and the second scan start signal may include the scan start pulse in each frame period.
In example embodiments, the first partial panel region may include first through N-th pixel rows, the second partial panel region may include (N+1)-th through (N+M)-th pixel rows, and the diode initialization signals may include first through (N+M)-th diode initialization signals, where each of N and M is an integer greater than 1. The scan driver may include a first diode initialization stage configured to apply the first diode initialization signal to the first pixel row in response to a first diode initialization start signal, second through N-th diode initialization stages configured to apply the second through N-th diode initialization signals to the second through N-th pixel rows in response to the first through (N−1)-th diode initialization signals, a diode initialization input control circuit configured to selectively output a second diode initialization start signal or the N-th diode initialization signal in response to a mode control signal, an (N+1)-th diode initialization stage configured to apply the (N+1)-th diode initialization signal to the (N+1)-th pixel row in response to an output signal of the diode initialization input control circuit, and (N+2)-th through (N+M)-th diode initialization stages configured to apply the (N+2)-th through (N+M)-th diode initialization signals to the (N+2)-th through (N+M)-th pixel rows in response to the (N+1)-th through (N+M−1)-th diode initialization signals.
In example embodiments, the diode initialization input control circuit may include a first diode initialization input control transistor configured to output the N-th diode initialization signal received from the N-th diode initialization stage in response to the mode control signal having an on-level in the normal driving mode, and a second diode initialization input control transistor configured to output the second diode initialization start signal in response to an inverted mode control signal having the on-level in the partial driving mode.
In example embodiments, in the normal driving mode, the mode control signal may have an on-level, the first diode initialization start signal may include a diode initialization start pulse in each frame period, and the second diode initialization start signal may have an off-level. In the partial driving mode, when the first partial panel region is driven and the second partial panel region is not driven, the mode control signal may have the off-level, the first diode initialization start signal may include the diode initialization start pulse in each frame period, and the second diode initialization start signal may have the on-level. In the partial driving mode, when the first partial panel region is not driven and the second partial panel region is driven, the mode control signal may have the off-level, the first diode initialization start signal may have the on-level, and the second diode initialization start signal may include the diode initialization start pulse in each frame period.
In example embodiments, the first through N-th diode initialization stages may operate in response to first and second diode initialization clock signals, and the (N+1)-th through (N+M)-th diode initialization stages may operate in response to third and fourth diode initialization clock signals. In the normal driving mode, the first and second diode initialization clock signals may have same phases as those of the third and fourth diode initialization clock signals, respectively. In the partial driving mode, when the first partial panel region is driven and the second partial panel region is not driven, the first and second diode initialization clock signals may periodically toggle between an on-level and an off-level, the third and fourth diode initialization clock signals may have the on-level, and the second diode initialization start signal may include a diode initialization start pulse in a first frame period of the partial driving mode. In the partial driving mode, when the first partial panel region is not driven and the second partial panel region is driven, the first and second diode initialization clock signals may have the on-level, the third and fourth diode initialization clock signals may periodically toggle between the on-level and the off-level, and the first diode initialization start signal may include the diode initialization start pulse in the first frame period of the partial driving mode.
According to example embodiments, there is provided an OLED display device including a display panel including a first partial panel region including first through N-th pixel rows and a second partial panel region including (N+1)-th through (N+M)-th pixel rows, where each of N and M is an integer greater than 1, a scan driver configured to sequentially apply scan signals to the first through (N+1)-th pixel rows in a normal driving mode where both of the first and second partial panel regions are driven, and to sequentially apply the scan signals to the (N+1)-th through (N+M)-th pixel rows in a partial driving mode where the first partial panel region is not driven and the second partial panel region is driven, and a data driver configured to apply data signals to the first through (N+M)-th pixel rows in the normal driving mode, and to apply the data signals to the (N+1)-th through (N+M)-th pixel rows in the partial driving mode where the first partial panel region is not driven and the second partial panel region is driven. In the normal driving mode, the scan driver is configured to sequentially apply diode initialization signals to the first through (N+M)-th pixel rows. In the partial driving mode where the first partial panel region is not driven and the second partial panel region is driven, the scan driver is configured to sequentially apply the diode initialization signals to the (N+1)-th through (N+M)-th pixel rows, and to concurrently apply the diode initialization signals to the first through N-th pixel rows.
In example embodiments, in the partial driving mode where the first partial panel region is not driven and the second partial panel region is driven, the scan signals and the data signals may not be applied to the first through N-th pixel rows.
In example embodiments, in the partial driving mode where the first partial panel region is not driven and the second partial panel region is driven, OLEDs of pixels included in the first partial panel region may be initialized in response to the concurrently applied diode initialization signals.
In example embodiments, in the partial driving mode where the first partial panel region is not driven and the second partial panel region is driven, pixels included in the first partial panel region may form leakage current paths from a power supply voltage line to an initialization voltage line in response to the concurrently applied diode initialization signals.
In example embodiments, in the partial driving mode where the first partial panel region is not driven and the second partial panel region is driven, the diode initialization signals applied to first partial panel region may sequentially have an on-level in a first frame period of the partial driving mode, and may be maintained as the on-level until a driving mode of the OLED display device is changed to the normal driving mode.
In example embodiments, in the partial driving mode where the first partial panel region is driven and the second partial panel region is not driven, the scan driver may sequentially apply the diode initialization signals to the first through N-th pixel rows, and may concurrently apply the diode initialization signals to the (N+1)-th through (N+M)-th pixel rows.
As described above, the OLED display device according to example embodiments may concurrently apply diode initialization signals to a partial panel region that is not driven in a partial driving mode, thereby forming, in pixels of the non-driven partial panel region, discharge paths for discharging parasitic capacitors of OLEDs and leakage current paths where leakage currents of driving transistors flow. Accordingly, the non-driven partial panel region may be prevented or reduced from undesirably emitting light.
Illustrative, non-limiting example embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.
The example embodiments are described more fully hereinafter with reference to the accompanying drawings. Like or similar reference numerals refer to like or similar elements throughout.
Referring to
The display panel 110 may include a plurality of data lines, a plurality of scan lines, a plurality of gate initialization lines, a plurality of diode initialization lines, a plurality of emission control lines, and a plurality of pixels PX connected thereto. The display panel 110 may be an OLED display panel where each pixel PX includes an OLED. In some example embodiments, the display panel 110 may be a flexible display panel, such as a foldable display panel, a rollable display panel, a stretchable display panel, etc.
In some example embodiments, as illustrated in
As illustrated in
In an example embodiment, where the display panel 110 is a foldable display panel, and the display panel 110 is folded such that the first partial panel region PPR1 is located in the rear of the OLED display device 100, the first partial panel region PPR1 may not be driven and the second partial panel region PPR2 may be driven in the partial driving mode. Although
The data driver 130 may provide the data signals DS to the plurality of pixels PX based on image data DAT and a data control signal DCTRL received from the controller 190. In some example embodiments, the data control signal DCTRL may include, but not limited to, a horizontal start signal and a load signal. In the normal driving mode where both of the first and second partial panel regions PPR1 and PPR2 are driven, the data driver 130 may apply the data signals DS to the first and second partial panel regions PPR1 and PPR2. In the partial driving mode where one of the first and second partial panel regions PPR1 and PPR2 is driven and the other one of the first and second partial panel regions PPR1 and PPR2 is not driven, the data driver 130 may apply the data signals DS to the driven one of the first and second partial panel regions PPR1 and PPR2, and may not apply the data signals DS to the non-driven one of the first and second partial panel regions PPR1 and PPR2. For example, in the partial driving mode where the first partial panel region PPR1 is not driven and the second partial panel region PPR2 is driven, the data driver 130 may not apply the data signals DS to the first through N-th pixel rows PXR1 through PXRN, and may apply the data signals DS to the (N+1)-th through (N+M)-th pixel rows PXRN+1 through PXRN+M.
The scan driver 150 may sequentially provide the scan signals GW1 through GWN+M, the gate initialization signals GI1 through GIN+M and the diode initialization signals GB1 through GBN+M on a pixel row basis based on a scan control signal received from the controller 190. In some example embodiments, the scan control signal may include, but is not limited to, a mode control signal MCS, first and second scan start signals GW_FLM1 and GW_FLM2, first and second scan clock signals GW_CLK1 and GW_CLK2, first and second gate initialization start signals GI_FLM1 and GI_FLM2, first and second gate initialization clock signals GI_CLK1 and GI_CLK2, first and second diode initialization start signals GB_FLM1 and GB_FLM2, and first and second diode initialization clock signals GB_CLK1 and GB_CLK2. In the normal driving mode where both of the first and second partial panel regions PPR1 and PPR2 are driven, the scan driver 150 may sequentially provide the scan signals GW1 through GWN+M, the gate initialization signals GI1 through GIN+M and the diode initialization signals GB1 through GBN+M to the first and second partial panel regions PPR1 and PPR2 on a pixel row basis. In the partial driving mode where one of the first and second partial panel regions PPR1 and PPR2 is driven and the other one of the first and second partial panel regions PPR1 and PPR2 is not driven, the scan driver 150 may sequentially apply the scan signals (e.g., GWN+1 through GWN+M), the gate initialization signals (e.g., GIN+1 through GIN+M) and the diode initialization signals (e.g., GBN+1 through GBN+M) to the driven one (e.g., PPR2) of the first and second partial panel regions PPR1 and PPR2, and may not apply the scan signals (e.g., GW1 through GWN) and the gate initialization signals (e.g., GI1 through GIN) to the non-driven one (e.g., PPR1) of the first and second partial panel regions PPR1 and PPR2. However, in the partial driving mode, the scan driver 150 may concurrently (e.g., substantially simultaneously) apply the diode initialization signals (e.g., GB1 through GBN) to the non-driven one (e.g., PPR1) of the first and second partial panel regions PPR1 and PPR2.
In some example embodiments, as illustrated in
The emission driver 170 may provide the emission control signals EM1 through EMN+M to the plurality of pixels PX based on an emission driver control signal received from the controller 190. In some example embodiments, the emission driver control signal may include, but is not limited to, the mode control signal MCS, first and second emission control start signals EM_FLM1 and EM_FLM2 and first and second emission control clock signals EM_CLK1 and EM_CLK2. In some example embodiments, in the normal driving mode, the emission driver 170 may sequentially apply the emission control signals EM1 through EMN+M to the first and second partial panel regions PPR1 and PPR2 on a pixel row basis, and thus the first through (N+M)-th pixel rows PXR1 through PXRN+M may sequentially emit light. In the partial driving mode, the emission driver 170 may apply the emission control signals (e.g., EMN+1 through EMN+M) to the driven one (e.g., PPR2) of the first and second partial panel regions PPR1 and PPR2, and may not apply the emission control signals (e.g., EM1 through EMN) to the non-driven one (e.g., PPR1) of the first and second partial panel regions PPR1 and PPR2. In some example embodiments, the emission driver 170 may include a plurality of emission control stages EM_STG for sequentially outputting the emission control signals EM1 through EMN+M.
Although
The controller (e.g., a timing controller) 190 may receive the image data DAT and a control signal CTRL from an external host (e.g., a graphic processing unit (GPU) or a graphic card). In some example embodiments, the control signal CTRL may include, but not limited to, a main clock signal, a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, etc. The controller 190 may control the data driver 130 by providing the image data DAT and the data control signal DCTRL to the data driver 130, may control the scan driver 150 by providing the mode control signal MCS, the start signals GW_FLM1, GW_FLM2, GI_FLM1, GI_FLM2, GB_FLM1 and GB_FLM2 and the clock signal GW_CLK1, GW_CLK2, GI_CLK1, GI_CLK2, GB_CLK1, and GB_CLK2 to the scan driver 150, and may control the emission driver 170 by providing the mode control signal MCS, the first and second emission control start signals EM_FLM1 and EM_FLM2, and first and second emission control clock signals EM_CLK1 and EM_CLK2 to the emission driver 170.
In the partial driving mode, even if the data signals DS are not applied to the non-driven partial panel region, the non-driven partial panel region may undesirably emit light due to remaining currents or leakage currents. For example, in a pixel PX of the non-driven partial panel region, remaining currents caused by the data signal DS in a previous frame period may exist in a parasitic capacitor COLED (e.g., as shown in
However, in the OLED display device 100 according to example embodiments, the scan driver 150 may concurrently (e.g., substantially simultaneously) apply the diode initialization signals (e.g., GB1 through GBN) to the non-driven partial panel region (e.g., PPR1) in the partial driving mode. Here, that the scan driver 150 concurrently (e.g., substantially simultaneously) applies the diode initialization signals (e.g., GB1 through GBN) to the non-driven partial panel region (e.g., PPR1) may mean that the scan driver 150 applies the diode initialization signals (e.g., GB1 through GBN) concurrently (e.g., substantially simultaneously) having an on-level (e.g., a low level) for more than a set or predetermined time to the non-driven partial panel region (e.g., PPR1). In some example embodiments, in the partial driving mode, the diode initialization signals (e.g., GB1 through GBN) applied to the non-driven partial panel region (e.g., PPR1) may concurrently (e.g., substantially simultaneously) have the on-level for at least one horizontal time. In other example embodiments, in the partial driving mode, the diode initialization signals (e.g., GB1 through GBN) applied to the non-driven partial panel region (e.g., PPR1) may sequentially have the on-level in a first frame period of the partial driving mode, and may be maintained as the on-level until a driving mode of the OLED display device 100 is changed to the normal driving mode.
In the partial driving mode, once the diode initialization signals (e.g., GB1 through GBN) are concurrently (e.g., substantially simultaneously) applied to the non-driven partial panel region (e.g., PPR1), the organic light emitting diodes EL of the pixels PX in the non-driven partial panel region (e.g., PPR1) may be initialized in response to the concurrently (e.g., simultaneously) applied diode initialization signals (e.g., GB1 through GBN). Further, in the partial driving mode, the pixels PX in the non-driven partial panel region (e.g., PPR1) may form leakage current paths LCPATH from the power supply voltage line ELVDDL to the initialization voltage line VINITL in response to the concurrently (e.g., simultaneously) applied diode initialization signals (e.g., GB1 through GBN). For example, in the partial driving mode, the diode initialization transistors T7 of the pixels PX in the non-driven partial panel region (e.g., PPR1) may be turned on in response to the concurrently (e.g., simultaneously) applied diode initialization signals (e.g., GB1 through GBN). The turned-on diode initialization transistors T7 of the pixels PX in the non-driven partial panel region (e.g., PPR1) may form discharge paths DPATH for discharging the parasitic capacitors COLED of the organic light emitting diodes EL to the initialization voltage line VINITL, and may form leakage current paths LCPATH for allowing the leakage currents of the driving transistors T1 (and the emission transistors T5 and T6) to flow to the initialization voltage line VINITL. Accordingly, the remaining currents in the parasitic capacitors COLED of the organic light emitting diodes EL may be removed through the discharge paths DPATH, the leakage currents of the driving transistors T1 (and the emission transistors T5 and T6) may be prevented or reduced by the leakage current paths LCPATH from being applied to the organic light emitting diodes EL, and thus the undesirable light emission of the pixels PX in the non-driven partial panel region (e.g., PPR1) caused by the remaining currents and the leakage currents may be prevented or reduced.
As described above, the OLED display device 100 according to example embodiments may concurrently (e.g., simultaneously) apply the diode initialization signals (e.g., GB1 through GBN) to the non-driven partial panel region (e.g., PPR1) in the partial driving mode, thereby forming the discharge paths DPATH for discharging the parasitic capacitors COLED of the organic light emitting diodes EL and the leakage current paths LCPATH for allowing the leakage currents of the driving transistors T1 to flow in the pixels PX of the non-driven partial panel region (e.g., PPR1). Accordingly, the undesirable light emission of the non-driven partial panel region (e.g., PPR1) may be prevented or reduced.
Referring to
The first through (N+M)-th scan stages GW_STG1 through GW_STGN+M may sequentially apply the first through (N+M)-th scan signals GW1 through GWN+M to first through (N+M)-th pixel rows PXR1 through PXRN+M based on first and second scan start signals GW_FLM1 and GW_FLM2 and first and second scan clock signals GW_CLK1 and GW_CLK2. In some example embodiments, the first and second scan clock signals GW_CLK1 and GW_CLK2 may have opposite phases to each other. In some example embodiments, odd-numbered scan stages (e.g., GW_STG1, GW_STGN+1, etc.) may output the scan signals (e.g., GW1, GWN+1, etc.) in response to the second scan clock signal GW_CLK2, and even-numbered scan stages (e.g., GW_STG2, GW_STGN, GW_STGN+2, GW_STGN+M, etc.) may output the scan signals (e.g., GW2, GWN, GWN+2, GWN+M, etc.) in response to the first scan clock signal GW_CLK1. In some example embodiments, as illustrated in
For example, in each stage STG of the first through (N+M)-th scan stages GW_STG1 through GW_STGN+M, the first transistor M1 may transfer the start signal FLM or the previous output signal POUT to a first node N1 in response to the first clock signal CLK1 (or the second clock signal CLK2 in case of the even-numbered scan stage), the second transistor M2 may transfer a high gate voltage VGH to a third node N3 in response to a voltage of a second node N2, the third transistor M3 may transfer a voltage of the third node N3 to the first node N1 in response to the second clock signal CLK2 (or the first clock signal CLK1 in case of the even-numbered scan stage), the fourth transistor M4 may transfer the first clock signal CLK1 (or the second clock signal CLK2 in case of the even-numbered scan stage) to the second node N2 in response to a voltage of the first node N1, the fifth transistor M5 may transfer a low gate voltage VGL to the second node N2 in response to the first clock signal CLK1 (or the second clock signal CLK2 in case of the even-numbered scan stage), the sixth transistor M6 may output the high gate voltage VGH as the output signal OUT to an output node NO in response to the voltage of the second node N2, and the seventh transistor M7 may output the second clock signal CLK2 (or the first clock signal CLK1 in case of the even-numbered scan stage) as the output signal OUT to the output node NO in response to the voltage of the first node N1. Further, the first capacitor C1 may be connected between a line of the high gate voltage VGH and the second node N2, and the second capacitor C2 may be connected between the first node N1 and the output node NO. Although
In some example embodiments, the first scan stage GW_STG1 may apply the first scan signal GW1 to the first pixel row PXR1 in response to the first scan start signal GW_FLM1, and the second through N-th scan stages GW_STG2 through GW_STGN may apply the second through N-th scan signals GW2 through GWN to the second through N-th pixel rows PXR2 through PXRN in response to a previous scan signal, or the first through (N−1)-th scan signals GW through GWN−1.
The scan input control circuit GWICT1 and GWICT2 may selectively output the second scan start signal GW_FLM2 or the N-th scan signal GWN in response to a mode control signal MCS. The scan input control circuit GWICT1 and GWICT2 may output the N-th scan signal GWN when the mode control signal MCS represents a normal driving mode, or when the mode control signal MCS has an on-level, and may output the second scan start signal GW_FLM2 when the mode control signal MCS represents a partial driving mode, or when the mode control signal MCS has an off-level.
In some example embodiments, the scan input control circuit GWICT1 and GWICT2 may include a first scan input control transistor GWICT1 that outputs the N-th scan signal GWN received from the N-th scan stage GW_STGN in response to the mode control signal MCS having the on-level in the normal driving mode, and a second scan input control transistor GWICT2 that outputs the second scan start signal GW_FLM2 in response to the inverted mode control signal/MCS having the on-level in the partial driving mode.
The (N+1)-th scan stage GW_STGN+1 may apply the (N+1)-th scan signal GWN+1 to the (N+1)-th pixel row PXRN+1 in response to an output signal (i.e., the second scan start signal GW_FLM2 or the N-th scan signal GWN) of the scan input control circuit GWICT1 and GWICT2. The (N+2)-th through (N+M)-th scan stages GW_STGN+2 through GW_STGN+M may apply the (N+2)-th through (N+M)-th scan signals GWN+2 through GWN+M to the (N+2)-th through (N+M)-th pixel rows PXRN+2 through PXRN+M in response to a previous scan signal, or the (N+1)-th through (N+M−1)-th scan signals GWN+1 through GWN+M−1.
In the normal driving mode, the mode control signal MCS may have the on-level, the first scan start signal GW_FLM1 may include a scan start pulse in each frame period, and the second scan start signal GW_FLM2 may have the off-level. Accordingly, the scan input control circuit GWICT1 and GWICT2 may output the N-th scan signal GWN, and the first through (N+M)-th scan stages GW_STG1 through GW_STGN+M may sequentially apply the first through (N+M)-th scan signals GW1 through GWN+M to the first through (N+M)-th pixel rows PXR1 through PXRN+M.
In the partial driving mode, when a first partial panel region PPR1 is driven and a second partial panel region PPR2 is not driven, the mode control signal MCS may have the off-level, the first scan start signal GW_FLM1 may include the scan start pulse in each frame period, and the second scan start signal GW_FLM2 may have the off-level. In this case, the first through N-th scan stages GW_STG1 through GW_STGN may sequentially apply the first through N-th scan signals GW1 through GWN to the first through N-th pixel rows PXR1 through PXRN in response to the first scan start signal GW_FLM1 in each frame period. Although the scan input control circuit GWICT1 and GWICT2 outputs the second scan start signal GW_FLM2, because the second scan start signal GW_FLM2 has the off-level, the (N+1)-th through (N+M)-th scan stages GW_STGN+1 through GW_STGN+M may not apply the (N+1)-th through (N+M)-th scan signals GWN+1 through GWN+M to the (N+1)-th through (N+M)-th pixel rows PXRN+1 through PXRN+M.
In the partial driving mode, when the first partial panel region PPR1 is not driven and the second partial panel region PPR2 is driven, the mode control signal MCS may have the off-level, the first scan start signal GW_FLM1 may have the off-level, and the second scan start signal GW_FLM2 may include the scan start pulse in each frame period. In this case, because the first scan start signal GW_FLM1 has the off-level, the first through N-th scan stages GW_STG1 through GW_STGN may not apply the first through N-th scan signals GW1 through GWN to the first through N-th pixel rows PXR1 through PXRN. The scan input control circuit GWICT1 and GWICT2 may output the second scan start signal GW_FLM2, and the (N+1)-th through (N+M)-th scan stages GW_STGN+1 through GW_STGN+M may sequentially apply the (N+1)-th through (N+M)-th scan signals GWN+1 through GWN+M to the (N+1)-th through (N+M)-th pixel rows PXRN+1 through PXRN+M in response to the second scan start signal GW_FLM2 in each frame period.
The first through (N+M)-th gate initialization stages GI_STG1 through GI_STGN+M may sequentially apply the first through (N+M)-th gate initialization signals GI1 through GIN+M to the first through (N+M)-th pixel rows PXR1 through PXRN+M based on first and second gate initialization start signals GI_FLM1 and GI_FLM2 and first and second gate initialization clock signals GI_CLK1 and GI_CLK2. In some example embodiments, the first and second gate initialization clock signals GI_CLK1 and GI_CLK2 may have opposite phases to each other. In some example embodiments, odd-numbered gate initialization stages (e.g., GI_STG1, GI_STGN+1, etc.) may output the gate initialization signals (e.g., GI1, GIN+1, etc.) in response to the second gate initialization clock signal GI_CLK2, and even-numbered gate initialization stages (e.g., GI_STG2, GI_STGN, GI_STGN+2, GI_STGN+M, etc.) may output the gate initialization signals (e.g., GI2, GIN, GIN+2, GIN+M, etc.) in response to the first gate initialization clock signal GI_CLK1. In some example embodiments, as illustrated in
The gate initialization input control circuit GIICT1 and GIICT2 may include a first gate initialization input control transistor GIICT1 that outputs the N-th gate initialization signal GIN received from the N-th gate initialization stage GI_STGN in response to the mode control signal MCS having the on-level in the normal driving mode, and a second gate initialization input control transistor GIICT2 that outputs the second gate initialization start signal GI_FLM2 in response to the inverted mode control signal /MCS having the on-level in the partial driving mode.
In the normal driving mode, the mode control signal MCS may have the on-level, the first gate initialization start signal GI_FLM1 may include a gate initialization start pulse in each frame period, and the second gate initialization start signal GI_FLM2 may have the off-level. Accordingly, the gate initialization input control circuit GIICT1 and GIICT2 may output the N-th gate initialization signal GIN, and the first through (N+M)-th gate initialization stages GI_STG1 through GI_STGN+M may sequentially apply the first through (N+M)-th gate initialization signals GI1 through GIN+M to the first through (N+M)-th pixel rows PXR1 through PXRN+M.
In the partial driving mode, when the first partial panel region PPR1 is driven and the second partial panel region PPR2 is not driven, the mode control signal MCS may have the off-level, the first gate initialization start signal GI_FLM1 may include the gate initialization start pulse in each frame period, and the second gate initialization start signal GI_FLM2 may have the off-level. In this case, the first through N-th gate initialization stages GI_STG1 through GI_STGN may sequentially apply the first through N-th gate initialization signals GI1 through GIN to the first through N-th pixel rows PXR1 through PXRN in each frame period, and the (N+1)-th through (N+M)-th gate initialization stages GI_STGN+1 through GI_STGN+M may not apply the (N+1)-th through (N+M)-th gate initialization signals GIN+1 through GIN+M to the (N+1)-th through (N+M)-th pixel rows PXRN+1 through PXRN+M.
In the partial driving mode, when the first partial panel region PPR1 is not driven and the second partial panel region PPR2 is driven, the mode control signal MCS may have the off-level, the first gate initialization start signal GI_FLM1 may have the off-level, and the second gate initialization start signal GI_FLM2 may include the gate initialization start pulse in each frame period. In this case, the first through N-th gate initialization stages GI_STG1 through GI_STGN may not apply the first through N-th gate initialization signals GI1 through GIN to the first through N-th pixel rows PXR1 through PXRN, and the (N+1)-th through (N+M)-th gate initialization stages GI_STGN+1 through GI_STGN+M may sequentially apply the (N+1)-th through (N+M)-th gate initialization signals GIN+1 through GIN+M to the (N+1)-th through (N+M)-th pixel rows PXRN+1 through PXRN+M in each frame period.
The first through (N+M)-th diode initialization stages GB_STG1 through GB_STGN+M may sequentially apply the first through (N+M)-th diode initialization signals GB1 through GBN+M to the first through (N+M)-th pixel rows PXR1 through PXRN+M based on first and second diode initialization start signals GB_FLM1 and GB_FLM2 and first and second diode initialization clock signals GB_CLK1 and GB_CLK2. In some example embodiments, the first and second diode initialization clock signals GB_CLK1 and GB_CLK2 may have opposite phases to each other. In some example embodiments, odd-numbered diode initialization stages (e.g., GB_STG1, GB_STGN+1, etc.) may output the diode initialization signals (e.g., GB1, GBN+1, etc.) in response to the second diode initialization clock signal GB_CLK2, and even-numbered diode initialization stages (e.g., GB_STG2, GB_STGN, GB_STGN+2, GB_STGN+M, etc.) may output the diode initialization signals (e.g., GB2, GBN, GBN+2, GBN+M, etc.) in response to the first diode initialization clock signal GB_CLK1. In some example embodiments, as illustrated in
The diode initialization input control circuit GBICT1 and GBICT2 may include a first diode initialization input control transistor GBICT1 that outputs the N-th diode initialization signal GBN received from the N-th diode initialization stage GB_STGN in response to the mode control signal MCS having the on-level in the normal driving mode, and a second diode initialization input control transistor GBICT2 that outputs the second diode initialization start signal GB_FLM2 in response to the inverted mode control signal /MCS having the on-level in the partial driving mode.
In the normal driving mode, the mode control signal MCS may have the on-level, the first diode initialization start signal GB_FLM1 may include a diode initialization start pulse in each frame period, and the second diode initialization start signal GB_FLM2 may have the off-level. Accordingly, the diode initialization input control circuit GBICT1 and GBICT2 may output the N-th diode initialization signal GBN, and the first through (N+M)-th diode initialization stages GB_STG1 through GB_STGN+M may sequentially apply the first through (N+M)-th diode initialization signals GB1 through GBN+M to the first through (N+M)-th pixel rows PXR1 through PXRN+M.
In the partial driving mode, when the first partial panel region PPR1 is driven and the second partial panel region PPR2 is not driven, the mode control signal MCS may have the off-level, the first diode initialization start signal GB_FLM1 may include the diode initialization start pulse in each frame period, and the second diode initialization start signal GB_FLM2 may have the on-level. In this case, the first through N-th diode initialization stages GB_STG1 through GB_STGN may sequentially apply the first through N-th diode initialization signals GB1 through GBN to the first through N-th pixel rows PXR1 through PXRN in each frame period. Because the diode initialization input control circuit GBICT1 and GBICT2 outputs the second diode initialization start signal GB_FLM2, and the second diode initialization start signal GB_FLM2 has the on-level, the (N+1)-th through (N+M)-th diode initialization stages GB_STGN+1 through GB_STGN+M may provide the (N+1)-th through (N+M)-th pixel rows PXRN+1 through PXRN+M with the (N+1)-th through (N+M)-th diode initialization signals GBN+1 through GBN+M that sequentially have the on-level in the first frame period of the partial driving mode and are maintained as the on-level until a driving mode is changed to the normal driving mode.
In the partial driving mode, when the first partial panel region PPR1 is not driven and the second partial panel region PPR2 is driven, the mode control signal MCS may have the off-level, the first diode initialization start signal GB_FLM1 may have the on-level, and the second diode initialization start signal GB_FLM2 may include the diode initialization start pulse in each frame period. In this case, the first through N-th diode initialization stages GB_STG1 through GB_STGN may provide the first through N-th pixel rows PXR1 through PXRN with the first through N-th diode initialization signals GB1 through GBN that sequentially have the on-level in the first frame period of the partial driving mode and are maintained as the on-level until the driving mode is changed to the normal driving mode. The (N+1)-th through (N+M)-th diode initialization stages GB_STGN+1 through GB_STGN+M may sequentially apply the (N+1)-th through (N+M)-th diode initialization signals GBN+1 through GBN+M to the (N+1)-th through (N+M)-th pixel rows PXRN+1 through PXRN+M in each frame period.
Referring to
The first through (N+M)-th emission control stages EM_STG1 through EM_STGN+M may sequentially apply the first through (N+M)-th emission control signals EM1 through EMN+M to first through (N+M)-th pixel rows PXR1 through PXRN+M based on first and second emission control start signals EM_FLM1 and EM_FLM2 and first and second emission control clock signals EM_CLK1 and EM_CLK2. In some example embodiments, the first and second emission control clock signals EM_CLK1 and EM_CLK2 may have opposite phases to each other. In some example embodiments, each odd-numbered emission control stage (e.g., EM_STG1, EM_STGN+1, etc.) may receive the first and second emission control clock signals EM_CLK1 and EM_CLK2 at first and second clock inputs, respectively, and each even-numbered emission control stage (e.g., EM_STG2, EM_STGN, EM_STGN+2, EM_STGN+M, etc.) may receive the second and first emission control clock signals EM_CLK2 and EM_CLK1 at the first and second clock inputs, respectively.
In some example embodiments, as illustrated in
Referring to
Referring to
A second diode initialization start signal GB_FLM2 may include the diode initialization start pulse DISP in each frame period, a second gate initialization start signal GI_FLM2 may include the gate initialization start pulse GISP in each frame period, and a second scan start signal GW_FLM2 may include the scan start pulse SSP in each frame period. Accordingly, the (N+1)-th through (N+M)-th diode initialization signals GBN+1 through GBN+M may be sequentially output at each 1H, the (N+1)-th through (N+M)-th gate initialization signals GIN+1 through GIN+M may be sequentially output at each 1 H, and the (N+1)-th through (N+M)-th scan signals GWN+1 through GWN+M may be sequentially output at each 1 H.
An OLED display device 100a of
Referring to
In a normal driving mode, the third diode initialization clock signal GB_CLK3 may have a phase same as a phase of the first diode initialization clock signal GB_CLK1, and the fourth diode initialization clock signal GB_CLK4 may have a phase same as a phase of the second diode initialization clock signal GB_CLK2. Accordingly, the first through (N+M)-th diode initialization stages GB_STG1 through GB_STGN+M may sequentially output first through (N+M)-th diode initialization signals GB1 through GBN+M to first through (N+M)-th pixel rows PXR1 through PXRN+M.
In a partial driving mode where a first partial panel region PPR1 is not driven and a second partial panel region PPR2 is driven, as illustrated in
The third and fourth diode initialization clock signals GB_CLK3 and GB_CLK4 may periodically toggle between the on-level and an off-level, and a second diode initialization start signal GB_FLM2 may include the diode initialization start pulse DISP in each frame period. Accordingly, the (N+1)-th through (N+M)-th diode initialization stages GB_STGN+1 through GB_STGN+M may sequentially output the (N+1)-th through (N+M)-th diode initialization signals GBN+1 through GBN+M to the (N+1)-th through (N+M)-th pixel rows PXRN+1 through PXRN+M.
In a partial driving mode where the first partial panel region PPR1 is driven and the second partial panel region PPR2 is not driven, the first and second diode initialization clock signals GB_CLK1 and GB_CLK2 may periodically toggle between the on-level and the off-level, the third and fourth diode initialization clock signals GB_CLK3 and GB_CLK4 may have the on-level, the first diode initialization start signal GB_FLM1 may include the diode initialization start pulse DISP in each frame period, and the second diode initialization start signal GB_FLM2 may include the diode initialization start pulse DISP in the first frame period FP1 of the partial driving mode. Accordingly, the first through N-th diode initialization stages GB_STG1 through GB_STGN may sequentially output the first through N-th diode initialization signals GB1 through GBN to the first through N-th pixel rows PXR1 through PXRN, and the (N+1)-th through (N+M)-th diode initialization stages GB_STGN+1 through GB_STGN+M may provide the (N+1)-th through (N+M)-th pixel rows PXRN+1 through PXRN+M with the (N+1)-th through (N+M)-th diode initialization signals GBN+1 through GBN+M that sequentially have the on-level in the first frame period FP1 of the partial driving mode and are maintained as the on-level until the driving mode is changed to the normal driving mode.
Referring to
The processor 1110 may perform various computing functions or tasks. The processor 1110 may be an application processor (AP), a micro-processor, a central processing unit (CPU), etc. The processor 1110 may be coupled to other components via an address bus, a control bus, a data bus, etc. Further, in some example embodiments, the processor 1110 may be further coupled to an extended bus such as a peripheral component interconnection (PCI) bus.
The memory device 1120 may store data for operations of the electronic device 1100. For example, the memory device 1120 may include at least one non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistance random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc., and/or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile dynamic random access memory (mobile DRAM) device, etc.
The storage device 1130 may be a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc. The I/O device 1140 may be an input device such as a keyboard, a keypad, a mouse, a touch screen, etc., and/or an output device such as a printer, a speaker, etc. The power supply 1150 may supply power for operations of the electronic device 1100.
The OLED display device 1160 may concurrently (e.g., simultaneously) apply diode initialization signals to a partial panel region that is not driven in a partial driving mode, thereby forming, in pixels of the non-driven partial panel region, discharge paths for discharging parasitic capacitors of OLEDs and leakage current paths where leakage currents of driving transistors flow. Accordingly, the non-driven partial panel region may be prevented or reduced from undesirably emitting light.
In some example embodiments, the electronic device 1100 be any electronic device including the OLED display device 1160, such as a cellular phone, a smart phone, a tablet computer, a wearable device, a virtual reality (VR) device, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation system, a digital television, a 3D television, a personal computer (PC), a home appliance, a laptop computer, etc.
It will be understood that, although the terms “first”, “second”, “third”, etc., may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed herein could be termed a second element, component, region, layer or section, without departing from the spirit and scope of the inventive concept.
Spatially relative terms, such as “beneath”, “below”, “lower”, “under”, “above”, “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that such spatially relative terms are intended to encompass different orientations of the device in use or in operation, in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” or “under” other elements or features would then be oriented “above” the other elements or features. Thus, the example terms “below” and “under” can encompass both an orientation of above and below. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
The terminology used herein is for the purpose of describing aspects of some example embodiments only and is not intended to be limiting of the inventive concept. As used herein, the terms “substantially,” “about,” and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art.
As used herein, the singular forms “a” and “an” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising”, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. Further, the use of “may” when describing embodiments of the inventive concept refers to “one or more embodiments of the present invention”. Also, the term “exemplary” is intended to refer to an example or illustration. As used herein, the terms “use,” “using,” and “used” may be considered synonymous with the terms “utilize,” “utilizing,” and “utilized,” respectively.
It will be understood that when an element or layer is referred to as being “on”, “connected to”, “coupled to”, or “adjacent to” another element or layer, it may be directly on, connected to, coupled to, or adjacent to the other element or layer, or one or more intervening elements or layers may be present. In contrast, when an element or layer is referred to as being “directly on”, “directly connected to”, “directly coupled to”, or “immediately adjacent to” another element or layer, there are no intervening elements or layers present.
The foregoing is illustrative of example embodiments and is not to be construed as limiting thereof. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the example embodiments without materially departing from the novel teachings and advantages of the present inventive concept. Accordingly, all such modifications are intended to be included within the scope of the present inventive concept as defined in the claims. Therefore, it is to be understood that the foregoing is illustrative of various example embodiments and is not to be construed as limited to the specific example embodiments disclosed, and that modifications to the disclosed example embodiments, as well as other example embodiments, are intended to be included within the scope of the appended claims, and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2018-0171982 | Dec 2018 | KR | national |
