This application claims priority to and the benefit of Korean Patent Application No. 10-2012-0084986, filed on Aug. 2, 2012 in the Korean Intellectual Property Office, the entire content of which is incorporated herein by reference.
1. Field
Aspects of embodiments of the present invention relate to photoelectric devices.
2. Description of the Related Art
Recently, due to the increased demand for finite energy sources (such as fossil fuels) and to the worsening global environmental problems, the development of clean energy has accelerated. As a clean energy, solar power generation that uses solar energy is expected to be a widely used energy source since solar energy may be directly converted to electricity.
However, the cost of power generation from an industrial solar cell remains higher than that of fossil fuel power generation. An increase in efficiency of the solar power generation would allow more widespread application of the solar cell. Possible ways of increasing this efficiency include reducing optical loss, reducing recombination loss, and reducing series resistance with respect to an optical current generated in the solar cell. Another way of saving costs is to develop a new structure in which manufacturing costs and process simplification are considered for mass production of high efficiency solar cells.
One or more embodiments of the present invention provide for photoelectric devices that can reduce optical loss, reduce recombination loss of carriers, and have a simplified manufacturing process. Additional aspects will be set forth in part in the description that follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments.
According to an exemplary embodiment of the present invention, a photoelectric device is provided. The photoelectric device includes a semiconductor substrate, a first semiconductor stack on a first surface of the semiconductor substrate and having a first conductivity, and a second semiconductor stack on the first surface of the semiconductor substrate and having a second conductivity opposite to the first conductivity. Edge portions of the first and second semiconductor stacks face each other with an insulating portion therebetween.
The first semiconductor stack may constitute a base for collecting major carriers and the second semiconductor stack may constitute an emitter for collecting minor carriers.
The edge portion of the first semiconductor stack, the insulating portion, and the edge portion of the second semiconductor stack may be stacked sequentially from the semiconductor substrate.
The edge portions of the first and second semiconductor stacks may be vertically separated from each other by a first height.
The edge portion of the second semiconductor stack may be supported on the insulation portion. An edge surface of the second semiconductor stack and an edge surface of the insulating portion may be aligned with each other.
The edge portion of the first semiconductor stack may extend on the semiconductor substrate in a first direction parallel to the semiconductor substrate.
The edge portion of the second semiconductor stack may be vertically separated by a second height from a main body portion of the second semiconductor stack that extends in a first direction parallel to the semiconductor substrate.
The second semiconductor stack may further include a connection portion that extends in a second direction different from the first direction to connect the main body portion and the edge portion.
The connection portion of the second semiconductor stack may extend in the second direction to cover an edge surface of the first semiconductor stack and the edge surface of the insulating portion.
The connection portion of the second semiconductor stack may contact the edge surface of the first semiconductor stack.
The first semiconductor stack may include a first intrinsic semiconductor layer and a first conductive semiconductor layer that extend in the first direction on the semiconductor substrate. The connection portion of the second semiconductor stack may include a second intrinsic semiconductor layer and a second conductive semiconductor layer that extend parallel to each other in the second direction.
The second intrinsic semiconductor layer may contact an edge surface of the first intrinsic semiconductor layer.
The second intrinsic semiconductor layer may contact the first intrinsic semiconductor layer along a thickness direction of the first intrinsic semiconductor layer. The first intrinsic semiconductor layer may have a thickness smaller than that of the first conductive semiconductor layer.
The second intrinsic semiconductor layer may contact an edge surface of the first conductive semiconductor layer.
The second intrinsic semiconductor layer may constitute an emitter having a band gap narrower than that of the first intrinsic semiconductor layer constituting a base.
The insulating portion may include a silicon nitride film.
The first semiconductor stack may include a first intrinsic semiconductor layer and a first conductive semiconductor layer stacked on the semiconductor substrate. The second semiconductor stack may include a second intrinsic semiconductor layer and a second conductive semiconductor layer.
The photoelectric device may further include first and second transparent conductive films respectively on the first and second conductive semiconductor layers.
The photoelectric device may further include first and second metal films respectively on the first and second transparent conductive films.
These and/or other aspects will become apparent and more readily appreciated from the following description of exemplary embodiments, taken in conjunction with the accompanying drawings of which:
The present invention will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown.
Referring to
The semiconductor substrate 100 has a first surface S1 and a second surface S2 opposite to the first surface S1. A base electrode (such as the first electrode 115) and an emitter electrode (such as the second electrode 125) are formed on the first surface S1. Accordingly, the second surface S2 (from which an electrode structure has been removed) functions as a light receiving surface. Thus, effective incident light may be increased and optical loss may be reduced. That is, by not forming electrodes on the light receiving surface S2, optical loss caused by the electrodes may be reduced and a high output may be obtained when compared to a solar cell in which electrodes are formed on the light receiving surface S2.
When the semiconductor substrate 100 receives light through the second surface S2, the semiconductor substrate 100 generates optical generation carriers (hereinafter, carriers). The carriers include holes and electrons from the semiconductor substrate 100. The semiconductor substrate 100 may be, for example, a monocrystalline silicon substrate or a polycrystalline silicon substrate having an n-type or a p-type conductivity. For example, the semiconductor substrate 100 may be an n-type monocrystalline silicon substrate. For ease of description, the semiconductor substrate 100 of the exemplary embodiment of
In the exemplary embodiment of claim 1, a texture structure 190 having a corrugated pattern is formed on the second surface S2 of the semiconductor substrate 100. The texture structure 190 reduces a reflection rate of incident light, and has a corrugated surface that includes a plurality of fine protrusions. A passivation film 181 is formed on the second surface S2 of the semiconductor substrate 100. The passivation film 181 reduces or prevents recombination of the carriers generated in the semiconductor substrate 100, which may lead to increased carrier collection efficiency.
The passivation film 181 may be formed, for example, of a material doped with a dopant that has the same conductivity as the semiconductor substrate 100. For example, the passivation film 181 may be a highly doped n+ layer formed on the second surface S2 of the semiconductor substrate 100. The passivation film 181 may form a front surface field (FSF) for reducing the surface recombination loss. The passivation film 181 may be formed, for example, of a silicon oxide (SiOx) film or a silicon nitride (SiNx) film.
A reflection prevention film 182 is formed on the passivation film 181. The reflection prevention film 182 is formed on the second surface S2, which is the light receiving surface S2. The reflection prevention film 182 may increase optical absorption of the semiconductor substrate 100 by reducing reflection of incident light, which may lead to increased optical collection efficiency. The reflection prevention film 182 may be formed, for example, of a silicon oxide film or a silicon nitride film. For example, the reflection prevention film 182 may be a monolayer of a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, or may be a composite layer of a silicon oxide (SiOx) film and a silicon nitride (SiNx) film, which have refractive indexes that are different from each other.
In the exemplary embodiment of
Returning to the exemplary embodiment of
The first semiconductor stack 110 includes a first intrinsic semiconductor layer 111 and a first conductive semiconductor layer 113, which are sequentially stacked on the semiconductor substrate 100. The first intrinsic semiconductor layer 111 and the first conductive semiconductor layer 113 may be formed, for example, of amorphous silicon a-Si or fine crystal silicon μc-Si. For example, the first intrinsic semiconductor layer 111 and the first conductive semiconductor layer 113 may be formed of hydrogenated amorphous silicon a-Si:H. For ease of description, the first intrinsic semiconductor layer 111 and the first conductive semiconductor layer 113 of the exemplary embodiment of
The first intrinsic semiconductor layer 111 may be formed, for example, without adding a dopant or by adding a minor amount of a dopant. The first intrinsic semiconductor layer 111 may passivate the first surface S1 of the semiconductor substrate 100 to reduce or prevent recombination of carriers generated in the semiconductor substrate 100. Further, the first intrinsic semiconductor layer 111 may increase an interface characteristic between the semiconductor substrate 100 formed of crystalline silicon and the first conductive semiconductor layer 113 formed of amorphous silicon.
The first conductive semiconductor layer 113 may be formed, for example, by adding an n-type or a p-type dopant. For example, the first conductive semiconductor layer 113 may be doped with an n-type dopant, which is the same conductivity as the semiconductor substrate 100. In addition, the first conductive semiconductor layer 113 may form a base that collects major carriers (electrons) from the n-type semiconductor substrate 100.
A first electrode 115 is formed on the first semiconductor stack 110. The first electrode 115 includes a first transparent conductive film 116 that is electrically conductive and optically transparent. For example, the first transparent conductive film 116 may be formed of a transparent conducting oxide (TCO) such as indium tin oxide (ITO) or zinc oxide (ZnO). The first electrode 115 further includes a first metal film 117 on the first transparent conductive film 116. The first metal film 117 may include, for example, a metal such as Ag, Al, Cu, or Ni. The first metal film 117 may be formed of a metal having high electrical conductivity to reduce series resistance because the first metal film 117 forms an optical current path. The first transparent conductive film 116 and the first metal film 117 are sequentially stacked on the first semiconductor stack 110. Accordingly, the first transparent conductive film 116 may intermediate an electrical connection (for example, reduce contact resistance) between the first semiconductor stack 110 and the first metal film 117.
The second semiconductor stack 120 includes a second intrinsic semiconductor layer 121 and a second conductive semiconductor layer 123, which are sequentially stacked on the semiconductor substrate 100. The second intrinsic semiconductor layer 121 and the second conductive semiconductor layer 123 may be formed, for example, of amorphous silicon a-Si or fine crystalline silicon μc-Si. For example, the second intrinsic semiconductor layer 121 and the second conductive semiconductor layer 123 may be formed of hydrogenated amorphous silicon a-Si:H. For ease of description, the second intrinsic semiconductor layer 121 and the second conductive semiconductor layer 123 of the exemplary embodiment of
The second intrinsic semiconductor layer 121 may be formed, for example, without adding a dopant or by adding a small amount of a dopant. The second intrinsic semiconductor layer 121 may passivate the semiconductor substrate 100 to reduce or prevent recombination of carriers generated in the semiconductor substrate 100. Further, the second intrinsic semiconductor layer 121 may increase an interface characteristic between the semiconductor substrate 100 formed of crystalline silicon and the second conductive semiconductor layer 123 formed of amorphous silicon.
The second conductive semiconductor layer 123 may be formed, for example, by adding an n-type or a p-type dopant. For example, the second conductive semiconductor layer 123 may be doped with a p-type dopant, which is opposite in conductivity to that of the semiconductor substrate 100. In addition, the second conductive semiconductor layer 123 may form an emitter that collects minor carriers (holes) from the n-type semiconductor substrate 100.
A second electrode 125 is formed on the second semiconductor stack 120. The second electrode 125 includes a second transparent conductive film 126 that is electrically conductive and optically transparent. For example, the second transparent conductive film 126 may be formed of a TCO such as ITO or ZnO. The second electrode 125 further includes a second metal film 127 formed on the second transparent conductive film 126. The second metal film 127 may include, for example, a metal such as Ag, Al, Cu, or Ni. The second metal film 127 may be formed of a metal having high electrical conductivity to reduce series resistance since the second metal film 127 forms an optical current path. The second transparent conductive film 126 and the second metal film 127 are sequentially stacked on the second semiconductor stack 120. Accordingly, the second transparent conductive film 126 may intermediate the electrical connection (for example, reduce contact resistance) between the second semiconductor stack 120 and the second metal film 127.
The first and second semiconductor stacks 110 and 120 are alternately arranged (for example, adjacent) along the first surface S1 of the semiconductor substrate 100. In addition, edge portions 110a and 120a of the first and second semiconductor stacks 110 and 120 overlap each other, thus forming overlapping regions OV. For example, the overlapping regions OV of the first and second semiconductor stacks 110 and 120 may correspond to regions where a first semiconductor region A1 (which is a projected region of the first semiconductor stack 110 onto the semiconductor substrate 100) and a second semiconductor region A2 (which is a projected region of the second semiconductor stack 120 onto the semiconductor substrate 100) overlap.
In the exemplary embodiment of
The first semiconductor stack 110 extends in a first direction Z1 parallel to the semiconductor substrate 100 on the semiconductor substrate 100. Further, the edge portion 110a of the first semiconductor stack 110 is formed at an edge of the first semiconductor stack 110 in the extended direction.
The second semiconductor stack 120 includes a main body portion 120b on the semiconductor substrate 100, the edge portion 120a vertically separated by a second height h2 from the main body portion 120b, and a connection portion 120c that connects the main body portion 120b and the edge portion 120a. The main body portion 120b also extends in the first direction Z1 parallel to the semiconductor substrate 100 on the semiconductor substrate 100. In addition, the edge portion 120a is formed at a second height h2 above the main body portion 120b. The connection portion 120c extends in a second direction Z2 that is perpendicular to the semiconductor substrate 100 to connect the main body portion 120b and the edge portion 120a.
The connection portion 120c of the second semiconductor stack 120 contacts the first semiconductor stack 110. As illustrated in the exemplary embodiment of
The connection portion 120c of the second semiconductor stack 120 includes the second intrinsic semiconductor layer 121 and the second conductive semiconductor layer 123, which are parallel to each other, and contacts the first intrinsic semiconductor layer 111 and the first conductive semiconductor layer 113, which extend in the first direction Z1 on the semiconductor substrate 100. The second intrinsic semiconductor layer 121 contacts the first intrinsic semiconductor layer 111 and the first conductive semiconductor layer 113 by extending in the second direction Z2 to cover the edge surfaces 111a and 113a of the first intrinsic semiconductor layer 111 and the first conductive semiconductor layer 113.
As illustrated in the exemplary embodiment of
When the first and second semiconductor stacks 110 and 120 (having opposite conductivity from each other) contact each other, in a charge separation process in which optical carriers generated in the semiconductor substrate 100 are separately collected in the first and second semiconductor stacks 110 and 120 due to an internal electric field, recombination occurs through a contact between the first and second semiconductor stacks 110 and 120 (that is, between the first intrinsic semiconductor layer 111 and the second intrinsic semiconductor layer 121). Thus, inefficiencies such as a current leakage, recombination loss, and a reduction of carriers may occur. The recombination loss may be reduced or minimized by controlling the thickness t1 of the first intrinsic semiconductor layer 111 (such as making t1 extremely small, e.g., under 50 Å).
Recombination loss may also occur through another contact between the first and second semiconductor stacks 110 and 120, that is, between the second intrinsic semiconductor layer 121 and the first conductive semiconductor layer 113. As shown in
In the exemplary embodiment of
The insulation portion 150 may be formed, for example, of silicon nitride film SiNx. However, the material for forming the insulation portion 150 is not specifically limited. For example, in other embodiments, the insulation portion 150 may be formed of any insulating material that electrically insulates between the edge portions 110a and 120a of the first and second semiconductor stacks 110 and 120. The insulation portion 150 may be formed, for example, as a portion of an insulating layer that serves as an etch stop film (for example, an etch mask) when texturing the second surface S2 of the semiconductor substrate 100. Accordingly, the insulation portion 150 may be formed of a material that has a resistance to a texturing etchant.
Carriers, that is, electrons and holes, are optically generated in the semiconductor substrate 100 and respectively collected in the first and second semiconductor stacks 110 and 120 by charge separation caused by an internal electric field formed by a p-n junction. Band offsets EC1, EV1, EC2, and EV2 are formed at interfaces between the semiconductor substrate 100, and the first intrinsic semiconductor layer 111 and the second intrinsic semiconductor layer 121 according to the band gap difference. In
The movement of the minor carriers (for example, holes) to the first intrinsic semiconductor layer 111 is blocked by a high potential barrier of the valence band offset EV1 formed on the band edge of the first intrinsic semiconductor layer 111. Likewise, the movement of the major carriers (for example, electrons) to the second intrinsic semiconductor layer 121 is blocked by a high potential barrier of the conduction band offset EC2 formed on a band edge of the second intrinsic semiconductor layer 121. Accordingly, the recombination loss of the optically generated carriers due to being diffused in a direction opposite to an internal electric field may be repressed by the band offsets EV1 and EC2 of the first intrinsic semiconductor layer 111 and the second intrinsic semiconductor layer 121.
In an exemplary embodiment, the first intrinsic semiconductor layer 111 and the second intrinsic semiconductor layer 121 are formed to have band gaps E1 and E2 that are different from each other (for example, by controlling a dopant, doping levels, etc.) In particular, the second intrinsic semiconductor layer 121 has a band gap E2 narrower than the band gap E1 of the first intrinsic semiconductor layer 111. For example, the second intrinsic semiconductor layer 121 is formed to have a band gap of 1.76 eV or less, while the first intrinsic semiconductor layer 111 is formed to have a band gap of 1.76 eV or more.
When the second intrinsic semiconductor layer 121 is formed to have a relatively narrow band gap E2, the valence band offset EV2 of the second intrinsic semiconductor layer 121 is reduced and the minor carriers (for example, holes) may readily move to the second intrinsic semiconductor layer 121. Further, when the first intrinsic semiconductor layer 111 is formed to have a relatively wide band gap E1, the valence band offset EV1 of the first intrinsic semiconductor layer 111 is increased and the recombination loss of the minor carriers (for example, holes) due to being diffused into the first intrinsic semiconductor layer 111 may be repressed.
Edge portions 210a and 220a of the first and second semiconductor stacks 210 and 220 form an overlapping region OV′ where the first and second semiconductor stacks 210 and 220 overlap each other. The edge portions 210a and 220a of the first and second semiconductor stacks 210 and 220 contact each other along a width of the overlapping region OV′. Since the edge portions 210a and 220a of the first and second semiconductor stacks 210 and 220 form a relatively long surface contact with each other, during charge separation of carriers optically generated in the semiconductor substrate 200 to the first and second semiconductor stacks 210 and 220, carrier recombination occurs through the contact between the first and second semiconductor stacks 210 and 220. Thus, due to current leakage and recombination loss, an output characteristic is reduced.
In the exemplary photoelectric device of
A gap insulation film 350 is formed between the first and second semiconductor stacks 310 and 320 to insulate between the first and second semiconductor stacks 310 and 320 and to passivate the semiconductor substrate 300 exposed between the first and second semiconductor stacks 310 and 320. The photoelectric device according to the comparative example 2 may be formed such that, after forming a pattern of the gap insulation film 350, the first and second semiconductor stacks 310 and 320 are respectively stacked and patterned. That is, the photoelectric device according to the comparative example 2 is formed through a series of processes such as the forming of the gap insulation film 350, the patterning of the gap insulation film 350, the stacking of the first semiconductor stack 310, the patterning of the first semiconductor stack 310, the stacking of the second semiconductor stack 320, and the patterning of the second semiconductor stack 320.
However, in the process of forming the photoelectric device according to the exemplary embodiment of
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More specifically, after applying an etch mask M1 on the insulating layer 450′, exposed portions through the etch mask M1 are removed. That is, the portions of the insulating layer 450′, the first conductive semiconductor layer 413, and the first intrinsic semiconductor layer 411 are removed (except for the portions protected by the etch mask M1) by using an etchant. At this point, the etchant may be HF, H3PO4, etc., having an etch characteristic with respect to the insulating layer 450′. As depicted in
Next, as depicted in
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As depicted in
More specifically, the etch mask M2 is formed on the second conductive semiconductor layer 423, and portions exposed through the etch mask M2 are removed. That is, the portions of the second conductive semiconductor layer 423 and the second intrinsic semiconductor layer 421 that are not protected by the etch mask M2 are removed by applying an etchant. For example, the etchant may be one selected from the group consisting of HNO3, HF, CH3COOH, DI water, and a mixture of these materials.
When the etching is completed, as depicted in
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According to embodiments of the present invention, there is provided a photoelectric device having a rear surface contact structure in which an electrode structure on a light receiving surface is removed to reduce or minimize optical loss. In addition, in a photoelectric device according to embodiments of the present invention, a manufacturing process may be simplified and recombination loss of optical carriers generated in a semiconductor substrate may be reduced.
While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims, and equivalents thereof.
Number | Date | Country | Kind |
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10-2012-0084986 | Aug 2012 | KR | national |