Patent Application
20120305059
1. Field of the Invention
Embodiments of the invention generally relate to optoelectronic semiconductor devices such as photovoltaic devices including solar cells, and methods for fabricating such optoelectronic devices.
2. Description of the Related Art
As fossil fuels are being depleted at ever-increasing rates, the need for alternative energy sources is becoming more and more apparent. Energy derived from wind, from the sun, and from flowing water offer renewable, environment-friendly alternatives to fossil fuels, such as coal, oil, and natural gas. Being readily available almost anywhere on Earth, solar energy may someday be a viable alternative.
To harness energy from the sun, the junction of a solar cell absorbs photons to produce electron-hole pairs, which are separated by the internal electric field of the junction to generate a voltage, thereby converting light energy to electric energy. The generated voltage can be increased by connecting solar cells in series, and the current may be increased by connecting solar cells in parallel. Solar cells may be grouped together on solar panels. An inverter may be coupled to several solar panels to convert DC power to AC power.
Nevertheless, the currently high cost of producing solar cells relative to the low efficiency levels of contemporary devices is preventing solar cells from becoming a mainstream energy source and limiting the applications to which solar cells may be suited. During conventional fabrication processes for photovoltaic devices, metallic contacts are often deposited with a vapor deposition process, and usually heated to temperatures of over 300° C. during thermal anneal processes. These high temperature processes are generally expensive due to the excessive consumption of time and energy. Also, the high temperature processes often damage sensitive materials contained within the photovoltaic device.
Accordingly, there is a need for optoelectronic devices with increased efficiency and methods for fabricating such optoelectronic devices at reduced costs when compared to conventional solar cells.
Embodiments of the invention generally relate to optoelectronic semiconductor devices including photovoltaic cells and the fabrication processes for forming such devices.
In one embodiment, an optoelectronic semiconductor device includes an absorber layer made of gallium arsenide (GaAs) and having only one type of doping. An emitter layer is located closer than the absorber layer to the back side of the device, the emitter layer made of a different material than the absorber layer and having a higher bandgap than the absorber layer. A heterojunction is formed between the emitter layer and the absorber layer, and a p-n junction is formed between the emitter layer and the absorber layer at a location offset from the heterojunction. The p-n junction causes a voltage to be generated in the device in response to the device being exposed to light at the front side of the device. The device also includes an n-metal contact disposed on the front side of the device and a p-metal contact disposed on the back side of the device. The front side is disposed over the back side. The p-metal contact has reflectivity such that light trapping, leading to enhanced photon recycling is enabled such that the open circuit voltage, and the operating voltage, of the device are enhanced.
So that the manner in which the above recited features of the invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
Embodiments of the invention generally relate to optoelectronic semiconductor devices and processes including photovoltaic devices and processes, and more specifically relate to photovoltaic cells and the fabrication processes for forming such photovoltaic cells and metallic contacts. Some of the fabrication processes include epitaxially growing thin films of gallium arsenide materials which are further processed by an epitaxial lift off (ELO) process. Some embodiments of photovoltaic cells described herein provide a gallium arsenide based cell containing an n-type film stack disposed over a p-type film stack, such that the n-type film stack is facing the front or sun side while the p-type film stack is on the back side of the cell. In one embodiment, the photovoltaic cell is a two-sided photovoltaic cell and has an n-metal contact disposed on the front side while a p-metal contact is disposed on the back side of the cell. In another embodiment, the photovoltaic cell is a single-sided photovoltaic cell and has the n-metal and the p-metal contacts disposed on the back side of the cell. Embodiments of an optoelectronic device include an absorber layer and an emitter layer, the emitter layer being of an opposite type to the absorber layer. The embodiments also include a heterojunction formed between emitter and absorber layers, and a p-n junction between the emitter layer and the absorber layer and at a location offset from the heterojunction, as described in greater detail below. Described innovations may allow for greater efficiency and flexibility in photovoltaic devices when compared to conventional solar cells.
Some embodiments of the invention provide processes for epitaxially growing Group III-V materials at high growth rates of greater than 5 μm/hr, such as about 10 μm/hr or greater, about 20 μm/hr or greater, about 30 μm/hr or greater, such as about 60 μm/hr or greater including about 100 μm/hr or greater or about 120 μm/hr or greater. The Group III-V materials are thin films of epitaxially grown layers which contain gallium arsenide, gallium aluminum arsenide, gallium aluminum indium phosphide, gallium aluminum phosphide, or combinations thereof.
In another embodiment described herein, the photovoltaic unit 90 may be exposed to a wet etch solution in order to etch the sacrificial layer 104 and to separate the gallium arsenide based cell 140 from the growth wafer 101 during an epitaxial lift off (ELO) process. The wet etch solution generally contains hydrofluoric acid, and may also contain various additives, buffers, and/or surfactants. The wet etch solution selectively etches the sacrificial layer 104 while preserving the gallium arsenide based cell 140 and the growth wafer 101. Once separated, the gallium arsenide based cell 140, as depicted in
The Group III-V materials are thin films of epitaxially grown layers which may contain gallium arsenide, gallium aluminum arsenide, among others. Some layers, such as the window layer may contain additional materials including gallium aluminum indium phosphide, aluminum indium phosphide, or combinations thereof. The epitaxially grown layers may be formed by growing Group III-V materials during a high growth rate vapor deposition process. The high growth rate deposition process allows for growth rates of greater than 5 μm/hr, such as about 10 μm/hr or greater, about 20 μm/hr or greater, about 30 μm/hr or greater, such as about 60 μm/hr or greater including about 100 μm/hr or greater or about 120 μm/hr or greater as compared to the conventional observed deposition rates of less than 5 μm/hr.
The process includes heating a wafer to a deposition temperature of about 550° C. or greater, within a processing system, exposing the wafer to a deposition gas containing a chemical precursor, such as gallium precursor gas and arsine for a gallium arsenide deposition process, and depositing a layer containing gallium arsenide on the wafer. The high growth rate deposition process may be utilized to deposit a variety of materials, including gallium arsenide, aluminum gallium arsenide, aluminum gallium phosphide, aluminum gallium indium phosphide, aluminum indium phosphide, indium gallium phosphide, aluminum arsenide, alloys thereof, doped variants thereof, or combinations thereof. In some embodiments of the deposition process, the deposition temperature may be within a range from about 550° C. to about 900° C. In other examples, the deposition temperature may be within a range from about 650° C. to about 850° C. In other examples, the deposition temperature may be within a range from about 750° C. to about 850° C. In other examples, the deposition temperature may be within a range from about 770° C. to about 830° C.
In one embodiment, a deposition gas may be formed by combining or mixing two, three, or more chemical precursors within a gas manifold prior to entering or passing through the showerhead. In another embodiment, the deposition gas may be formed by combining or mixing two, three, or more chemical precursors within a reaction zone after passing through the showerhead. The deposition gas may also contain one, two or more carrier gases, which may also be combined or mixed with the precursor gases prior to or subsequent to passing through the showerhead.
The deposition gas may contain one or multiple chemical precursors of gallium, aluminum, indium, arsenic, phosphorus, or others. The deposition gas may contain a gallium precursor gas which is an alkyl gallium compound, such as trimethylgallium or triethylgallium. The deposition gas may further contain an aluminum precursor gas which is an alkyl aluminum compound, such as trimethylaluminum or triethylaluminum. The deposition gas may further contain an indium precursor gas which is an alkyl indium compound, such as trimethylindium.
In some embodiments, the deposition gas further contains a carrier gas. The carrier gas may contain hydrogen (H2), nitrogen (N2), a mixture of hydrogen and nitrogen, argon, helium, or combinations thereof. In many examples, the carrier gas contains hydrogen, nitrogen, or a mixture of hydrogen and nitrogen. Each of the deposition gases may be provided to the processing chamber at a flow rate from about 5 sccm (standard cubic centimeters per minute) to about 300 sccm. The carrier gases may be provided to the processing chamber at a flow rate from about 500 sccm to about 3,000 sccm.
In other embodiments, the deposition gas contains the arsine and the gallium precursor gas at an arsine/gallium precursor ratio of about 3 or greater, or may be about 4 or greater, or may be about 5 or greater, or may be about 6 or greater, or may be about 7 or greater. In some examples, the arsine/gallium precursor ratio may be within a range from about 5 to about 10. In other embodiments, the Group III-V materials may be formed or grown from a deposition gas containing a ratio of Group V precursor to Group III precursor of about 30:1, or 40:1, or 50:1, or 60:1, or greater. In some examples, the deposition gas has a phosphine/Group III precursor of about 50:1.
The processing system may have an internal pressure within a range from about 20 Torr to about 1,000 Torr. In some embodiments, the internal pressure may be ambient or greater than ambient, such as within a range from about 760 Torr to about 1,000 Torr. In some examples, the internal pressure may be within a range from about 800 Torr to about 1,000 Torr. In other examples, the internal pressure is within a range from about 780 Torr to about 900 Torr, such as from about 800 Torr to about 850 Torr. In other embodiments, the internal pressure may be ambient or less than ambient, such as within a range from about 20 Torr to about 760 Torr, preferably, from about 50 Torr to about 450 Torr, and more preferably, from about 100 Torr to about 250 Torr.
The deposition processes for depositing or forming Group III-V materials, as described herein, may be conducted in a single wafer deposition chamber, a multi-wafer deposition chamber, a stationary deposition chamber, or a continuous feed deposition chamber. One continuous feed deposition chamber that may be utilized for growing, depositing, or otherwise forming Group III-V materials is described in the commonly assigned U.S. Ser. Nos. 12/475,131 and 12/475,169, both filed on May 29, 2009, which are herein incorporated by reference.
In one embodiment, one or more buffer layers 102 may be formed on the growth wafer 101 in order to start forming the photovoltaic unit 90. The growth wafer 101 may contain an n-type or semi-insulating material, and may contain the same or similar material as the one or more subsequently deposited buffer layers. For example, the growth wafer 101 may contain gallium arsenide, or n-doped gallium arsenide, when creating a gallium arsenide, or n-doped gallium arsenide, buffer layer. The p-dopants may be selected from carbon, magnesium, zinc, or combinations thereof while the n-dopants may be selected from silicon, selenium, tellurium, or combinations thereof. In some embodiments, p-type dopant precursors may include carbon tetrabromide (CBr4) for a carbon dopant, bis(cyclopentadienyl)magnesium (Cp2Mg) for a magnesium dopant, and dialkyl zinc compounds including dimethylzinc or diethylzinc for a zinc dopant. In other embodiments, n-type dopant precursors may include silane (SiH4) or disilane (Si2H6) for a silicon dopant, hydrogen selenide (H2Se) for a selenium dopant, and dialkyl tellurium compounds including dimethyltellurium, diethyltellurium, and diisopropyltellurium for a tellurium dopant.
The buffer layer 102 or layers may provide an intermediary between the growth wafer 101 and the semiconductor layers of the final photovoltaic unit that can accommodate their different crystallographic structures as the various epitaxial layers are formed. The one or more buffer layers 102 may be deposited to a thickness from about 100 nm to about 600 nm, such as a thickness of about 500 nm, for example. Each of the one or more buffer layers 102 may contain a Group III-V compound semiconductor, such as gallium arsenide, depending on the desired composition of the final photovoltaic unit. The buffer layer 102 may also be doped, such as an n-doped material, for example n-doped gallium arsenide.
A sacrificial layer 104 may be deposited on the buffer layer 102. The sacrificial layer 104 may contain a suitable material, such as aluminum arsenide or an aluminum arsenide alloy, and may be deposited to have a thickness within a range from about 3 nm to about 50 nm, such as from about 5 nm to about 20 nm, for example, about 20 nm. The sacrificial layer 104 may also be doped, such as an n-doped material, for example n-doped aluminum arsenide. The sacrificial layer 104, also known as the release layer, is etched and removed while separating the gallium arsenide based cell 140 from the growth wafer 101 during the ELO process. Prior to being etched, the sacrificial layer 104 is also utilized to form the lattice structure for the subsequently and epitaxially grown layers contained within the gallium arsenide based cell 140, such as the n-type contact layer 105.
The gallium arsenide based cell 140 includes an n-type film stack 120 containing n-doped gallium arsenide materials disposed over a p-type film stack 130 which contain p-doped gallium arsenide materials. Each of the n-type film stack 120 and the p-type film stack 130 independently contains multiple layers of varying compositions of materials including gallium arsenide materials. In one embodiment, the n-type film stack 120 includes an n-type contact layer 105, an n-type front window 106, an n-type absorber layer 108 formed adjacent the n-type front window 106, and optionally, an intermediate layer 114. The p-type film stack 130 includes a p-type emitter layer 110 and a p-type contact layer 112 formed on the p-type emitter layer 110.
During a fabrication process, as described in one embodiment, the n-type contact layer 105, or interface layer, may be deposited on the sacrificial layer 104. The n-type contact layer 105 contains Group III-V materials, such as gallium arsenide, depending on the desired composition of the final photovoltaic unit. The n-type contact layer 105 is n-doped, and for some embodiments, the doping concentration may be within a range greater than about 1×1018 atoms/cm3, such as greater than to 6×1018 atoms/cm3, for example, from greater than about 1×1018 atoms/cm3 to about 1×1019 atoms/cm3. The n-type contact layer 105 may be formed at a thickness within a range from about 10 nm to about 1,000 nm or from about 10 nm to about 100 nm, such as from about 25 nm to about 75 nm, for example, about 50 nm. The n-type contact layer 105 may be formed at this stage, such as a part of the gallium arsenide based cell 140 prior to the ELO process. Alternatively, in another embodiment, the n-type contact layer 105 may be formed at a later stage subsequent to the ELO process. One advantage to forming the n-type contact layer 105 as a part of the gallium arsenide based cell 140 prior to the ELO process is that the n-type contact layer 105 helps to protect the n-type front window 106 from undesired damage or material contamination during subsequent processing steps, such as while etching the sacrificial layer 104 during the ELO process.
An n-type front window 106, also known as a passivation layer, may be formed on the sacrificial layer 104, or if present, on the optional contact layer 105. The n-type front window 106 may contain a Group III-V material such as aluminum gallium, aluminum gallium arsenide, alloys thereof, or combinations thereof. The n-type front window 106 material may be n-doped, and for some embodiments, the doping concentration may be within a range greater than about 1×1018 atoms/cm3, such as greater than to 3×1018 atoms/cm3, for example, from greater than about 1×1018 atoms/cm3 to about 1×1019 atoms/cm3. The n-type front window 106 material may be non-doped. The aluminum gallium arsenide may have the formula of molar ratios, the AlxGa1-xAs, for example, a molar ratio of Al0.3Ga0.7As. The n-type front window 106 may be deposited to have a thickness within a range from about 5 nm to about 75 nm, for example, about 30 nm or about 40 nm. The n-type front window 106 may be transparent to allow photons to pass through the n-type front window 106 on the front side of the gallium arsenide based cell 140 to other underlying layers.
Alternatively, the n-type front window 106 may contain a material such as aluminum indium phosphide, aluminum gallium indium phosphide, alloys thereof, derivatives thereof, or combinations thereof. These aluminum (gallium) indium phosphide compounds provide for a large band gap, such as about 2.2 eV, as well as high collector efficiency at shorter wavelengths when utilized within the n-type front window 106.
An absorber layer 108 may be formed on the front window 106. The absorber layer 108 may contain a Group III-V compound semiconductor, such as gallium arsenide. The absorber layer 108 may be monocrystalline. The absorber layer 108 may, for example, have only one type of doping, for example, n-doping, and for some embodiments, the doping concentration of the n-type absorber layer 108 may be within a range from about 1×1016 atoms/cm3 to about 1×1019 atoms/cm3, for example, about 1×1017 atoms/cm3. The thickness of the n-type absorber layer 108 may be within a range from about 300 nm to about 3,500 nm, such as from about 1,000 nm to about 3,000 nm (about 1.0 μm to about 3.0 μm), for example, about 2,200 nm. Increasing the doping in layer 108 will increase the radiative recombination rate. That in turn, leads to a higher frequency of photon recycling levels. Increasing the photon recycling levels, will potentially improve light coupling of the device.
As illustrated in
In some embodiments, the contact of the n-type absorber layer 108 with the p-type emitter layer 110 creates a p-n interface layer for absorbing photons. In embodiments of the invention in which the n-type absorber layer 108 contains one material (such as gallium arsenide) and the p-type emitter layer 110 contains a different material having a different bandgap than the material of the absorber layer 108 (such as aluminum gallium arsenide), the p-n interface layer is a heterojunction. Heterojunctions, as described in embodiments herein, are observed to have reduced dark current, and improved voltage production, as compared to homojunctions of the conventional photovoltaic materials. In some embodiments described herein, the material of the p-type emitter layer 110 has a higher bandgap than the material of the n-type absorber layer 108.
Accordingly in an embodiment, the process of photon recycling within the device is utilized to enhance its operation. Photon recycling is the process by which a photon absorbed, or generated, within the semiconductor layers of an optoelectronic device, such as a photovoltaic device, can generate an electron-hole pair which then radiatively recombines to create another photon. This photon can then create another electron-hole pair, and so on. Under open-circuit conditions, this process can repeat itself many times—this is photon recycling. For a PV device this can create a much higher probability that photo-generated carriers are collected, increasing the effective lifetime in the device. Similarly, for a device such as an LED this can greatly increase the probability that generated photons escape the semiconductor.
Photon recycling requires a device with very low carrier losses to non-radiative recombination processes in the semiconductor, and very low photon losses to processes other than escape out through the front of the device, and carrier generation. As such, it is associated with highly-efficient devices in general, particularly devices that have very low dark-current. For a PV device under open-circuit conditions, the carrier density within the device can be greatly increased due to the recycling as described above, which in turn will lead to a greatly increased Voc. Indeed, in terms of an electrical output, a high Voc is the primary signature of photon recycling. Photon recycling can also boost other performance metrics of the device, such as the maximum-power operating voltage Vmax, the associated current density Jmax, the short-circuit current density Jsc, as well as the overall device efficiency.
In embodiments using the epitaxial lift off (ELO) process, Vocs in excess of 1.1V, using high-quality epitaxial material including an approximately 2 micron-thick GaAs absorber, and pn heterojunction (GaAs/AlGaAs), and either silver or gold reflectors at the rear side of the device have been observed as shown in
When light is absorbed near the p-n interface layer to produce electron-hole pairs, the built-in electric field caused by the p-n junction may force the holes to the p-doped side and the electrons to the n-doped side. This displacement of free charges results in a voltage difference between the n-type absorber layer 108 and the p-type emitter layer 110 such that electron current may flow when a load is connected across terminals coupled to these layers.
In some embodiments described herein, the p-type emitter layer 110 is closer than the n-type absorber layer 108 to the back side of the cell 140, i.e., the n-type absorber layer is closer to the front side of the cell 140. This arrangement of emitter layer under absorber layer can in some embodiments provide single carrier transport in the solar cell, in which the emitter and p-n junction are provided closer to the back side of the cell such that the absorber layer absorbs most of the incident photons on the device and generates most of the carriers, such that substantially a single type of carrier is generated. For example, with the emitter layer 110 being made of a higher bandgap material than the absorber layer, the emitter layer is more suited to absorb blue-spectrum photons which do not penetrate as far into the device and thus not as many of these photons reach the emitter layer that is further from the top side than the absorber layer 108.
Fabricating a thinner base/absorber layer according to some embodiments described herein allows use of an n-doped base/absorber layer. The higher mobility of electrons in an n-doped layer compared to the mobility of holes in a p-doped layer can lead to lower doping density in the n-type absorber layer 108 as described by embodiments herein. Other embodiments may use a p-doped base/absorber layer and an n-doped back/emitter layer. For example, the base/absorber layer may be p-doped in embodiments having a thicker absorber layer due to the diffusion length of the carriers.
In other embodiments, as shown in
This embodiment of the cell 140 provides a structure that allows the p-n junction that generates voltage for the cell to be offset from the heterojunction provided by materials having different bandgaps. For example, the p-n junction 152 is at the interface between the n-type and p-type materials of the emitter layer 110 and the intermediate layer 114. Thus, in one described embodiment, the p-n junction is provided at least partially within the higher-bandgap material of which the emitter layer 110 and intermediate layer 114 are composed (e.g., AlGaAs), and the heterojunction 154 is located at the interface between the intermediate layer 114 and the absorber layer 108 (e.g., the interface between GaAs and AlGaAs). This offset provides some advantages over a coincident p-n junction and heterojunction. For example, the offset p-n junction provided between the AlGaAs layers can reduce barrier effects of an interface between the AlGaAs and GaAs layers. In some embodiments, a majority of the absorber layer 108 is outside of a depletion region formed by the p-n junction.
In some embodiments, the heterojunction 154 is located within two depletion lengths of the p-n junction 152. For example, a depletion region may be about 1000 Å (100 nm) wide in some embodiments. The depletion region typically still has a depletion effect past this region, within about two depletion region widths (depletion lengths) of the p-n junction. A heterojunction located further than this distance from the p-n junction may not allow the depletion effect to span the heterojunction interface and a barrier may thus exist.
As shown in
The embodiment of 160 includes a p-n junction 162 formed between the n-doped layer 117 and the p-doped layer 110. The p-n junction 162 is offset from the heterojunction 164 provided between two materials having different bandgaps. In the example of embodiment 160, the materials are GaAs in absorber layer 108 and AlGaAs in the graded layer 115. Although the heterojunction 164 is shown in
The graded layer 115 may be a graded layer that includes a material gradation ranging from the absorber layer to the back window 117, where the gradation ranges from the material of the absorber layer at the graded layer side closer to the absorber layer, to the material of the back window 117 at the side closer to the back window. Thus, using the example materials described above, the gradation material may start as gallium arsenide adjacent the n-type absorber layer 108, and have a gradation in the direction of the back window of an increasing amount of aluminum and a decreasing amount of GaAs, such that the gradation ends adjacent the n-type back window 117 with about the same aluminum gallium arsenide material (molar ratios) as the material of back window 117. In many examples, the aluminum gallium arsenide at the window end of the gradation may have the formula of molar ratios, AlxGa1-xAs; for example, a molar ratio of Al0.3Ga0.7As can be used. The gradation of the graded layer 115 may be parabolic, exponential or linear in gradation. The n-type back window 117 may also contain aluminum gallium arsenide and may have the formula of molar ratios, the AlxGa1-xAs, for example, a molar ratio of Al0.3Ga0.7As. In other embodiments, the intermediate layer 114 contains only the graded layer 115, or the intermediate layer 114 contains only the non-graded back window 117 (as shown in
Optionally, a p-type contact layer 112 may be formed on the p-type emitter layer 110. The p-type contact layer 112 may contain a Group III-V compound semiconductor, such as gallium arsenide. The p-type contact layer 112 is generally monocrystalline and p-doped, and for some embodiments, the doping concentration of the p-type contact layer 112 may be greater than 1×1018 atoms/cm3, such as from about 6×1018 atoms/cm3 to about 2×1019 atoms/cm3, for example, about 1×1019 atoms/cm3. The p-type emitter layer 110 may have a thickness within a range from about 10 nm to about 100 nm, for example, about 50 nm.
Once the p-type emitter layer 110 has been formed, cavities or recesses (not shown) may be formed in the p-type emitter layer 110 (or optional p-type contact layer 112) deep enough to reach the underlying base n-type absorber layer 108. Such recesses may be formed by applying a mask to the p-type emitter layer 110 (or optional p-type contact layer 112) using photolithography, for example, and removing the material in the p-type emitter layer 110 (and optional p-type contact layer 112) not covered by the mask using a technique, such as wet or dry etching. In this manner, the n-type absorber layer 108 may be accessed via the back side of the gallium arsenide based cell 140.
In other embodiments, the opposite type of doping can be used in the layers discussed above, and/or other materials can be used that can provide the described heterojunction and p-n junction. Furthermore, in other embodiments the layers can be deposited or formed in a different order than the order described above.
A photovoltaic unit created in this manner has a significantly thin absorber layer, for example, less than 500 nm) compared to conventional solar units, which may be several micrometers thick. The thickness of the absorber layer is proportional to dark current levels in the photovoltaic unit (e.g., the thinner the absorber layer, the lower the dark current). Dark current is the small electric current that flows through the photovoltaic unit or other similar photosensitive device, for example, a photodiode, even when no photons are entering the device. This background current may be present as the result of thermionic emission or other effects. Because the open circuit voltage (Voc) increases as the dark current is decreased in a photosensitive semiconductor device, a thinner absorber layer may most likely lead to a greater Voc for a given light intensity and, thus, increased efficiency. As long as the absorber layer is able to trap light, the efficiency increases as the thickness of the absorber layer is decreased.
The thinness of the absorber layer may not only be limited by the capabilities of thin film technology and ELO. For example, efficiency increases with the thinness of the absorber layer, but the absorber layer should be thick enough to carry current. However, higher doping levels may allow current to flow, even in very thin absorber layers. Therefore, increased doping may be utilized to fabricate very thin absorber layers with even greater efficiency. Conventional photovoltaic devices may suffer from volume recombination effects, and therefore, such conventional devices do not employ high doping in the absorber layer. The sheet resistance of the absorber layer may also be taken into consideration when determining the appropriate thickness.
Photovoltaic devices which contain a thin absorber layer as described herein are usually more flexible than conventional solar cells having a thickness of several micrometers. Also, the thin absorber layers as described herein provide increased efficiency over conventional solar cells. Therefore, photovoltaic units according to embodiments of the invention may be appropriate for a greater number of applications than conventional solar cells.
In one embodiment, an n-metal contact layer 208 is deposited on the n-type contact layer 105 and subsequently, recesses are formed through the n-metal contact layer 208 and the n-type contact layer 105 to expose the n-type front window 106 on the front side of the photovoltaic cell 200. In an alternative embodiment, recesses may be initially formed in the n-type contact layer 105 to expose the n-type front window 106 on the front side of the photovoltaic cell 200. Thereafter, the n-metal contact layer 208 may be formed on the remaining portions of the n-type contact layer 105 while leaving exposed the n-type front window 106. The n-type contact layer 105 contains n-doped gallium arsenide materials which may have a dopant concentration of greater than about 3×1018 atoms/cm3, such as within a range from greater than about 6×1018 atoms/cm3 to about 1×1019 atoms/cm3.
An anti-reflective coating (ARC) layer 202 may be disposed over the exposed n-type front window 106, as well as the n-type contact layer 105 and the n-metal contact layer 208, in accordance with an embodiment of the invention. The ARC layer 202 contains a material that allows light to pass through while preventing light reflection from the surface of the ARC layer 202. For example, the ARC layer 202 may contain magnesium fluoride, zinc sulfide, titanium oxide, silicon oxide, derivatives thereof, or combination thereof. The ARC layer 202 may be applied to the n-type front window 106 by a technique, such as sputtering. The ARC layer 202 may have a thickness within a range from about 25 nm to about 200 nm, such as from about 50 nm to about 150 nm.
For some embodiments, the n-type front window 106, the p-type emitter layer 110, and/or the p-type contact layer 112 may be roughened or textured before applying the ARC layer 202. Each of the n-type front window 106, the p-type emitter layer 110, and/or the p-type contact layer 112 may be roughened by an etching process, such as a wet etching process or a dry etching process. Texturing may be achieved by applying small particles, such as polystyrene spheres, to the surface of the n-type front window 106 before applying the ARC layer 202. By roughening or texturing the n-type front window 106, the p-type emitter layer 110, and/or the p-type contact layer 112, different angles are provided at the interface between the ARC layer 202 and the n-type front window 106, which may have different indices of refraction. In this manner, more of the incident photons may be transmitted into the n-type front window 106 rather than reflected from the interface between the ARC layer 202 and the n-type front window 106 because some angles of incidence for photons are too high according to Snell's Law. Thus, roughening or texturing the n-type front window 106, the p-type emitter layer 110, and/or the p-type contact layer 112 may provide increased trapping of light.
In some embodiments, the n-type front window 106 may contain multiple window layers. For these embodiments, the outermost window layer (e.g., the window layer closest to the front side of the photovoltaic cell 200) may be roughened or textured as described above before the ARC layer 202 is applied, as illustrated in
The p-metal contact layer 204 and/or the n-metal contact layer 208 each contain contact materials which are electrically conductive materials, such as metals or metal alloys. Preferably, the contact materials contained within the p-metal contact layer 204 and/or the n-metal contact layer 208 do not diffuse through other layers, such as a semiconductor layer, during any of the process steps utilized during the fabrication of the photovoltaic cell 200. Usually, each of the p-metal contact layer 204 and the n-metal contact layer 208 contains multiple layers of the same or different contact materials. The contact materials preferably have specific contact resistance of 1×10−3 Ω-cm2 or less. Preferred contact materials also have Schottky barrier heights (φbn) of about 0.8 eV or greater at carrier concentrations of about 1×1018 atoms/cm3. Suitable contact materials may include gold, copper, silver, aluminum, palladium, platinum, titanium, zirconium, nickel, chromium, tungsten, tantalum, ruthenium, zinc, germanium, palladium germanium alloy, derivatives thereof, alloys thereof, or combinations thereof.
In some embodiments described herein, the p-metal contact layer 204 and/or the n-metal contact layer 208 may be fabricated on the photovoltaic cell 200 by a method, such as vacuum-evaporation through a photoresist, photolithography, screen printing, or merely depositing on the exposed surface of the photovoltaic cell 200 that have been partially covered with a resist mask, a wax, or another protective material.
Optionally, a metal protective layer, or metal adhesion layer, may be deposited on the p-metal contact layer 204. The metal protective layer may contain a material including nickel, chromium, titanium, alloys thereof, or combinations thereof. The metal protective layer preferably exhibits good adhesion to p-doped gallium arsenide. In one example embodiment, the metal protective layer may be deposited to a thickness within a range from about 5 Å to about 20 Å and have a reflectance of about 80% or greater. Preferably, the material of the metal protective layer and deposition thickness are deposited to minimize any interference with the reflectiveness of the p-metal contact layer 204. The metal protective layer may be deposited by an electron beam deposition process or a PVD process, also known as a sputtering process.
Specifically, a structure may be in an embodiment, a thin (100 nm-5000 nm, or, preferably, with an absorber layer that is about 1000 nm to about 3000 nm thick) semiconductor material with a highly reflective metal protective layer 204. The semiconductor layer should have high internal fluorescence yield, and as such may typically be a single crystal, and may typically be an III-V material, such as GaAs, or a stack of materials including GaAs and possibly other III-V materials.
The metal protective layer 204 may also provide electrical contact to the device, and may for example be a highly reflective metal, such as gold, silver, copper, aluminum, or an alloy of one or more of these elements, with each other and/or with other elements, such as palladium for example. Alternatively the metal protective layer 204 may be a stack of more than one metallic layers, one of which may be highly reflective and contain gold, silver, copper, aluminum, or an alloy of one or more of these elements, with each other and/or with other elements. The other layers in the stack need not be highly reflective, so long as the thickness of any layers between the semiconductor device and the reflective metal layer is comparable in thickness to, or thinner than, the skin depth of light at the bandgap wavelength of the semiconductor material. A Ni layer about 1 nm thick, between the semiconductor device and a thicker gold layer, is one example.
Alternatively, the metal protective layer 204 may involve a dielectric material between the metal layer(s) and the semiconductor device. This can increase the reflectivity of the metal protective layer 204. The dielectric layer may contain at least one dielectric material such as aluminum oxide, titanium oxide, tin oxide, indium tin oxide, fluorine tin oxide, zinc oxide, aluminum zinc oxide, zinc sulfide, silicon oxide, silicon oxynitride, silicon nitride, derivatives thereof, or combinations thereof. The dielectric layer may have a thickness within a range from about 10 nm to about 200 nm, preferably, from about 30 nm to about 100 nm.
Alternatively, the metal protective layer 204 may involve an additional semiconductor, of lower refractive index than the device epi stack materials, between the metal layer(s) and the semiconductor device. This can increase the reflectivity of the metal protective layer 204. This intermediate layer may contain at least one of zinc sulfide, arsenic trisulfide, derivatives thereof, or combinations thereof. This intermediate layer may have a thickness within a range from about 10 nm to about 200 nm.
This dielectric or semiconductor intermediate layer may be completely or substantially resistant to being etched when exposed to hydrofluoric acid during an ELO process. Possible examples include arsenic trisulfide, zinc sulfide, silicon nitride, derivatives thereof, or combinations thereof.
The dielectric or semiconductor intermediate layer may be conductive or non-conductive of electrical current. The dielectric or semiconductor intermediate layer may be patterned with through-holes to allow the metallic layer to contact the semiconductor layer directly in some areas, while the majority of the area has the intermediate semiconductor or dielectric layer intact between the metal and the device layers to improve the reflectivity.
Reflectivity at the device absorber layer bandgap wavelength (˜871 nm for GaAs) should be made as high as possible, preferably >50%, at the device/metal protective layer 204 interface. This can be achieved with metal and/or dielectric combinations applied to the metal protective layer 204 of the device, as described above, but can also involve engineering of the device layer structure itself. For example, a back AlGaAs or other wide bandgap semiconductor layer may exist at the back side of the device, behind which may exist a GaAs contact layer. This GaAs contact layer may be thinned, or alloyed with some amount of Al content, or may be omitted altogether, in order to improve the reflectivity at the back of the device.
As before described open-circuit voltages (Vocs) above 1.1V, were observed under 1 sun illumination in a single-junction, thin-film photovoltaic (PV) device with a GaAs absorber. This may be attributable to light trapping, leading to enhanced photon recycling.
Some example embodiments of p-metal contact layer 204, n-metal contact layer 208, and other contact, adhesion, and reflector layers suitable for use with contact layers of the cell 200 are described in copending U.S. patent application Ser. No. ______, entitled, “Metallic Contacts for Photovoltaic Devices and Low-Temperature Fabrication Processes Thereof,” filed on an even date herewith, and which is incorporated herein by reference. Other types, structures, and materials of metal contact layers can also be used with cell 200.
In some embodiments, the photovoltaic cell 300 may be formed from the gallium arsenide based cell 140 of
In one embodiment, the p-metal contact layer 306 is formed on a portion of the exposed the p-type contact layer 112 and the n-metal alloy contact 310 is formed on a portion of the exposed the n-type absorber layer 108. Thereafter, the insulation layer 216 may be deposited over the surface of the photovoltaic cell 300, such as to cover all exposed surfaces including the p-metal contact layer 306 and the n-metal alloy contact 310. Subsequently, the exposed surfaces of the p-metal contact layer 306 and the n-metal alloy contact 310 are revealed by etching pattern holes into the insulation layer 216 by a lithography process. In some embodiments, the p-metal contact layer 306 and the n-metal alloy contact 310 are formed prior to separating the gallium arsenide based cell 140 from the growth wafer 101 during the ELO process while the insulation layer 216 is formed subsequent to the ELO process. The p-metal contact layer 304 may be formed on the p-metal contact layer 306 and a portion of the insulation layer 216 while the n-metal contact layer 308 may be formed on the n-metal alloy contact 310 and other portions of the insulation layer 216 to form the photovoltaic cell 300, as depicted in
In an alternative embodiment, the p-metal contact 302 and the n-metal contact 312 may be fabricated, in whole or in part, and subsequently, the insulation layer 216 may be formed over and on the sidewalls of the recesses between and around the p-metal contact 302 and the n-metal contact 312. In another alternative embodiment, the insulation layer 216, in whole or in part, may be formed on the photovoltaic cell 300 prior to forming the p-metal contact 302 and the n-metal contact 312.
Despite all the contacts, such as the p-metal contact 302 and the n-metal contact 312, being on the back side of the photovoltaic cell 300 to reduce solar shadows, dark current and its stability with time and temperature may still be concerns when designing an efficient photovoltaic device, such as the photovoltaic cell 300. Therefore, for some embodiments, an insulation layer 216 may be deposited or otherwise formed on the back side of the photovoltaic cell 300. The insulation layer 216 contains an electrically insulating material or grout which helps to reduce the dark current within the photovoltaic cell 300.
The insulation layer 216 may contain an electrically insulating material or grout, such as silicon oxides, silicon dioxide, silicon oxynitride, silicon nitride, polysiloxane or silicone, sol-gel materials, titanium oxide, tantalum oxide, zinc sulfide, derivatives thereof, or combinations thereof. The insulation layer 216 may be formed by a passivation method, such as by a sputtering process, an evaporation process, a spin-coating process, or a CVD process.
In another embodiment, the insulation layer 216 eliminates or substantially reduces electrical shorts from occurring between the p-metal contact 302 and the n-metal contact 312. The insulation layer 216 contains an electrically insulating grout and/or other electrically insulating material that has an electrical resistance of at least 0.5 MΩ (million ohms) or greater, such as within a range from about 1 MΩ to about 5 MΩ, or greater. Exemplary grouts or other electrically insulating materials may contain a polymeric material, such as ethylene vinyl acetate (EVA), polyimide, polyurethane, derivatives thereof, or combinations thereof. In one example, the electrically insulating grout contains a photosensitive polyimide coating. In another example, the electrically insulating grout contains a thermal set polymeric material.
In many embodiments, the n-metal alloy contact 310 may be formed by a low temperature process, which includes low temperature deposition processes followed by a low temperature, thermal anneal process. Suitable contact materials deposited within the n-metal alloy contact 310 by low temperature deposition processes may include palladium, germanium, palladium germanium alloy, titanium, gold, nickel, silver, copper, platinum, alloys thereof, or combinations thereof, among others.
In another embodiment, the n-metal alloy contact 310 may contain multiple layers of conductive materials including a palladium germanium alloy. The n-metal alloy contact 310 is disposed between the n-type absorber layer 108 and the n-metal contact layer 308 for providing a strong ohmic contact therebetween. The palladium germanium alloy within the n-metal alloy contact 310 allows a high conductivity of the electric potential from the gallium arsenide materials within the n-type absorber layer 108, across n-metal alloy contact 310, and to the n-metal contact layer 308. The n-metal alloy contact 310 can also contain a metallic capping layer which can be provided, for example, on the palladium germanium alloy layer. In some embodiments, the capping layer can include an adhesion layer and a high conductivity layer. For example, the adhesion layer can allow the conductivity layer to adhere to the alloy layer. In some examples, the adhesion layer may contain titanium, tin, zinc, alloys thereof, or combinations thereof and the high conductivity layer may contain gold, silver, nickel, copper, aluminum, alloys thereof, or combinations thereof, or a stack of multiple different metal layers and/or alloy layers. In one example, the n-metal alloy contact 310 contains a high conductivity layer containing gold disposed on an adhesion layer containing titanium, which is disposed on a palladium germanium alloy.
Similar fabrication methods and embodiments as described above for the p-metal contact layer 204 and/or the n-metal contact layer 208 on cell 200 can be used for the p-metal contact layer 306 on photovoltaic cell 300. Some example embodiments of n-metal alloy contact 304, p-metal contact 302, n-metal contact 312, n-metal alloy contact 310, and other layers suitable for use with contact layers of the cell 300 are described in copending patent application Ser. No. ______, entitled, “Metallic Contacts for Photovoltaic Devices and Low-Temperature Fabrication Processes Thereof,” filed on an even date herewith, and which is incorporated herein by reference. Other types, structures, and materials of metal contact layers can also be used with cell 300.
While the foregoing is directed to embodiments of the inventions, other and further embodiments of the inventions may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
The present application claims the benefit of U.S. Provisional Application No. 61/493,936, filed on Jun. 6, 2011, entitled “PHOTON RECYCLING IN AN OPTOELECTRONIC DEVICE,” which is incorporated herein by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 61493936 | Jun 2011 | US |
