Patent Application
20200295654
The present invention relates generally to electrical circuits and devices, and particularly to DC voltage filtering.
When a variable power source supplies a load with DC voltage, the voltage across the load tends to fluctuate. The traditional way to suppress such fluctuations is to connect a large capacitor, typically an electrolytic capacitor or a supercapacitor, in parallel with the load. Such filtering capacitors are commonly encountered, for example, on the DC bus in photovoltaic systems, wind power generators, sub-modules of modular multilevel converters (MMC), electric vehicles, power factor compensators (PFC), uninterruptible power supplies, and power supplies for flicker-free LED lighting. Large capacitors of this sort, however, are bulky, expensive and have a short working life.
A number of alternative solutions have been proposed to suppress voltage fluctuations without a large filter capacitor. For example, PCT International Publication WO 2015/019344, whose disclosure is incorporated herein by reference, describes a virtual infinite capacitor (VIC)—a switched power circuit containing switches, an inductor, and two small capacitors, including a charge buffering capacitor. Within a designated normal operating range, the VIC emulates the behavior of very large capacitors by maintaining a constant voltage notwithstanding changes in the charge on the buffering capacitor. The VIC is thus able to emulate large capacitors using smaller, cheaper, and more reliable ceramic or film capacitors together with suitable electronic circuitry.
Embodiments of the present invention that are described hereinbelow provide improved circuits and methods for DC voltage filtering.
There is therefore provided, in accordance with an embodiment of the invention, apparatus for controlling DC voltage on a bus, which includes a switched power converter, including a pair of terminals for connection between the bus and a ground, a buffering capacitor, and switching circuitry coupled between the buffering capacitor and the terminals and configured to control a voltage between the terminals while a charge on the buffering capacitor varies over a predefined range in response to a current flowing through the terminals. A control circuit is coupled to monitor the voltage between the terminals, the current, and a voltage on the buffering capacitor, and is configured to adjust the voltage between the terminals by controlling the switching circuitry in response to changes in the monitored voltages and current so that the terminal voltage is maintained at a reference voltage value.
In the disclosed embodiments, the switched power circuit includes a filtering capacitor coupled between the terminals, and the switching circuitry includes diodes and switches, which are configured as a reversible buck converter circuit.
In some embodiments, the control circuit is configured to control the switching circuitry by applying a state machine model including a charging state, in which the current flowing through the terminals, after conversion by the power converter, charges the buffering capacitor, a normal operating state, in which the switching circuitry is controlled to charge and discharge the buffering capacitor while maintaining the voltage between the terminals at the reference voltage value, and a protection state, in which the switching circuitry is opened to prevent overcharging of the buffering capacitor. Typically, the state machine model includes a hysteresis in levels of the charge on the buffering capacitor that cause transitions between the states.
In some embodiments, the control circuit is configured to control the switching circuitry so as to maintain the charge on the buffering capacitor within the predefined range. In the disclosed embodiments, the control circuit is configured to adjust the reference voltage value responsively to changes in the buffer voltage so as to maintain the charge on the buffering capacitor within the predefined range. In one embodiment, the control circuit includes a voltage sensor and a low-pass filter, which couples the voltage sensor to measure the buffer voltage on the buffering capacitor while filtering out of the measured buffer voltage variations above a predefined cutoff frequency, and the control circuit is configured to adjust the reference voltage value responsively to the measured, filtered buffer voltage.
Additionally or alternatively, the control circuit is configured to adjust the reference voltage value by applying an asymmetric backlash function to the changes in the voltage on the buffering capacitor. In one embodiment, the control circuit is configured to modify a width of the asymmetric backlash function responsively to a swing range of the changes in the buffer voltage.
There is also provided, in accordance with an embodiment of the invention, a method for controlling DC voltage on a bus, which includes coupling a pair of terminals of a switched power converter between the bus and a ground. The switched power converter includes a buffering capacitor and switching circuitry coupled between the buffering capacitor and the terminals and configured to maintain a voltage between the terminals at a reference voltage value while a charge on the buffering capacitor varies over a predefined range in response to a current flowing through the terminals. The voltage between the terminals and the current flowing through the terminals are monitored, and the voltage between the terminals is adjusted by controlling the switching circuitry in response to changes in the monitored voltage and current so that the voltage is maintained at the reference voltage value.
The present invention will be more fully understood from the following detailed description of the embodiments thereof, taken together with the drawings in which:
The VICs described in the above-mentioned PCT International Publication WO 2015/019344 suffer from a lack of flexibility: The buffering circuit that is used in the VIC to absorb voltage variations must be integrated tightly with the host system as a built-in module, in order to ensure effective charge control. For this purpose, the source-side converter must generally be modified to allow the charge controller of the VIC access to the voltage regulator of the power source. This closely-coupled solution is ineffective for distributed systems, such as DC power grids, where devices are not in the same geographic location. It is generally unsuitable for use on the DC bus of an existing power electronic system in cases in which a user would like to add or install a VIC without tampering with the control circuits of the existing system.
Embodiments of the present invention, as described herein, add “plug-and-play” capability to the VIC, meaning that the VIC can be packaged and deployed in a wide range of systems as an independent module. The plug-and-play (PnP) VIC need have only two terminals, like a conventional capacitor, and need not “know” in advance the stabilized terminal voltage, i.e., the equilibrium voltage of the (unknown) DC bus to which it is to be connected. The reference voltage of the PnP VIC is adjusted automatically so that it will converge to the equilibrium voltage of the DC bus (i.e., the average DC bus voltage at which current supply and current demand of all the devices connected to the DC bus are equal). For this purpose, a control circuit monitors the charge on the buffering capacitor of the VIC, on the basis of the voltage on the buffering capacitor, and adjusts the reference voltage when the charge approaches either end of its normal operating range.
In one embodiment, the reference voltage Vr is generated based on the average value of the voltage on the buffering capacitor VS over a recent time interval, measured via a high-order low-pass filter (LPF). The characteristics of this LPF are chosen carefully to ensure sharp separation between the high frequency range in which ripple occurs and the low frequency range in which power variations occur on the DC bus.
In an alternative embodiment, the reference voltage Vr is derived from an asymmetric backlash, which is applied directly to the buffering capacitor voltage VS.
In both embodiments, the output impedance of the plug-and-play VIC behaves at both very low and very high frequencies of voltage variation as though the VIC was a small capacitor. In the intermediate range of frequencies, where ripple current is expected, however, for example between 50 Hz and 1000 Hz, the output impedance of the VIC is very small (and ideally zero), thus emulating a very large capacitor. When these criteria are satisfied, the VIC effectively eliminates voltage ripple on the DC bus to which it is connected. No further connection is required between the PnP VIC and the DC power supply, other than the pair of terminals of the PnP VIC that are connected to the DC bus.
In the pictured example, a DC power supply 24 receives AC domestic grid input and generates a desired DC voltage on a bus 26. Power supply 24 provides power factor correction (PFC), as is known in the art, and has a small output capacitance Co. A variety of loads 30 can be coupled between bus 26 and a ground 28, including (in this example) a fixed resistive load RL1, a switched resistive load RL2, and a nonlinear load represented as a current source id. Power supply 24 outputs a substantial ripple on bus 26 at the AC lines frequency and harmonics thereof, which is exacerbated by the effects of the nonlinear load. In systems that are known in the art, a large electrolytic capacitor could be coupled between bus 26 and ground 28 (either as a part of power supply 24 or as a separate unit) in order to filter the high-frequency ripple.
In the present embodiment, however, PnP VIC 22 alleviates the need for a large filter capacitor. PnP VIC 22 comprises a pair of terminals 31, which are connected respectively to bus 26 and ground 28, with only a small filtering capacitor 34 between the terminals. Switched power and control circuits in the PnP VIC, as shown in the figures that follow, maintain the voltage V between terminals 31 at a reference voltage value Vr, while substantially eliminating the ripple on bus 26. PnP VIC 22 is designed so that other than terminals 31, there is no need for any further connection between the PnP VIC and power supply 24 or any other elements of system 20.
Further details of the design and operation of switched power circuit 32 are described in the above-mentioned PCT International Publication WO 2015/019344, particularly in
Control circuit 50 monitors the voltage V between terminals 31, the voltage VS on buffering capacitor 48, and the current i flowing through the terminals, and controls switching circuitry 36 based on these monitored values so as to maintain V at the desired reference voltage value Vr. Specifically, control circuit 50 outputs binary control signals q and q, which open and close switches 38 and 40, respectively. The timing of opening and closing the switches defines a pattern of pulse-width modulation (PWM), which varies the voltage VS on buffering capacitor 48 while keeping VS within a desired range, corresponding to the predefined range over which the charge on the buffering capacitor is permitted to vary. (This functionality is described further hereinbelow with reference to
Control circuit 50 comprises digital logic circuitry for carrying out the control functions that are described herein, together with suitable sensors for measuring voltages and currents in switched power converter 32 and driver circuits for controlling switches 38 and 40. Some of these components of control circuit 50 are described further hereinbelow with reference to the figures that follow. The digital logic circuitry may comprise hard-wired or programmable logic components. Alternatively or additionally, at least some of the functions of the digital logic circuitry may be implemented by a programmable processor under the control of suitable software or firmware.
Reference is now made to
As shown in
The states of the state machine that is shown in
Control circuit 50 makes transitions between states 62, 64 and 66 in response to changes in the charge (and thus the voltage VS) on buffering capacitor 48. To prevent rapid oscillation between states, control circuit 50 applies a hysteresis to the levels of the charge on the buffering capacitor that cause transitions between the states. Thus, for example, the transition from state 62 to state 64 will occur at a higher value of VS than the opposite transition from state 64 to state 62.
By appropriate choice of the components of switched power circuit 32 and design of control circuit 50, the output impedance of PnP VIC 22 between terminals 31 in normal operating state 64 will be very small over the range of frequencies in which ripple is of concern, for example 50-1000 Hz. In an example design for this purpose, capacitors 34 and 48 may comprise ceramic or film components with values in the range of 10-100 μF, for instance, while inductor 46 has a value in the range of 50-200 μH. Designs of control circuit 50 that can be used in achieving the desired behavior are described further hereinbelow. When appropriately configured and controlled, PnP VIC 22 in state 64 will effectively eliminate ripple on bus 26 within the frequency range of interest. At higher and lower frequencies, the output impedance of the PnP VIC will be similar to that of a small capacitor.
For the purposes of
Control circuit 50 measures the current i and the voltage Vas digital values using respective sensors 80 and 82, which are represented as low-pass filters (LPF1 and LPF2). Control circuit 50 applies a controller transfer function (g1) 86 in computing a reference current value iC* based on the difference between the voltage measured by sensor 82 and the reference voltage Vr (which is initially set to a certain reference voltage level {tilde over (V)}ref and is adjusted thereafter by control circuit 50). Control circuit 50 drives switching circuitry 36 with a PWM signal based on the reference current value iP*, which is computed by subtracting iC* from the actual current measured by sensor 80.
The reference voltage Vr is adjusted by a charge control loop in control circuit 50, comprising a voltage sensor with a low-pass filter (LPF3) 84. This charge control loop operates even when the charge on buffering capacitor is outside normal charge range 54. Sensor and low-pass filter 84 measure the buffer voltage VS on buffering capacitor 48 while filtering out variations above a predefined cutoff frequency, thus giving an averaged value
Control circuit 50 subtracts
The input to digital control circuit 98 is the present value of the buffer voltage VS. The block diagram in
Control circuit 98 works as follows: The voltage control loop of PnP VIC 90 has a large bandwidth, as explained above, and thus the voltage V between terminals 31 will closely track Vr. Therefore, on horizontal segments such as segments 112 and 116, where Vr is constant, the ripple in V will be small, as desired. If V is smaller than the equilibrium voltage V0, however, more current i will continue flowing into PnP VIC 90, thus increasing VS and pushing the operating point (VS, Vr) from segment 116 onto segment 110. As VS increases further along segment 110, Vr will also increase until it reaches its maximum value on segment 112. Likewise, as VS decreases along segment 112, (VS, Vr) will reach segment 114, along which Vr will decrease as VS continues to drop.
Although the parameters of the asymmetric backlash function of
It will be appreciated that the embodiments described above are cited by way of example, and that the present invention is not limited to what has been particularly shown and described hereinabove. Rather, the scope of the present invention includes both combinations and subcombinations of the various features described hereinabove, as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description and which are not disclosed in the prior art.
This application claims the benefit of U.S. Provisional Patent Application 62/569,625, filed Oct. 9, 2017, which is incorporated herein by reference.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/IB2018/057774 | 10/8/2018 | WO | 00 |
| Number | Date | Country | |
|---|---|---|---|
| 62569625 | Oct 2017 | US |
