Patent Application
20150207345
1. Field
The disclosed embodiments generally relate to battery packs comprised of multiple battery banks coupled through a series connection. More specifically, the disclosed embodiments relate to a method and an apparatus for balancing voltages among series-connected battery banks, wherein the battery banks can have different capacities. In addition, the disclosed embodiments describe how the different voltages between the series-connected battery banks can provide simultaneous and independent load currents while maintaining battery balance.
2. Related Art
When designing battery-based devices, compromises must often be made to the battery design to accommodate competing system needs. Specifically, there are tradeoffs when selecting the number of battery banks to put in series, wherein a battery bank is defined as a set of one or more battery cells in parallel that is then treated as a single unit. Subsystem loads typically require power supply voltages that must be converted from the battery voltage using DC-DC converters, such as buck or boost converters. For most DC-DC converters, the closer the battery voltage is to the target voltage, the more efficient the conversion. Some subsystems may benefit from more banks in series, such as one that is powered by a boost converter to generate a higher voltage, while other subsystems may benefit from fewer banks in series. Therefore, the number of battery banks in series is typically chosen to optimize the overall efficiency, taking into account the power supply requirements of all of the subsystem power supplies.
In addition to conversion losses, power losses arise from the resistive paths between the battery and the input to the subsystem's DC-DC converters. For systems with large resistive paths, more banks in series can reduce overall power loss by passing the power at a higher voltage and a lower current. Placement of the DC-DC converters relative to the battery and to the subsystems is also optimized when possible to reduce loss. Similarly, charging large capacity batteries with more banks in series is often more efficient, because the current is lower for the same power, thereby reducing resistive loss. In short, the selection of the number of battery banks in series typically benefits some subsystems to the detriment of other subsystems, and a compromise must typically be made to optimize overall efficiency.
Suppose a system has some subsystems that are optimized for a two-in-series bank configuration (2S), and other subsystems optimized for a single bank configuration (1S). The designer would typically need to choose a fixed bank configuration, such as a two-in-series configuration, and use less optimal DC-DC converters for generating the lower voltage power supplies. The designer is not allowed to draw current for these lower voltage subsystems directly from the so-called 1S tap between the two banks in series because it would lead to extreme bank imbalance.
The general rule for a battery pack with banks in series is that charging and discharging of the battery pack must come from the top of the series configuration, and that tapping the voltage between banks is not allowed. For instance, if current is drawn from both the 2S tap and the 1S tap in a 2S configuration where both battery banks are identical, then the lower battery bank will be discharged by the sum of the two tapped currents, while the upper battery bank will be discharged only by the current from the 2S tap. Consequently, the lower bank will be discharged first, and no more current can be drawn from either the 1S or the 2S rail even though the upper bank may have remaining charge. Therefore, when connecting battery banks in series, the battery banks must typically match in capacity and impedance, with charging and discharging from the upper bank only; otherwise, the battery pack can suffer from an imbalance condition.
Even if battery packs are designed with balanced banks, imbalance can arise over the life of a battery pack as bank capacities and impedances degrade with time and cycles. An imbalanced battery pack has reduced capacity because the bank with the highest state-of-charge will cause the charging process to terminate, which means that banks with a lower state-of-charge never get fully charged. Additionally, when the battery pack is discharged, the bank with the least charge can cause the discharging process to stop, even though charge may remain in the other banks.
A number of techniques have been developed to handle the imbalance conditions in battery packs. These balancers can be roughly categorized as either passive or active in nature.
Passive balancers are operated by switching resistances in parallel with selected battery banks during the charging process. These resistances act to divert current around the selected banks, which causes the selected banks to charge more slowly, thereby allowing the voltage or state-of-charge to equalize across the banks. Since passive balancers effectively consume the capacity differences, they are typically used during charging only and cannot alleviate imbalance problems that arise during the discharging process. For nominally balanced banks, however, the passive balancer can be implemented with little circuitry and at low cost.
Active balancers are inductor or capacitor based and can operate during charging or discharging, or during rest. Typically the circuitry required for active balancers is more complex, larger, and more costly than that required for passive balancers, but active balancers can be more effective at keeping banks in balance. Since active balancers still consume power related to the amount of imbalance or are limited in their ability to move significant current, battery packs with active balancers are still typically designed to have banks with the same nominal capacity and impedance. Moreover, intentional imbalance is typically avoided and drawing current from between the banks is typically disallowed.
Hence, what is needed is a method and an apparatus for addressing capacity imbalance problems between battery banks without the drawbacks of existing passive balancers or active balancers.
The disclosed embodiments provide a system that balances voltages between battery banks. This system includes a plurality of asymmetric battery banks having differing capacities electrically connected to each other through a series connection. The system also includes a charging circuit configured to charge the plurality of asymmetric battery banks through the series connection. To balance voltages between the battery banks, the system includes a balancing mechanism comprising switching circuitry and an additional switching bank. This balancing mechanism equalizes voltages between the battery banks by using the switching bank to transfer charge among the plurality of asymmetric battery banks during operation of the system, including during charging and/or discharging.
In some embodiments, the plurality of asymmetric battery banks includes a first bank and a second bank. In these embodiments, the switching circuitry is configured to equalize voltages between the first bank and the second bank by iteratively: connecting the first bank in parallel with the switching bank to equalize voltages between the first bank and the switching bank; and then connecting the second bank in parallel with the switching bank to equalize voltages between the second bank and the switching bank.
In a variation on the above embodiments, the plurality of asymmetric battery banks also includes a third bank connected in series with the first and second banks, and the balancing mechanism includes a second switching bank. In these embodiments, the switching circuitry is additionally configured to equalize voltages between the second bank and the third bank by iteratively: connecting the second bank in parallel with the second switching bank to equalize voltages between the second bank and the second switching bank; and then connecting the third bank in parallel with the second switching bank to equalize voltages between the third bank and the second switching bank.
In some embodiments, the system includes a plurality of voltage rails, including: a full voltage rail connected to a positive terminal of a furthest battery bank from ground in the series connection; and at least one intermediate voltage rail connected to a positive terminal of an intermediate battery bank that is not the furthest from ground in the series connection.
In some embodiments, each battery bank in the plurality of asymmetric battery banks is coupled to: (1) a sense resistor configured to measure a current flowing through the battery bank; (2) a temperature gauge configured to measure a temperature of the battery bank; (3) safety field-effect transistors (FETs), including a charging FET configured to stop charging of the battery bank, and a discharging FET configured to stop discharging of the battery bank; and (4) a battery-management unit (BMU) front end configured to monitor current and temperature and control the safety FETs for the battery bank.
In a variation on the above embodiments, the system further comprise a gas gauge microcontroller configured to communicate with each of the BMU front ends through a level-shifted or AC-coupled communication interface.
In some embodiments, the safety FETs for each battery bank are low-side FETs, which are coupled to a low voltage terminal of the battery bank.
In some embodiments, each battery bank includes one or more battery cells connected in parallel.
The following description is presented to enable any person skilled in the art to make and use the disclosed embodiments, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the disclosed embodiments. Thus, the disclosed embodiments are not limited to the embodiments shown, but are to be accorded the widest scope consistent with the principles and features disclosed herein.
The data structures and code described in this detailed description are typically stored on a non-transitory computer-readable storage medium, which may be any device or medium that can store code and/or data for use by a computer system. The non-transitory computer-readable storage medium includes, but is not limited to, volatile memory, non-volatile memory, magnetic and optical storage devices such as disk drives, magnetic tape, CDs (compact discs), DVDs (digital versatile discs or digital video discs), or other media capable of storing code and/or data now known or later developed.
The methods and processes described in the detailed description section can be embodied as code and/or data, which can be stored in a non-transitory computer-readable storage medium as described above. When a computer system reads and executes the code and/or data stored on the non-transitory computer-readable storage medium, the computer system performs the methods and processes embodied as data structures and code and stored within the non-transitory computer-readable storage medium. Furthermore, the methods and processes described below can be included in hardware modules. For example, the hardware modules can include, but are not limited to, application-specific integrated circuit (ASIC) chips, field-programmable gate arrays (FPGAs), and other programmable-logic devices now known or later developed. When the hardware modules are activated, the hardware modules perform the methods and processes included within the hardware modules.
The system also includes a battery-management unit (BMU) front end 110, which is responsible for measuring the temperature, current, and voltages of both bank A 102 and bank B 104. (Note that current is monitored by measuring the voltage drop across a sense resistor RSNS 103, which is also incorporated into the series connection.) BMU front end 110 communicates with a gas-gauge microcontroller (gauge μC) 112 that performs computational operations based on the temperature current and voltage information obtained by BMU front end 110. Gauge μC 112 uses this information to control charge pump 106 and balancer 108. Note that balancer 108 can be either an “active balancer” or a “passive balancer,” which uses resistors, capacitors or inductors to maintain a voltage or state of charge balance between bank A 102 and bank B 104.
Battery Pack with a Balancing Bank
We now describe a system that uses a special battery bank called a “switching bank” to equalize voltages between series-connected battery banks. To equalize voltages, this switching bank can be switched in parallel between different series-connected banks. This allows current to be drawn from both the top of the battery pack as well as between the battery banks, while keeping the battery pack in balance. Such a battery pack is called an asymmetric, balanced, multi-S battery. The term “multi-S” indicates that the battery can be simultaneously charged or discharged from any series-connected bank. The term “balanced” indicates that all of the banks in the battery pack are nominally kept at the same voltage, such that if they were composed of the same chemistry they would charge to full and empty at the same time, thereby maximizing available capacity. The term “asymmetric” indicates that the battery banks need not be the same capacity, although an optimal asymmetry typically exists for a given system.
The switching bank C 206 operates like the switching capacitor in a switched capacitor circuit, where the current flow through bank C 206, IC, is approximately given by:
where QC is bank C 206's capacity, f is the switching frequency, Ron is the on-resistance of a single switching FET, and the voltages of banks A 202, B 204, and C 206 are VA, VB and VC, respectively. For a large bank capacity, significant current can be moved while keeping the frequency f relatively low, on the order of once a second. Consequently, the switching losses associated with switching the Hi and Lo FETs 232-235 connected to bank C can be made insignificant.
Equation (1) can be used to estimate the current flowing into and out of bank C 206, but not as accurately as directly measuring the voltage across the sense resistor, RSNSC 226. For accurate gauging, a measurement integrated circuit (IC), shown as the BMU front-end blocks 208, 210 and 212 in
Each BMU front end also controls two safety FETs that allow charging or discharging the bank when enabled. In
To operate the asymmetric, balanced, multi-S battery, bank C 206 is initially connected in parallel with bank A 202 by enabling both Lo A FET 235 and Hi A FET 233, during phase A. Current will flow between banks A 202 and C 206 bringing them to the same voltage. Then, in phase B, bank C 206 is switched in parallel to bank B 204, by first disabling the Lo A FET 235 and Hi A FET 233, and then enabling Lo B FET 234 and Hi B FET 232. Again, current will flow between banks C 206 and B 204 bringing them to the same voltage. This process is repeated, keeping the voltages of all banks equal, via the switching bank C 206, even with different loads on the 1S and 2S rails. Consequently, the concerns that arise from imbalanced packs are eliminated even as the bank's capacities and impedances change with age and cycling.
In addition to being able to provide simultaneous current at both the 1S and 2S rails, a major advantage of the asymmetric, balanced, multi-S battery is that the capacities of the three banks do not need to be same. For highest performance, the capacities of the banks should be designed in proportion to the expected typical load so that the switching currents are minimized. Since the bank capacities need not be the same, the product can be optimized to maximize the battery volume without restrictions on symmetry. In addition, the process of characterizing and matching cells when building packs in order to minimize imbalance can be eliminated, which reduces manufacturing costs.
Since the banks are allowed to be different sizes, the requirement of an additional bank does not increase the size of the battery pack. The available capacity is simply the sum of the bank's capacities. Hence three smaller banks could take the place of two larger banks in the standard configuration and still provide the same amount of charge.
Since the balancing bank keeps the voltage the same among all banks and not the state-of-charge, the chemistry of the different banks should ideally be the same in order for the states-of-charge of the different banks to be the same when the load currents go to zero.
While the asymmetric, balanced, multi-S battery solves the problems of multi-S discharge and the use of different sized banks while maintaining balance, the design does provide challenges for coulomb counting, pack resistance, and communications.
A valuable component to accurately gauging a battery pack is to integrate the current going into and out of each bank, in a process called the “coulomb count.” In a typical series configured battery, only a single sense resistor is required since the current flowing into each of the banks in series is the same. However, in the asymmetric, balanced, multi-S battery, a sense resistor and separate coulomb count are required for each bank because the currents are different from one another.
In addition to the component cost of the additional sense resistors and coulomb counters, the series resistance of the pack is higher than a standard series configured battery. For instance, even if the asymmetric, balanced, multi-S battery is used in a system that only draws current from the 2S rail, with no current flow into balancing bank C 206, the discharge current still needs to flow through the two sense resistors RSNSA 228 and RSNSB 230 rather than flowing through a single necessary sense resistor RSNS 103 in the standard series configuration battery, shown in
A standard series configuration battery only requires a single set of charge and discharge FETs for safety, whereas the asymmetric, balanced, multi-S battery requires a set for each charge/discharge rail increasing the series resistance. When discharging from the 2S rail in
Even with the higher series resistance, the performance of the asymmetric, balanced, multi-S battery typically exceeds the standard series configuration battery due to the efficiency improvements gained by the system being able to use both the 1S and 2S rails.
Communicating with the BMU front ends also presents a challenge because not all of the front ends are ground-referenced. The BMU front end on bank B 204, for instance, is referenced to the 1S rail. Even more challenging, the BMU front end on the switching bank C 206 is sometimes referenced to ground, sometimes referenced to 1S, and sometimes disconnected entirely (except by FET body diodes), depending upon the state of the switching FETs. Consequently, the communications from the ground-referenced system to the BMU front ends need to be either level-shifted or AC-coupled as indicated by the capacitors 222-224 in series with the communication lines in
A benefit of a level-shifted or AC-coupled communication interface is that communication is not disrupted when the safety FETs are disabled. In the standard series configuration battery, communication disruption is avoided by putting the safety FETs on the high side. The disadvantage to high-side NFETs is the need for a power consuming charge pump, shown in
The asymmetric, balanced, multi-S battery is highly modular and easily extendible to any number of batteries in series. For example
In an alternative embodiment, instead of using two switching banks, the system can use a single switching bank, which is switched among three battery banks A 301, B 302 and C 303. Note that this embodiment requires additional switching circuitry to allow the single switching bank to be electrically connected to the three battery banks A 301, B 302 and C 303.
While the battery pack is operating, the system equalizes voltages between the first bank and the second bank by iteratively connecting the first bank in parallel with the switching bank to equalize voltages between the first bank and the switching bank (step 404), and then connecting the second bank in parallel with the switching bank to equalize voltages between the second bank and the switching bank (step 406). Note that this iterative switching process can take place at a relatively low frequency, such as once a second. Moreover, the switching process can take place automatically, without having to adjust the switching intervals. Alternatively, the system can temporarily suspend or otherwise modulate the switching operations based on the voltage balance between battery banks.
While the battery pack is operating, the system equalizes voltages among the first, second and third banks by iteratively performing the following operations. The system first connects the first bank in parallel with the switching bank to equalize voltages between the first bank and the switching bank. At the same time, the system connects the second bank in parallel with the second switching bank to equalize voltages between the second bank and the second switching bank (step 504). Next, the system connects the second bank in parallel with the switching bank to equalize voltages between the second bank and the switching bank. At the same time, the system connects the third bank in parallel with the second switching bank to equalize voltages between the third bank and the second switching bank (step 506).
The above-described asymmetric, balanced, multi-S battery is capable of improving system runtime by providing simultaneous battery voltage rails without incurring loss of capacity due to imbalance. In addition, the battery banks need not be the same size, thereby eliminating design constraints for the system designer and eliminating the need to bin batteries in the factory in order to build balanced packs.
The foregoing descriptions of embodiments have been presented for purposes of illustration and description only. They are not intended to be exhaustive or to limit the present description to the forms disclosed. Accordingly, many modifications and variations will be apparent to practitioners skilled in the art. Additionally, the above disclosure is not intended to limit the present description. The scope of the present description is defined by the appended claims.
