NSF Award
0839272
This Small Business Innovation Research (SBIR) Phase I project will develop a novel approach to through-wafer via formation in silicon. Vertical stacking of MEMS and CMOS devices is becoming increasingly popular for increasing functional density, and for combining specialized microelectromechanical systems (MEMS) with standard silicon integrated circuits. Vertical stacking generally requires that via holes for contacts be formed through a wafer using anisotropic etching, but current low-pressure techniques for performing this step are slow and expensive. This project will apply the company?s unique Linear Inductive Plasmatron technology to silicon etching using both the current multistep (etch/passivation) approach and single-step etching. The increased species densities at atmospheric pressure should enable passivation and etching of high-aspect-ratio features without etch-stop behavior observed at low pressure, and low electron temperatures ensure minimal plasma damage.<br/><br/>If successful such a tool will greatly reduce the cost of via fabrication and enable 3D stacking of circuitry in applications where it would otherwise be prohibitively expensive. The unique characteristics of an atmospheric-pressure plasma etch process allow design of a processing tool that combines low cost, high throughput, and high performance. Because gas flows can be used to define reaction regions, wafers can be exposed to multiple process steps at high rates in batches using a carousel-type architecture. Once proven as a semiconductor manufacturing tool, the Linear Inductive Plasmatron is likely to find other applications in high-rate, low-cost processing for semiconductor fabrication, photovoltaic fabrication, and other manufacturing dependent on thin film deposition and etch processes.
