The present invention relates generally to integrated circuit fabrication, and, more specifically, the present invention relates to the fabrication of a self-aligned device design and process flow that allows for a compact bipolar junction transistor layout.
An epitaxial bipolar junction transistor (BJT) exhibits the presence of defects at the monocrystalline/polycrystalline boundary of the base. The defects may include misfit dislocations, stacking faults, screw dislocations, and the like. Such defects may cause unacceptable current leakage in the BJT. Where the defects are large enough, a short may even occur between the emitter and the collector.
One method of reducing the leakage is to heavily dope the monocrystalline-polycrystalline boundary region with an element that will electrically insulate, in order to enclose the leakage region 32. The implanted, doped enclosure 34 may reduce or significantly eliminate the possibility of the defects being an additional source of leakage in the BJT 10. In order for the implant to get through, a sufficient amount of a first space 36 needs to remain between the edge of the monocrystalline base 26 and the polysilicon of emitter structure 30, where the leakage region 32 may be found. Additional space 38 is needed between the edge of the polysilicon of structure 30 and the emitter cut to avoid the high dose of boron from diffusing from doped enclosure 34 to the emitter/base junction.
The need for both the heavy doping and the spaces 36 and 38 causes the BJT 10 to be large in cell layout size. A large cell layout size increases parasitic capacitance and resistance, both of which are associated with the base and collector. This increase degrades the performance of the BJT 10.
In order that the manner in which the embodiments of the invention are obtained, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings. Understanding that these drawings depict only typical embodiments of the invention that are not necessarily drawn to scale and are not therefore to be considered to be limiting of its scope, the invention will be described and explained with additional specificity and detail through the use of the accompanying drawings in which:
The present invention relates to a process of forming a bipolar junction transistor (BJT) that has a compact layout and that resists leakage.
An optional oxide pre-layer 124 is disposed above and on substrate 112. Above substrate 112, an etch resistant layer including a first layer 126 is formed, followed by a second layer 128. Optional oxide pre-layer 124, is formed on substrate 112 by a process flow selected from thermal growth, deposition, and native oxide growth. Whether first layer 126 and second layer 128 are made of different materials, e.g. oxide-nitride, or whether they are made of differing types of the same material, e.g. oxide-oxide, first layer 126 and second layer 128 have different responses to an etch recipe. Similarly, and optionally, first layer 126 and second layer 128 have different responses to an oxidation process.
In one embodiment, first layer 126 is an oxide layer. The first layer 126, when it is an oxide layer, may be a thermal oxide, a deposited oxide, or a combination thereof. Oxides that may be selected include silica, titania, ceria, thoria, alumina, zirconia, hafnia, and the like. In this embodiment, second layer 128 is a nitride layer. Second layer may be selected from silicon nitride, titanium nitride, aluminum nitride, and the like.
According to the present invention, a process flow integration is selected that dictates limited composition options of first layer 126 and second layer 128. In one embodiment first layer 126 and second layer 128 are configured wherein the first layer and the second layer are respectively selected from a first oxide layer and a second nitride layer. In another embodiment, the first layer and the second layer are respectively selected from a first nitride layer and a second oxide layer. In another embodiment, the first layer and the second layer are respectively selected from a first oxide layer and a second oxide layer. In another embodiment, the first layer and the second layer are respectively selected from a first nitride layer and a second nitride layer. In another embodiment, the first layer and the second layer are respectively selected from a first inorganic layer and a second organic layer. In another embodiment, the first layer and the second layer are respectively selected from a first organic layer and a second inorganic layer. In another embodiment, the first layer and the second layer are respectively selected from a first organic layer and a second organic layer. In another embodiment, the first layer and the second layer are respectively selected from and a first inorganic layer and a second inorganic layer.
A topology over substrate 112 is formed in first layer 126, second layer 128, and optional oxide pre-layer 124. A topology is understood to be a vertical relief in at least one layer with respect to the substrate. Patterning may be accomplished by a mask 130. Mask 130 may be a spin-on resist as is know in the art, or it may be a hard mask as is understood in the art.
In one exemplary embodiment, after forming oxide pre-layer 124 on the substrate 112, an oxide embodiment of first layer 126 is formed, a nitride embodiment of second layer 128 is formed, mask 130 is formed, and patterning is carried out with an anisotropic dry etching of second layer 128. The anisotropic dry etching may be a reactive ion etch (RIE), followed by an alternative wet clean as is known in the art.
Thereafter, patterning is finished with an isotropic wet etching of first layer 126 to expose an upper surface 132 and to form the topology. Optionally, oxide pre-layer 124 is etched in connection with the etching of first layer 126. First layer 126 and second layer 128 may be selected to be either oxide, nitride, organic, or otherwise according to a specific process integration. For example, where BJT 110 is part of a logic structure, fabrication of an embedded memory array elsewhere on the substrate may call for a nitride layer and an oxide layer. In this example, first layer 126 may be the same nitride- and second layer 128 may be the same oxide that act to cover the memory array during processing of the BJT 110.
Processing conditions for the formation of epitaxial base layer 138 may be carried out according to process flows that are known in the art. Epitaxial base layer 138 may be carried out by a chemical vapor deposition (CVD) process flow selected from low-pressure CVD (LPCVD), reactive-plasma CVD (RCVD), plasma-enhanced CVD (PECVD), and combinations thereof as known in the art. By way of one non-limiting example, the CVD process flow may be carried out in a pressure range from about 10−2 Torr, to about 2×10−1 Torr. The CVD gas may be supplied as a silane type gas or a doped silane type gas.
Leakage block structures are formed according to a diffusion process flow embodiment of the present invention.
Further processing is carried out to form a base tap 154 and a collector tap 156 according to process flows known in the art. As such, a BJT 110 is formed according to an embodiment. Essential to BJT 110 is emitter structure 146, emitter/base junction region 152, and collector structure 118.
It is noted that dopant that is diffused out of doped spacer 136 forms a leakage block structure 158 that allows the inventive BJT 110 to have smaller dimensions than the existing BJT. Leakage block structure 158 is a region where dopant has a concentration gradient within substrate 112. In other words, substrate 112 is an integral crystalline structure wherein leakage block structure 158 is disposed, and a concentration gradient within leakage block structure 158 exists in the direction of doped spacer.
In accordance with one embodiment of the present invention, a process flow is carried out during which out-diffused dopant from doped spacer 136 forms leakage block structure 158, especially at the monocrystalline-polycrystalline interface of epitaxial base layer 138. In an embodiment where doped spacer 136 is p-doped with, by way of non-limiting example, boron, a process flow is carried out under thermal conditions in a range from about 700° C. to about 1,200° C. In another non-limiting example where doped spacer 136 is p-doped, a process flow is carried out under thermal conditions in a range from about 800° C. to about 1,100° C. In yet another non-limiting example where doped spacer 136 is p-doped, a process flow is carried out under thermal conditions in a range from about 900° C. to about 1,000° C. Processing times may vary according to a specific embodiment and process integration. Processing times will be selected based upon dopant concentration in doped spacer 136, and the amount of out-diffusion needed in order to block the monocrystalline-polysilicon interface, between polycrystalline epitaxial base 140 and monocrystalline epitaxial base 142, of epitaxial base layer 138. Accordingly, leakage block structure 158 is formed in substrate 112. The leakage block structure 158 may block either current, potential, or both.
The out-diffused dopant may be referred to as a leakage block structure 158 that represents a dopant gradient in an integral section of monocrystalline silicon; meaning the non-epitaxial portion or the monocrystalline silicon of substrate 112. As is illustrated, a BJT 110 is formed between the two doped spacers 136.
In an alternative embodiment, doped spacer 136 may be substantially undoped such that it behaves as a dopant getterer or dopant sink for dopant within substrate 112. Accordingly, leakage block structure 158 is a region of substrate 112 with depleted dopant with respect to the rest of substrate 112. In this manner, electrical activity therein is hindered after a manner that is opposite to a substantially undoped leakage block structure 158.
Several of the embodiments set forth in this disclosure may be used with a bipolar-complementary metal oxide semiconductor (BiCMOS) process flow. For example, first layer 126 and second layer 128 are utilized as protective layers over a CMOS region (not depicted) of substrate 112 during forming doped spacer 136 at the topology. Thereafter, a CMOS process flow may be carried out in which at least portions of first layer 126 and second layer 128 are opened.
As illustrated in
The leakage block structure perimeter 228 is substantially symmetrical to the epitaxial base perimeter 214. The emitter stack perimeter 226 and the leakage block structure perimeter 228 intersect. The leakage block structure perimeter 228 is enclosed within the epitaxial base perimeter 214. Whereas the base tap 218 is enclosed by the leakage block structure 224, it can be seen by contrast from
It will be readily understood to those skilled in the art that various other changes in the details, material, and arrangements of the parts and method stages which have been described and illustrated in order to explain the nature of this invention may be made without departing from the principles and scope of the invention as expressed in the subjoined claims.
This is a divisional application of Ser. No. 10/013,225 filed Dec. 10, 2001, which is U.S. Pat. No. 6,579,771.
Number | Name | Date | Kind |
---|---|---|---|
4142117 | Chang | Feb 1979 | A |
4330569 | Gulett et al. | May 1982 | A |
4830972 | Hamasaki | May 1989 | A |
5024957 | Harame et al. | Jun 1991 | A |
5137840 | Desilets et al. | Aug 1992 | A |
5323032 | Sato et al. | Jun 1994 | A |
5523245 | Imai | Jun 1996 | A |
5837929 | Adekman | Nov 1998 | A |
5877540 | Naruse et al. | Mar 1999 | A |
6080631 | Kitahata | Jun 2000 | A |
20010048134 | Park | Dec 2001 | A1 |
Number | Date | Country |
---|---|---|
0189135 | Jul 1986 | EP |
0779663 | Jun 1997 | EP |
1058302 | Dec 2000 | EP |
Number | Date | Country | |
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20030219939 A1 | Nov 2003 | US |
Number | Date | Country | |
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Parent | 10013225 | Dec 2001 | US |
Child | 10418395 | US |