SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Abstract

To provide a semiconductor device having a structure in which a barrier metal film containing nitrogen is formed in a connection surface between a copper alloy wiring and a via, in which the electric resistance between the copper alloy wiring and the via can be prevented from rising, and the electric resistance can be prevented from varying. A semiconductor device according to the present invention comprises a first copper alloy wiring, a via and a first barrier metal film. The first copper alloy wiring is formed in an interlayer insulation film and contains a predetermined additive element in a main component Cu. The via is formed in an interlayer insulation film and electrically connected to the upper surface of the first copper alloy wiring. The first barrier metal film is formed so as to be in contact with the first copper alloy wiring in the connection part between the first copper alloy wiring and the via and contains nitrogen. The predetermined additive element reacts with nitrogen to form a high-resistance part. In addition, the concentration of the predetermined additive element is not more than 0.04 wt %.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an enlarged sectional view showing a substantial constitution of a semiconductor device according to an embodiment 1;

FIG. 2 is an explanatory sectional view showing a manufacturing step of the semiconductor device according to the embodiment 1;

FIG. 3 is an explanatory sectional view showing a manufacturing step of the semiconductor device according to the embodiment 1;

FIG. 4 is an explanatory sectional view showing a manufacturing step of the semiconductor device according to the embodiment 1;

FIG. 5 is an explanatory sectional view showing a manufacturing step of the semiconductor device according to the embodiment 1;

FIG. 6 is an explanatory sectional view showing a manufacturing step of the semiconductor device according to the embodiment 1;

FIG. 7 is an explanatory sectional view showing a manufacturing step of the semiconductor device according to the embodiment 1;

FIG. 8 is an explanatory sectional view showing a manufacturing step of the semiconductor device according to the embodiment 1;

FIG. 9 is an explanatory sectional view showing a manufacturing step of the semiconductor device according to the embodiment 1;

FIG. 10 is an explanatory sectional view showing a manufacturing step of the semiconductor device according to the embodiment 1;

FIG. 11 is a top plan view showing the semiconductor device being manufactured;

FIG. 12 is an explanatory sectional view showing a manufacturing step of the semiconductor device according to the embodiment 1;

FIG. 13 is an explanatory sectional view showing a manufacturing step of the semiconductor device according to the embodiment 1;

FIG. 14 is a view showing an experiment result in which the concentration of an additive element and variations in resistance are measured;

FIG. 15 is an enlarged sectional view showing a substantial constitution of a semiconductor device according to an embodiment 3;

FIG. 16 is an explanatory sectional view showing a manufacturing step of the semiconductor device according to the embodiment 3;

FIG. 17 is an explanatory sectional view showing a manufacturing step of the semiconductor device according to the embodiment 3;

FIG. 18 is an explanatory sectional view showing a manufacturing step of the semiconductor device according to the embodiment 3;

FIG. 19 is an explanatory sectional view showing a manufacturing step of the semiconductor device according to the embodiment 3;

FIG. 20 is an explanatory sectional view showing a manufacturing step of the semiconductor device according to the embodiment 3;

FIG. 21 is a sectional view showing that the constitution according to the embodiment 3 is sequentially provided over a lower to upper layers;

FIG. 22 is an explanatory sectional view showing a manufacturing step of a semiconductor device according to the embodiment 4;

FIG. 23 is an explanatory sectional view showing a manufacturing step of the semiconductor device according to the embodiment 4;

FIG. 24 is an explanatory sectional view showing a manufacturing step of the semiconductor device according to the embodiment 4;

FIG. 25 is an explanatory sectional view showing a manufacturing step of the semiconductor device according to the embodiment 4;

FIG. 26 is an explanatory sectional view showing a manufacturing step of the semiconductor device according to the embodiment 4; and

FIG. 27 is a sectional view showing that the constitution according to the embodiment 4 is sequentially provided over a lower to upper layers;

Claims

1. A semiconductor device comprising: a first copper alloy wiring formed in an interlayer insulation film and containing a predetermined additive element in a main component Cu;a via formed in said interlayer insulation film and electrically connected to the upper surface of said first copper alloy wiring; anda first barrier metal film formed between said first copper alloy wiring and said via, and being in contact with said first copper alloy wiring, and containing nitrogen, whereinthe concentration of said predetermined additive element is not more than 0.04 wt %.

2. The semiconductor device according to claim 1, wherein the concentration of said predetermined additive element is not less than 0.01 wt %.

3. The semiconductor device according to claim 1, wherein said predetermined additive element is Al, Si, Ge, Ga or Sn.

4. The semiconductor device according to claim 1, wherein the material of said first barrier metal film is TaN, TaSiN, TiN or WN.

5. The semiconductor device according to claim 1, wherein said interlayer insulation film contains an SiOC film.

6. The semiconductor device according to claim 1, further comprising: a second copper alloy wiring provided in said interlayer insulation film above said first copper alloy wiring and electrically connected to the upper surface of said via, whereineach of said first copper alloy wiring, said second copper alloy wiring and said via contains a predetermined additive element in a main component Cu.

7. The semiconductor device according to claim 1, further comprising: said first barrier metal film being in contact with said interlayer insulation film, between said interlayer insulation film and said via; anda second barrier metal film not containing nitrogen and being in contact with said via, between said interlayer insulation film and said via.

8. The semiconductor device according to claim 7, further comprising a wiring provided in said interlayer insulation film above said first copper alloy wiring and electrically connected to the upper surface of said via, wherein said first barrier metal film is formed between said interlayer insulation film and said wiring, and is in contact with said interlayer insulation film, andsaid second barrier metal film is formed between said interlayer insulation film and said wiring, and is in contact with said wiring.

9. The semiconductor device according to claim 1, wherein the concentration of nitrogen contained in said first barrier metal film is not less than 10 atom % but not more than 40 atom %.

10. The semiconductor device according to claim 7, wherein the film thickness of said first barrier metal film is not less than 1 nm but not more than 10 nm.

11. The semiconductor device according to claim 8, wherein the film thickness of said first barrier metal film is not less than 1 nm but not more than 10 nm.

12. A semiconductor device comprising: a first copper alloy wiring provided in a first interlayer insulation film and containing Al in a main component Cu;a second interlayer insulation film formed on said first interlayer insulation film; anda second copper alloy wiring provided in said second interlayer insulation film and containing Al in a main component Cu, whereinthe concentration of said Al in said second copper alloy wiring is less than the concentration of said Al in said first copper alloy wiring.

13. The semiconductor device according to claim 12, wherein the film thickness of said second copper alloy wiring is more than that of said first copper alloy wiring.

14. The semiconductor device according to claim 12, wherein said first interlayer insulation film and said second interlayer insulation film have different relative permittivity.

15. A semiconductor device comprising: a copper alloy wiring provided in a first interlayer insulation film and containing Al in a main component Cu;a second interlayer insulation film formed on said first interlayer insulation film; anda copper wiring not containing Al, provided in said second interlayer insulation film and having a film thickness larger than that of said copper alloy wiring.

16. A semiconductor device comprising: a first dual damascene structure provided in a first interlayer insulation film, comprising a first wiring and a first via, and containing Al in a main component Cu;a second interlayer insulation film formed on said first interlayer insulation film; anda second dual damascene structure provided in said second interlayer insulation film, comprising a second wiring having a film thickness larger than that of said first wiring and a second via whose lower surface is connected to the upper part of said first wiring, made of a copper wiring, and not containing Al.

17. The semiconductor device according to claim 16, wherein the diameter of said second via is larger than that of said first via.

18. The semiconductor device according to claim 16, further comprising: a first barrier metal film formed between the bottom of said second via and the upper surface of said first wiring, and being in contact with said first wiring in the connection part, and containing nitrogen, whereinthe concentration of said Al contained in said first wiring is not more than 0.04 wt %.

19. The semiconductor device according to claim 18, wherein the concentration of said Al contained in said first wiring is not less than 0.01 wt %.

20. The semiconductor device according to claim 18, further comprising: a second barrier metal film formed between said second dual damascene structure and said interlayer insulation film, and being in contact with said second dual damascene structure, and not containing nitrogen, whereinsaid first barrier metal film is formed between said second dual damascene structure and said interlayer insulation film also, and is in contact with said interlayer insulation film.

21. The semiconductor device according to claim 14, wherein each of said first interlayer insulation film and said second interlayer insulation film contains an SiOC film or an FSG film.

22. A semiconductor device, comprising: a first via formed in an interlayer insulation film and containing Al in a main component Cu;a first copper alloy wiring formed in said interlayer insulation film, electrically connected to the bottom of said first via, and containing Al in a main component Cu;a first barrier metal film formed between said interlayer insulation film and said first via, and being in contact with said interlayer insulation film, and containing nitrogen; anda second barrier metal film formed between said interlayer insulation film and said first via, and being in contact with said first via, and not containing nitrogen, whereinsaid first barrier metal film is not formed in the connection part between said first copper alloy wiring and said first via, andsaid second barrier metal film is formed in the connection part between said first copper alloy wiring and said first via also.

23. The semiconductor device according to claim 22, further comprising: a second via formed in said interlayer insulation film, electrically connected to the bottom of said first copper alloy wiring, and containing Al in a main component Cu, anda second copper alloy wiring formed in said interlayer insulation film, electrically connected to the bottom of said second via, and containing Al in a main component Cu, characterized in thata third barrier metal film containing nitrogen, and formed between said interlayer insulation film and said second via, and being in contact with said interlayer insulation film, anda fourth barrier metal film not containing nitrogen, and formed between said interlayer insulation film and said second via, and being in contact with said second via, whereinsaid third barrier metal film is not formed in the connection part between said second copper alloy wiring and said second via, andsaid fourth barrier metal film is also formed in the connection part between said second copper alloy wiring and said second via.

24. A manufacturing method of a semiconductor device comprising: (A) a step of forming a copper alloy wiring containing copper as a main component and an additive element having a concentration of 0.04 wt % or less, in a first interlayer insulation film;(B) a step of forming a connection hole from which the upper surface of said copper alloy wiring is exposed, in a second interlayer insulation film formed on said first interlayer insulation film;(C) a step of forming a first barrier metal film containing nitrogen, on the bottom and side of said connection hole; and(D) a step of filling said connection hole with a conductor after said step (C).

25. The manufacturing method of a semiconductor device according to claim 24, further comprising: (E) a step of removing said first barrier metal film formed on the bottom of said connection hole and a part of said copper alloy wiring, and(F) a step of forming a second barrier metal film not containing nitrogen, on the bottom and side of said connection hole after said step (E).

26. The manufacturing method of a semiconductor device according to claim 24, further comprising: (K) a step of forming a second barrier metal film not containing nitrogen, on said first barrier metal film;(L) a step of removing said first barrier metal film and said second barrier metal film formed on the bottom of said connection hole and a part of said copper alloy wiring; and(M) a step of forming a third barrier metal film not containing nitrogen, on the bottom and side of said connection hole after said step (L).

27. A manufacturing method of a semiconductor device comprising: (A) a step of providing a first copper alloy wiring containing Al in a main component Cu, in a first interlayer insulation film;(B) a step of forming a second copper alloy wiring containing Al in a main component Cu, having a film thickness larger than that of said first copper alloy wiring, and having an Al concentration lower than the Al concentration of said first copper alloy wiring, in a second interlayer insulation film formed on said first interlayer insulation film.

28. A manufacturing method of a semiconductor device comprising: (A) a step of providing a copper alloy wiring containing Al in a main component Cu, in a first interlayer insulation film; and(B) a step of forming a copper wiring having a film thickness larger than that of said copper alloy wiring and not containing Al, in a second interlayer insulation film formed on said first interlayer insulation film.

29. A manufacturing method of a semiconductor device comprising: (A) a step of forming a first dual damascene structure comprising a first wiring and a first via and containing Al in a main component Cu, in a first interlayer insulation film; and(B) a step of forming a second dual damascene structure comprising a second wiring having a film thickness thicker than that of said first wiring and a second via whose lower surface is connected to the upper part of said first wiring, and not containing Al, in a second interlayer insulation film formed on said first interlayer insulation film.