Semiconductor integrated circuit device

BACKGROUND OF THE INVENTION

[0002] This invention relates to a semiconductor integrated circuit device and to a fabrication process thereof, and more particularly, the invention relates to a technique which is effective when applied to a semiconductor integrated circuit device, which is fabricated by a process including a planarization step using the CMP (Chemical Mechanical Polishing) method.

[0003] To satisfy the continuing tendency to decrease the minimum processing size of a semiconductor integrated circuit device, in an exposure optical system, an increase in the performance of a stepper is required, which promotes a widening of the aperture size of a lens and a shortening of the exposure wave length. As a result, the focus depth of the exposure optical system decreases and even a slight unevenness on the surface to be processed becomes a problem. Therefore, the accurate planarization of the surface to be processed becomes an important technical objective for the device process. Furthermore, the above planarization does not aim at the easing of a stepped portion for the purpose of preventing a short cut of interconnections formed on the stepped portion, but is directed to a global planarization, in other words, a complete planarization.

[0004] As a surface planarization technique, there are a method of coating an SOG (Spin On Glass) film or a low-melting-point glass by melting it, a method of heat treatment through glass flow, a self planarization method adopting a surface reaction mechanism of CVD (Chemical Vapor Deposition) and the like. Owing to the surface conditions, to the heat treatment conditions being applied or to limitations in processing, in many cases, it is impossible to carry out complete planarization, that is, global planarization, using these methods. Therefore, the etchback and CMP processes are regarded as promising practical techniques which permit complete planarization.

[0005] As for the etchback process, the use of a photoresist as a sacrificial film, the use of an SOG film and the use of a self-planarization CVD film are known, but they are accompanied by such drawbacks as a complex procedure, a high cost and a lowering of the yield due to production of particles. The CMP process has, on the other hand, come to be regarded as an excellent process from an overall viewpoint, because, compared with the etchback process, it is more free from the above-described problems. Consequently, the CMP process is considered to be most promising as a practical technique for effecting complete planarization.

[0006] The CMP technique is described in, for example, Japanese Patent Application Laid-Open No. HEI 7-74175, U.S. Pat. No. 5,292,689 and “1996 Symposium on VLSI Technology Digest of Technical Papers, 158-159(1996)”.

SUMMARY OF THE INVENTION

[0007] During the investigation of a technique for the complete planarization of a device surface to which the CMP method is applied, which technique is not, however, a known process, the present inventors have recognized that there are the following drawbacks.

[0008] FIGS. 29(a) to 29(d) are each a cross-sectional view illustrating a planarization technique using the CMP method which the present inventors have investigated. For covering an interconnection with an insulating film and then planarizing the insulating film, an interconnection 102 is formed on an interlayer insulating film 101 (FIG. 29(a)); a first insulating film 103 and a second insulating film 104, such as SOG, are deposited to embed a concave portion thereof by the plasma CVD method or the like using TEOS (Tetraethoxysilane: (C2H5O)4Si) (FIG. 29(b)); a third insulating film 105 is deposited by the plasma CVD method using TEOS (FIG. 29(c)); and then the third insulating film 105 is polished by the CMP method for effecting planarization (FIG. 29(d)).

[0009] At the present time, in the designing of a layout based on principles of functional design and logic design, the most important consideration concerning the pattern of the interconnection 102 has been based on whether the pattern follows the ordinary layout rule or not, and polishing properties in the CMP step have not been taken into particular consideration.

[0010] The interconnection pattern is therefore not uniform, being sparse in some places and dense in some places. In the drawing illustrating the technique under investigation (FIG. 29(d)), it is seen that the interconnections 102 are dense in the portion A, while they are sparse in the other region. When CMP polishing is conducted under such a state, that is, a state where interconnections 102 are not disposed uniformly, being sparse in some places and dense in some places, the surface of the third insulating film 105 cannot be planarized completely. In a region where the interconnections 102 are dense, there appears a difference of 0.2 to 0.3 μm in height in the region A and a large undulation inevitably remains on the surface.

[0011] On the surface having such an undulation, the processing margin lowers in the subsequent photolithography step or etching step, and it becomes difficult to satisfy minute processing and heightening requirements of integration, which makes it impossible to bring about an improvement in the reliability of the semiconductor integrated circuit device and also an improvement in the yield. In addition, the existence of an undulation requires the optimization of the process conditions in order to carry out lithography and etching favorably in such a state, and an optimization of the CMP step also becomes necessary to suppress the undulation to a minimum. The time required for such optimization sometimes undesirably delays the starting time of the mass-production process.

[0012] In the region where the interconnections 102 are disposed sparsely, the recess between the interconnections 102 is not embedded sufficiently with the second insulating film 104, and so the third insulating film 105 must be thicker in order to fill in such a recess completely, which consequently causes problems, such as an increase in the polishing amount of the third insulating film 105 and a rise in the step load in the CMP step, as well as an increase in the step load, such as a long deposition time, of the third insulating film 105.

[0013] An object of the present invention is to completely planarize the surface of a member which has been polished by the CMP method.

[0014] Another object of the present invention is to provide a technique which can improve the processing margin in the photolithography and etching steps, thereby to achieve minute processing and an increased integration, while, at the same time, improving the reliability and yield of the semiconductor integrated circuit device.

[0015] A further object of the present invention is to facilitate the start of the process.

[0016] A still further object of the present invention is to reduce the amount of polishing of a member to be polished by the CMP method and to decrease the load and time of the polishing step, thereby improving the cost competitive advantage.

[0017] A still further object of the present invention is to provide a method of designing a member pattern which can be planarized completely by the CMP method.

[0018] A still further object of the present invention is to suppress an increase in the parasitic capacitance of an interconnection or the like which is caused by the measures to achieve complete planarization, thereby maintaining the performance of the semiconductor integrated circuit device.

[0019] The above-described and other objects, and novel features of the present invention will be more apparent from the following description and accompanying drawings.

[0020] Typical features of the invention disclosed by the present application will be described briefly.

[0021] (1) The semiconductor integrated circuit device according to the present invention comprises actual interconnections which are formed on a principal surface of a semiconductor substrate or an interlayer insulating film constituting a semiconductor integrated circuit element, and an insulating film containing a film which covers the actual interconnections and has been planarized by the CMP method; wherein dummy interconnections, formed of the same material as that of the actual interconnections, but not functioning as an element, are formed in an empty space between adjacent, spaced interconnections in the interconnection layer where said actual interconnections are formed.

[0022] In addition, the semiconductor integrated circuit device according to the present invention comprises a shallow trench formed on the principal surface of a semiconductor substrate, an element isolation region having an insulating film, which contains a film planarized by the CMP method, embedded in the shallow trench, and active regions of the semiconductor integrated circuit element separated by said element isolation region, wherein dummy regions, which do not function as a semiconductor integrated circuit element, are formed on the principle surface of the semiconductor substrate in an empty space of the semiconductor substrate between said spaced active regions.

[0023] By providing such a semiconductor integrated circuit device with dummy interconnections or dummy regions formed in an empty space to prevent the formation of a sparse portion, the surface of the insulating film which covers the interconnections or the principal surface of the semiconductor substrate can therefore be planarized completely.

[0024] Described more specifically, in the case where only actual interconnections or active regions (element constituting members) are formed without dummy interconnections or dummy regions (dummy members), an empty space appears between adjacent but spaced element constituting members. If an insulating film is deposited without eliminating such an empty region, the surface of the insulating film near the empty region becomes uneven reflecting the shape of each of the element constituting members precisely. Such an uneven shape becomes a factor for inhibiting complete planarization, as illustrated in FIG. 29(d).

[0025] In accordance with the present invention, therefore, dummy members are disposed in such an empty region to ease the uneven shape of the insulating film, whereby the surface of the insulating film is planarized completely after polishing by the CMP method. The surface of the insulating film is planarized completely in this manner so that the process margin in the subsequent lithography step or etching step can be increased. As a result, the production yield of the semiconductor integrated circuit device can be improved and the starting time for the process can be shortened.

[0026] Incidentally, examples of the interconnection include a metal interconnection formed on an interlayer insulating film, a gate interconnection of a MISFET (Metal-Insulator-Semiconductor Field Effect Transistor) and a bit line of a DRAM (Dynamic Random Access Memory). It is needless to say that not only the interconnection of memory devices, such as a DRAM, but also the interconnection of logic devices, are included in the metal interconnection and gate interconnection. In particular, the logic device generally has a multilayer interconnection formed of at least three layers so that the application of the present invention to such an interconnection brings about marked effects.

[0027] (2) In another aspect, the semiconductor integrated circuit device according to the present invention contains a high-density member region which satisfies the conditions that the distance between adjacent members of the dummy interconnections and the actual interconnections, or between adjacent members of dummy regions and active regions, is set to at least the minimum space width which is required by the resolution power of lithography, and that said distance is set to at least twice the height of the interconnection or the depth of the shallow trench; and the area of the high-density member region is at least 95% of the whole chip area.

[0028] By setting the distance between the adjacent members of the dummy interconnections and the actual interconnections or between the adjacent members of the dummy regions and active regions at not greater than twice the height of the interconnections or depth of the shallow trench, there is no pattern dependence of the member pattern on the CMP polishing rate of the insulating film formed over such members, and the CMP polishing rate becomes uniform, which makes it possible to attain substantially complete surface flatness of the insulating film.

[0029]
FIG. 30 shows data indicating the finding of the present inventors obtained as a result of test and investigation and it graphically represents the fluctuation of a CMP polishing amount relative to the distance between dummy patterns. The distance between dummy patterns standardized by the height of the pattern is plotted along the abscissa, while the CMP polishing amount of the insulating film on the pattern relative to the standard pattern (solid pattern) is plotted along the ordinate. As is apparent from FIG. 30, the CMP polishing amount of the insulating film does not show a change even it the distance between the dummy patterns becomes approximately twice the height of the pattern. In other words, if the distance between the adjacent members of the dummy interconnections and the actual interconnections, or between the adjacent members of the dummy regions and active regions, is set at not greater than twice the height of the interconnection or the depth of the shallow bench, the CMP rate of the insulating film formed over such members becomes fixed irrespective of the pattern and the insulating film can be planarized completely.

[0030] In order to attain planarization over the whole chip, the region where complete planarization can be materialized, that is, the high-density member region preferably is as wide as possible, but it is not necessary for the whole area of the chip to be a high-density member region. A sufficiently flat surface suited for practical use can be obtained so long as the high-density member region permitting complete planarization occupies at least 95% of the chip area.

[0031] Another condition that the distance between these members is set at not less than the minimum space width required by the resolution power of lithography is established because a processing space exceeding the minimum processing size is necessary for favorable member processing. It is possible to carry out processing of the interconnections or dummy interconnections, or the active regions or dummy regions, by satisfying the above condition. Incidentally, when a KrF exima laser is used as an exposure source, 0.2 μm can be given as an example of the minimum space width.

[0032] Incidentally, in the remaining 5% region which is not a high-density member region, it is preferred that the distance between adjacent members of dummy interconnections and actual interconnections, or between adjacent members of the dummy regions and active regions, is set at not greater than four times the height of the interconnection or the depth of the shallow trench. The polishing amount of the insulating film in such a region where the pattern distance is set at not greater than four times the height of the interconnection or the depth of the shallow trench, that is, a low-density member region shows fluctuations about twice as much as that of the high-density member region, as is illustrated in FIG. 30. Because the area of the low-density member region is not larger than 5% of the chip area, however, the influence of the fluctuation can be neglected.

[0033] In addition, in the semiconductor integrated circuit device according to the present invention, the dummy interconnections or dummy regions each have a width not smaller than the minimum line width which is required by the resolution power of lithography, or has a length not smaller than twice the minimum line width; and at the same time, in the scribing area, the width and length of each of the dummy interconnections or dummy regions is not larger than the distance between bonding pads. Incidentally, the minimum space width and minimum line width can each be set at 0.2 μm, and the distance between bonding pads can be set at 10 μm.

[0034] According to such a semiconductor integrated circuit device, by setting the width of each of the dummy interconnections or dummy regions at not smaller then the minimum line width, which is required by the resolution power of lithography, the dummy interconnections or dummy regions can be processed with precision; and by setting the length of each of the dummy interconnections or dummy regions at not less than twice the minimum line width, the resolution of such members can be maintained with certainty. In other words, there is a potential problem that a pattern having the minimum processing size in width and length cannot be resolved accurately, but such a potential problem can be avoided in the case of the present invention by setting the length of each of the dummy interconnections or dummy regions at not less than twice the minimum processing size. The width or length of each of the dummy interconnections or dummy regions is set at 30 μm or less, with 20 μm or less being frequently used and with 10 μm or less being preferred.

[0035] In addition, by setting each of the width and length of the dummy interconnections or dummy regions at not greater than 30 μm, a parasitic capacitance of the interconnection and the like and also failure due to short circuits between the bonding pads can be reduced. Described specifically, an increase in the width or length of each of the dummy interconnections or dummy regions inevitably enlarges such dummy members, which increases the parasitic capacitance of the interconnection or the like functioning as a semiconductor integrated circuit element and impairs the performance of the semiconductor integrated circuit device, such as the high-speed responsiveness thereof. If the width or length is not greater than 30 μm, on the other hand, it is possible to suppress the parasitic capacitance of the interconnection or the like to an extent not causing a problem in practical use. When the dummy interconnections are disposed in a scribing area, there is a possibility that the scribed chips may become conductive dust. Even if they unfortunately become conductive dust, they cause a short-circuit only between bonding pads. So, by setting the width and length of each of the dummy interconnections at not greater than the distance between the bonding pads, the scribed chips do not cause a short circuit even if they become conductive dust. Owing to these advantages, deterioration in the performance and yield of the semiconductor integrated circuit device can be prevented.

[0036] In addition, in the semiconductor integrated circuit device according to the present invention, the dummy interconnections or dummy regions are formed also in the scribing area. According to such a semiconductor integrated circuit device, complete planarization can be maintained even in the scribing area, whereby complete planarization all over the wafer can be actualized.

[0037] In addition, in the semiconductor integrated circuit device according to the present invention, a pattern density of interconnections formed of the dummy interconnections and actual interconnections, or a pattern density of regions formed of the dummy regions and active regions, is made substantially uniform all over the regions on the semiconductor substrate.

[0038] Even by the semiconductor integrated circuit device as described above, complete planarization of the insulating film on these patterns can be actualized. Described more specifically, as indicated above, the existence of unevenness in the pattern density inhibits the flatness of the insulating film on the pattern. The evenness of the insulating film is therefore improved also by disposing dummy members so as not to cause unevenness in the pattern density.

[0039] (3) In a further aspect, the semiconductor integrated circuit device according to the present invention is similar to the above-described one except that, in the same interconnection layer which includes a bonding pad portion or marker portion for photolithography disposed on the semiconductor substrate, dummy interconnections are not formed at the periphery of the bonding pad portion or a marker portion.

[0040] Such a semiconductor integrated circuit device makes it possible to smoothly perform automatic detection of a bonding pad upon wire bonding and also automatic detection of a marker used for mask alignment during photolithography. Described more specifically, if dummy members made of the same material as that of the bonding pad or marker have been formed at the periphery thereof, there is a possibility that the dummy members will disturb, in the manner of a noise, the smooth detection of the bonding pad or marker. The present invention is free from such a possibility. Incidentally, it is possible that the dummy interconnections are not formed in a region 20 μm from the bonding pad portion or 60 μm from the marker portion.

[0041] In addition, the semiconductor integrated circuit device according to the present invention may contain, as the insulating film, a silicon oxide film formed by the SOG or high-density plasma CVD method, a BPSG (Boron-doped Phospho-Silicate Glass) or PSG (Phospho-Silicate Glass) film formed by the reflow method or a polysilazane film. According to such a semiconductor integrated circuit device, since the silicon oxide film formed by the SOG or high-density plasma CVD method, the BPSG or PSG film formed by the reflow method or the polysilazane film is excellent in step covering properties and has properties of embedding a concave portion therewith, a concave portion formed by adjacent members of the interconnections and dummy interconnections or of the active regions and dummy regions is filled in favorably with such a film, whereby the thickness of the insulating film to be polished by the CMP method can be decreased. Such a decrease in the thickness of the film to be polished by the CMP method leads to not only a reduction in the load of the deposition step of the film to be polished by the CMP method, but also a reduction in the load of the CMP step, which in turn brings about an improvement in the cost competitive advantage of the semiconductor integrated circuit device, for example, by reducing the process time.

[0042] The process for the fabrication of a semiconductor integrated circuit device according to the present invention is a process for the fabrication of the above-described semiconductor integrated circuit device, which comprises (a) depositing a conductive film containing polycrystalline silicon or a metal over the principal surface of a semiconductor substrate or over an interlayer insulating film and patterning said conductive film to form actual interconnections and dummy connections, (b) depositing a first insulating film, which is composed of a silicon oxide film formed by the SOG method or high-density plasma CVD method, a BPSG or PSG film formed by the re-flow method or a polysilazane film, over the actual interconnections and dummy interconnections including inner surfaces of concave portions formed by the actual interconnections and dummy interconnections and filling the concave portions with said film, (c) depositing a second insulating film over said first insulating film and (d) polishing the surface of said second insulating film by the CMP method; and wherein the second insulating film is formed to have a thickness sufficient for planarizing the unevenness on the surface of the first insulating film.

[0043] According to such a fabrication process of a semiconductor integrated circuit device, the second insulating film can be deposited to give a smaller film thickness, whereby the deposition time of the second insulating film can be shortened; and at the same time, the polishing amount of the second insulating film in the CMP polishing step can be reduced. As a result, in spite of the fact that the above process comprises conventional steps, the step time can be shortened and the step load can be reduced, which brings about an improvement in the cost competitive advantage in a semiconductor integrated circuit device.

[0044] Described more specifically, in the fabrication process according to the present invention, the concave portions formed between the actual interconnections and dummy interconnections are filled in with the first insulating film composed of a silicon oxide film formed by the SOG or high-density plasma CVD method, a BPSG or PSG film formed by the re-flow method or a polysilazane film, whereby the unevenness remaining on the surface of the second insulating film is lessened compared with the unevenness before the formation of the film. Accordingly, the thickness of the second insulting film must be sufficient for the planarization of the unevenness on the surface of the first insulating film, but the surface of the second insulating film can be planarized sufficiently even by a thin film.

[0045] (4) Incidentally, a rigid pad can be used for said CMP polishing. Alternatively, polishing by the CMP method can be employed only for the surface finish polishing after the unevenness on the surface attributable to the existence of the actual interconnections and dummy interconnections is substantially planarized by the first and second insulating films. As a polishing means employed for the surface finish, not only the CMP method, but also other polishing means, such as dry belt polishing and lapping, may be used.

[0046] The process for the fabrication of a semiconductor integrated circuit device according to the present invention is a process for the fabrication of the above-described semiconductor integrated circuit device, which comprises (a) depositing a silicon nitride film on the principal surface of a semiconductor substrate and patterning a portion of the silicon nitride film and semiconductor substrate in regions except for the active regions and dummy regions to form a shallow trench, (b) depositing an insulating film composed of a silicon oxide film on the semiconductor substrate, interconnections and silicon nitride film including the inner surface of the shallow trench, thereby filling in the trench with the insulating film, and (c) polishing the insulating film by the CMP method to expose the silicon nitride film.

[0047] According to the above-described fabrication process of a semiconductor integrated circuit device, dummy regions are formed also in an element isolation region so that dishing, that is, the formation of a recess, in the element isolation region can be prevented and the surface of the semiconductor substrate can be planarized completely. In addition, since the silicon nitride film having a lower CMP polishing rate than the silicon oxide film is formed between the insulating film, which is a film to be polished by the CMP method, and the active region of the semiconductor substrate, the silicon nitride film serves as a stopper layer for the CMP polishing and more complete flatness can be attained.

[0048] Incidentally, the above process may further comprise a step of using an alkaline slurry, which contains a silicon oxide as an abrasive, as the slurry used for the CMP method in the step (c) and subsequent to the step (c), etching of the insulating film formed in the shallow trench is performed through wet etching or dry etching to make the surface of the insulating film equal to or lower then the principal surface of the semiconductor substrate. When the alkaline slurry containing a silicon oxide as an abrasive is used, the ratio of the polishing rate of the silicon oxide film to the silicon nitride film becomes 3 or 4:1 so that it is necessary to thicken the silicon nitride film. In such a case, when the height of the principal surface of the semiconductor substrate, that is, the active region, and the height of the silicon oxide film, which is an element isolation region after the removal of the silicon nitride film, are compared, the silicon oxide film is found to be higher. The silicon oxide film is therefore etched by wet etching or dry etching to make the surface of the insulating film equal to or lower than the principal surface of the semiconductor substrate, whereby minute gate processing can be carried out.

[0049] Alternatively, a slurry containing cerium oxide as an abrasive can be used as the slurry in the CMP method in the step (c). In this case, the ratio of the polishing rate of the silicon oxide film to the silicon nitride film becomes 30 to 50:1 so that it is not necessary to thicken the silicon nitride film. The thickness of the silicon nitride film can be set to a value which is negligible in the process, for example, not greater than 50 nm so that the etching of the silicon oxide film subsequent to the removal of the silicon nitride film is not required.

[0050] (5) The method of designing a semiconductor integrated circuit device according to the present invention comprises forming a mask pattern for a mask used for the processing of members each constituting a semiconductor integrated circuit element, wherein said mask pattern includes a member pattern for members and a dummy pattern which is not disposed in a dummy placement prohibited region; and a mask pattern is formed so as to satisfy all of the following conditions: a first condition wherein a pattern distance between adjacent patterns of the member patterns and dummy patterns is not less than the minimum space width which is required by the resolution power of lithography, or not less than 0.2 μm; a second condition wherein the pattern distance is not greater then twice the height of the member in a region of at least 95% of the chip area, and in a region of at most 5% of the chip area, the pattern distance is not greater than four times the height of the member; a third condition wherein the width of the dummy pattern is at least the minimum line width which is required by the resolution power of lithography, or at least 0.2 μm; a fourth condition wherein the width of the dummy pattern is not greater than the distance between bonding pads disposed in the semiconductor integrated circuit device or not greater than 10 μm; a fifth condition wherein the length of the dummy pattern is not less than twice the minimum line width or not less than 0.2 μm; and a sixth condition wherein the length of the dummy pattern is not greater than the distance between the bonding pads or not less than 10 μm.

[0051] Such a method of designing a semiconductor integrated circuit device makes it possible to design a mask for member patterns necessary for the fabrication of said semiconductor integrated circuit device. By the above-described conditions, the advantages of the above-described semiconductor integrated circuit device can be actualized.

[0052] Incidentally, it is needless to say that the dummy pasterns can be disposed also in a scribing area of the semiconductor substrate. The dummy placement prohibited region can be set within a range of 20 μm from an end portion of the pattern to be a bonding pad, a range of 60 μm from an end portion of the pattern to be a marker for photolithography, a range of 0.5 μm from a region in which a contact hole is to be formed, or a fuse region. By setting the dummy placement prohibited region as described above, it becomes easier to detect the bonding pad or the marker for the mask alignment upon wire bonding or photolithography, which makes it possible to form a contact hole between the interconnections of different layers or a contact hole between the interconnection and the semiconductor substrate.

[0053] In the case of a metal interconnection wherein the member and the storage capacitative element which is to be formed above a bit line are formed in substantially the same layer, the dummy placement can be prohibited in a region which is to have a storage capacitative element thereon. In such a case, the first metal interconnection layer and the storage capacitative element of a DRAM can be formed in the same layer and dummy interconnections can be disposed in a region of the first metal interconnection layer.

[0054] In the case of the active region wherein members are formed on the principal surface of the semiconductor substrate, the placement of dummy regions can be prohibited in a region wherein a gate interconnection is formed on the principal surface of the semiconductor substrate. In such a case, since no dummy region is formed belong the gate interconnection, the capacitance between the gate interconnection and the semiconductor substrate can be reduced. Described more specifically, because the dummy regions on the principal surface of the semiconductor substrate and the active region of the semiconductor substrate apparently have the same structure, the formation of the gate interconnection on the dummy regions increases the capacitance of the gate interconnection. The dummy regions are therefore not formed below the gate interconnection, which brings about an improvement in the performance of the semiconductor integrated circuit device, such as the high-speed responsiveness thereof.

[0055] In addition, the method of designing a semiconductor integrated circuit device according to the present invention comprises disposing dummy patterns so as to minimize the floating capacitance of a member which will otherwise be increased by the dummy members formed by the dummy patterns, whereby the performance of the semiconductor integrated circuit device, such as the high-speed responsiveness thereof, can be improved. Incidentally, such disposal of elements can be effected by satisfying the above-described conditions for the method of designing a semiconductor integrated circuit device and then, optimizing the dummy patterns so as to minimize the area and the number of the dummy patterns. Such optimization can be calculated automatically by an information processor such as computer which forms a layout pattern.

BRIEF DESCRIPTION OF THE DRAWINGS

[0056]
FIG. 1 is a cross-sectional view illustrating one example of a logic integrated circuit device according to Embodiment 1 of the semiconductor integrated circuit device of the present invention;

[0057]
FIG. 2 is a fragmentary plan view illustrating the layout of the interconnections and dummy interconnections in the first interconnection layer in FIG. 1;

[0058]
FIG. 3(b) is a plan view illustrating a layout rule applied to the layout of the interconnections and dummy interconnections and FIG. 3(a) is a cross-sectional view taken along a line A-A of FIG. 3(-b);

[0059]
FIG. 4 is a cross-sectional view illustrating an enlarged interconnection portion in FIG. 1;

[0060]
FIG. 5 is a cross-sectional view illustrating one example of the fabrication process of the logic integrated circuit device according to Embodiment 1 in the order of the steps;

[0061]
FIG. 6 is a cross-sectional view illustrating one example of the fabrication process of the logic integrated circuit device according to Embodiment 1 in the order of the steps;

[0062]
FIG. 7 is a cross-sectional view illustrating one example of the fabrication process of the logic integrated circuit device according to Embodiment 1 in the order of the steps;

[0063]
FIG. 8 is a cross-sectional view illustrating one example of the fabrication process of the logic integrated circuit device according to Embodiment 1 in the order of the steps;

[0064]
FIG. 9 is a cross-sectional view illustrating one example of the fabrication process of the logic integrated circuit device according to Embodiment 1 in the order of the steps;

[0065]
FIG. 10 is a cross-sectional view illustrating one example of the fabrication process of the logic integrated circuit device according to Embodiment 1 in the order of the steps;

[0066]
FIG. 11 is a cross-sectional view illustrating one example of the fabrication process of the logic integrated circuit device according to Embodiment 1 in the order of the steps;

[0067]
FIG. 12 is a cross-sectional view illustrating one example of a logic integrated circuit device according to Embodiment 2;

[0068]
FIG. 13 is a plan view illustrating a layout of interconnections and dummy interconnections in the fifth interconnection layer;

[0069]
FIG. 14 is a cross-sectional view illustrating one example of a logic integrated circuit device according to Embodiment 3 of the present invention;

[0070] FIGS. 15(a) and (b) are each a plan view illustrating another example of the logic integrated circuit device according to Embodiment 3;

[0071]
FIG. 16 is a cross-sectional view illustrating one example of DRAM according to Embodiment 3;

[0072]
FIG. 17 is a graph illustrating a relationship between a pattern size and focus depth of lithography;

[0073]
FIG. 18 is a cross-sectional view illustrating one example of the fabrication process of DRAM according to Embodiment 3 in the order of the steps;

[0074]
FIG. 19 is a cross-sectional view illustrating one example of the fabrication process of DRAM according to Embodiment 3 in the order of the steps;

[0075]
FIG. 20 is a cross-sectional view illustrating one example of the fabrication process of DRAM according to Embodiment 3 in the order of the steps;

[0076]
FIG. 21 is a cross-sectional view illustrating one example of the fabrication process of DRAM according to Embodiment 3 in the order of the steps;

[0077]
FIG. 22 is a cross-sectional view illustrating one example of a fabrication process of DRAM according to Embodiment 3 in the order of the steps;

[0078]
FIG. 23 is a cross-sectional view illustrating one example of a semiconductor integrated circuit device according to Embodiment 4;

[0079]
FIG. 24 is a plan view illustrating one example of the semiconductor integrated circuit device according to Embodiment 4;

[0080]
FIG. 25 is a cross-sectional view illustrating one example of the semiconductor integrated circuit device according to Embodiment 4 in the order of the steps;

[0081]
FIG. 26 is a cross-sectional view illustrating one example of the semiconductor integrated circuit device according to Embodiment 4 in the order of the steps;

[0082]
FIG. 27 is a cross-sectional view illustrating one example of the semiconductor integrated circuit device according to Embodiment 4 in the order of the steps;

[0083]
FIG. 28 is a cross-sectional view illustrating one example of the semiconductor integrated circuit device according to Embodiment 4 in the order of the steps;

[0084] FIGS. 29(a) to 29(d) are each a cross-sectional view illustrating planarization technique by the CMP method investigated by the present inventors;

[0085]
FIG. 30 is a graph illustrating the fluctuations of CMP polishing amount relative to the distance between patterns;

[0086]
FIG. 31 is a plan view illustrating one example of the semiconductor integrated circuit device according to Embodiment 4 of the present invention;

[0087]
FIG. 32 is a cross-sectional view illustrating one example of a semiconductor integrated circuit device according to Embodiment 5 of the present invention;

[0088]
FIG. 33 is a fragmentary plan view of the semiconductor integrated circuit device of FIG. 32; and

[0089]
FIG. 34 is a fragmentary plan view of the semiconductor integrated circuit device of FIG. 32

EMBODIMENTS OF THE PRESENT INVENTION

[0090] The embodiments of the present invention will next be described in detail with reference to accompanying drawings. Incidentally, in each of the drawings illustrating the following embodiments, like elements will be identified by like reference numerals and overlapping descriptions will be omitted.

[0091] (Embodiment 1)

[0092]
FIG. 1 is a cross-sectional view illustrating one example of a logic integrated circuit device according to Embodiment 1 of the semiconductor integrated circuit device of the present invention. In FIG. 1, a scribing area A, a pad and peripheral circuit region B and a logic circuit region C of the semiconductor integrated circuit device are illustrated.

[0093] In the logic integrated circuit device according to Embodiment 1, a shallow trench 2 is formed on the principal surface of the semiconductor substrate 1, and in the shallow trench 2 a silicon oxide film, which is an insulating film, is embedded, whereby an element isolation region 3 is formed. By this element isolation region 3, an active region 4 formed on the principal surface of the semiconductor substrate 1 is defined. Incidentally, as an element isolation structure, a shallow trench is exemplified here, but a field insulating film formed by the LOCOS (Local Oxidation of Silicon) method may be employed as well. Although not illustrated here, P-type and N-type well regions may be formed on the principal surface of the semiconductor substrate.

[0094] In the active region 4, a MISFET is formed. On the principal surface of the semiconductor substrate, a gate interconnection 6 is formed via a gate insulating film 5 of the MISFET. The gate insulating film 5 maybe, for example, a silicon oxide film formed by thermal oxidation, while the gate interconnection 6 may be, for example, a polycrystalline silicon film formed by the CVD method. On the surface of the polycrystalline silicon film, a silicide film is formed in order to reduce the electrical resistance.

[0095] A portion of the gate interconnection 6 is formed to extend over the element separation region 3 and another portion is formed to be a gate electrode 7 of a MISFETQ1 formed in the active region 4 of the semiconductor substrate 1. On both sides of the gate electrode 7 in the active regions 4 on the principal surface of the semiconductor substrate 1, impurity semiconductor regions 8 are formed. The impurity semiconductor regions 8 function as a source drain region for the MISFETQ1. It is also possible to employ the region 8 as a so-called LDD (Lightly Doped Drain). On the side of the gate interconnection 6, a side wall spacer 8b is formed. The side wall spacer 8b can be formed of a silicon oxide film or a silicon nitride film.

[0096] The MISFETQ1 formed in the logic circuit region C functions as an active device for the logic circuit. Although not illustrated in FIG. 1, the MISFET formed in the pad and peripheral circuit region B functions as an active device for the peripheral circuit. Incidentally, the MISFET is exemplified as a transistor formed in the logic circuit region C and pad and peripheral circuit region B, but a bipolar transistor or Bi-CMOS transistor can also be employed.

[0097] The gate interconnection 6 is covered with an interlayer insulating film 9, over which interconnections 10 and dummy interconnections 11 are formed in the first interconnection layer. The interlayer insulating film 9 can be formed, for example, of a PSG film, BPSG film or a silicon oxide film such as SOG film. Alternatively, a lamination film with a TEOS silicon oxide film can be used for the prevention of diffusion of impurities. It is preferred that the surface of the interlayer insulating film 9 has been planarized by the CMP method or etchback method.

[0098] The interconnection 10 and dummy interconnection 11 are made of the same material and formed by the same step (same layer). Examples of the material include metals, such as aluminum (Al) and copper (Cu). They may alternatively be made of a polycrystalline silicon film doped with impurities at a high concentration. In the case of the polycrystalline silicon film, the surface thereof may be converted into a silicide.

[0099]
FIG. 2 is a plan view illustrating the layout of the interconnections 10 and dummy interconnections 11 in the first layer. The dummy interconnections 11 are formed in a region (void region) where the space between adjacent interconnections 10 is wide. As a result, the dummy interconnections are placed evenly in a region where the interconnections 10 have not been disposed, the space between the adjacent members of the dummy interconnections 11 and interconnections 10 becomes narrow; and the dummy interconnections seem to be filled in the void region densely.

[0100] The dummy interconnections 11 are formed also in the scribing area A, whereby the flatness of an insulating film 12 is maintained all over the semiconductor substrate 1, which will be described later. The width and length of the dummy interconnection 11 formed in the scribing area A are constituted so as to be not greater than the distance between the bonding pads.

[0101]
FIG. 3(b) is a plan view illustrating a layout rule applied to the placement of the interconnections 10 and the dummy interconnections 11, and FIG. 3(a) is a cross-sectional view taken along a line A-A of FIG. 3(b).

[0102] The member space S, which is a space between the interconnection 10 and the dummy interconnection 11, or a space between adjacent dummy interconnections 11, is not greater than twice the height of the interconnection height H of the dummy interconnection 11 or interconnection 10. As described above with reference to FIG. 30, by setting the member space S at not greater than twice the interconnection height H, the CMP polishing amount of the insulating film 12 can be made uniform and the surface of the insulating film 12 can be completely planarized. In a region not wider than 5% of the chip area, the member space S is allowed to have a height of at most four times the interconnection height H. In this case, although the fluctuations of the polishing amount of the insulating film 12 increase about twice, they can be neglected as a whole because this area amounts to not greater than 5% of the chip area. The flatness of the whole insulating film 12 therefore can be substantially maintained.

[0103] In addition, as the member space S, a space not smaller than the minimum space width required by a lithographic tool is necessary. This condition permits accurate processing of the interconnection 10 and dummy interconnection 11, whereby each member can be processed accurately according to the design. In the case of an exposure apparatus using a KRF exima laser as a light source, 0.2 μm can be given as an example of the minimum space width.

[0104] The width (a) of the dummy interconnection 11 is set to be not smaller than the minimum line width required by a lithographic tool. By setting the width (a) to be not smaller than the minimum line width, the dummy interconnections 11 can be processed with certainty. In the scribing area, the width (a) of each of the dummy interconnections 11 is set at not greater than the distance between bonding pads 13. By doing so, even if the dummy interconnections 11 are peeled off into minute chips by dicing or the like and produce conductive dust, no short circuit occurs between the bonding pads 13, which makes it possible to eliminate a cause for possible failure. The width (a) of each of the dummy interconnections 11 is set to be, for example, not greater than 30 μm, with 20 μm being frequently employed and with 10 μm being preferred. The distance between the bonding pads 13 can be set at about 10 μm. Even if the dummy interconnections 11 of such a size are formed, the parasitic capacitance of the interconnection 10 does not increase and therefore does not cause a problem of retarding a signal transferred to the interconnection 10. As a result, the performance of the logic integrated circuit device is not deteriorated.

[0105] The length (b) of each of the dummy interconnections 11 is set at not less than twice the minimum line width, and in the scribing area, it is set at not greater than the distance between the bonding pads, for example, not greater than 10 μm. When the width (b) and length (a) of each of the dummy interconnections 11 are each set at the minimum line width, there is a possibility that proper resolution of the dummy interconnections 11 will not be attained. By setting the length (b) at least twice the minimum line width, the resolution of the dummy interconnections 11 can be carried out with certainty even if the width (a) is the minimum line width, which makes it possible to process it with certainty. For the same reason in the width (a), the length (b) is set at, for example, not greater than the distance between bonding pads, for example, not greater than 10 μm. Similar to the width (a), the length (b) of each of the dummy interconnections 11 is constituted at not greater than 30 μm, with 20 μm or less being frequently employed and with 10 μm or less being preferred.

[0106] In Embodiment 1, the dummy interconnections 11 are in a rectangular form, but may be in a triangular, trapezoidal, circular or another polygonal form so long as they satisfy the above-described conditions. For minimizing the parasitic capacitance of the interconnection 10, the size and number of the dummy interconnections 11 are each preferred to be as small as possible. For minimizing the parasitic capacitance of the interconnection 10 within a range satisfying the above-described conditions, it is most preferred to set the member space S at twice the interconnection height H, the width (a) of each of the dummy interconnections at the minimum line width and the length (b) of each of the dummy interconnections at not less than twice the minimum line width. In this Embodiment, for example, the dummy interconnections are constituted to have a width (a) of 0.6 to 1 μm and a length (b) of 10 to 25 μm.

[0107] The interconnections 10 and dummy interconnections 11 are covered with the insulating film 12. The surface of the insulating film 12 has been polished by the CMP method so that the film has a completely planarized surface.

[0108]
FIG. 4 is an enlarged cross-sectional view of the interconnection portion of FIG. 1. The insulating film 12 has an insulating film 12a, an insulating film 12b, an insulating film 12c and an insulating film 12d laminated in this order from the side contiguous to the interconnection 10 and dummy interconnection 11.

[0109] As the insulating film 12a, a silicon oxide film formed by the CVD method using TEOS can be employed for example. As illustrated in the drawing, the insulating film 12a is formed, faithfully tracing the surface line including a step difference. The film thickness can be set, for example, at 300 nm.

[0110] As the insulating film 12b, an inorganic SOG film, a silicon oxide film formed by the high-density plasma CVD method or a polysilazane film can be employed. In short, a film having properties for filling a concave portion therewith can be employed. As illustrated in the drawing, the film is embedded in the concave portion and the thickness of the film in the convex portion is formed to be thin. The reason why the concave portion can be embedded with the insulating film 12b is because the above-described dummy interconnections 11 are formed under the above-described conditions and the concave portion formed between adjacent dummy interconnections 11 is not greater than a given space necessary for embedding the insulating film 12b. The film thickness is for example set at 125 nm on the convex portion.

[0111] As the insulating film 12c, for example, a silicon oxide film formed by the CVD method using TEOS can be employed, with its surface being polished by the CMP method. The existence of the dummy interconnections 11 has enabled complete planarization of the polished surface. This film can be formed to give a thickness of 500 nm on the convex portion.

[0112] As the insulating film 12d, a silicon oxide film formed by the CVD method using TEOS can be employed. It has, for example, a film thickness of 200 nm. Incidentally, the insulating film 12d can be omitted. In such a case, it is necessary to add the thickness of the insulating film 12d to the thickness of the insulating film 12c upon deposition of the insulating film 12c.

[0113] Over the insulating film 12, interconnections 14, dummy interconnections 15 and an insulating film 16 of the second interconnection layer are formed, over which interconnections 17, dummy interconnections 18 and an insulating film 19 of the third interconnection layer are formed and then, interconnections 20, dummy interconnections 21 and an insulating film 22 are formed. The interconnections 14, 17 and 20, dummy interconnections 15, 18 and 21 and insulating films 16, 19 and 22 are formed similarly to the interconnection 10, dummy interconnection 11 and insulating film 12 of the first interconnection layer, respectively.

[0114] Over the fourth interconnection layer, interconnections 23 and an insulating film 24 of the fifth interconnection layer are formed, followed by the formation of a passivation film 25. As the passivation film 25, for example, a silicon nitride film can be employed. The interconnections 23 include the bonding pad 13.

[0115] A process for the fabrication of the logic integrated circuit device of Embodiment 1 will next be described with reference to FIGS. 5 to 11, which are cross-sectional views illustrating one example of the fabrication process of the logic integrated circuit device of Embodiment 1 in the order of the steps thereof.

[0116] As illustrated in FIG. 5, on a semiconductor substrate 1, a shallow trench 2 is formed using photolithography and etching techniques. On the principal surface of the semiconductor substrate 1 having the shallow trench 2 formed therein, a silicon oxide film is deposited, and then, it is polished by the CMP method or the like to form an element isolation region 3. Then, N-type and P-type well regions may be formed.

[0117] As illustrated in FIG. 6, a silicon oxide film to be a gate insulating film 5 is then formed by the thermal oxidation or thermal CVD method, followed by the deposition of a polycrystalline silicon film by the CVD method. The polycrystalline silicon film is patterned using photolithography and etching techniques, whereby a gate interconnection 6 (gate electrode 7) is formed. With the gate electrode 7 serving as a mask, impurities are subjected to ion implantation in self alignment relative to the gate electrode 7, whereby an impurity semiconductor region 8 is formed. After the deposition of a silicon oxide film, anisotropic etching is conducted, whereby a side-wall spacer 8b is formed. It is possible to carry out ion implantation of highly-concentrated impurities to form the impurity semiconductor region 8 as a so-called LDD structure.

[0118] As illustrated in FIG. 7, a PSG film is formed, followed by planarization by the etchback or CMP method, whereby an interlayer insulating film 9 is formed. Over the interlayer insulating film, an aluminum film is deposited by the sputtering or deposition method. The aluminum film so obtained is patterned by photolithography and etching techniques, whereby interconnections 10 and dummy interconnections 11 are formed. Patterning is conducted in accordance with the conditions as described above with regards to the dummy interconnections 11.

[0119] As illustrated in FIG. 8, an insulating film 12a is formed by the CVD method using TEOS. As the CVD method, a plasma CVD method can be employed, but a thermal CVD method using ozone in combination can be employed alternatively. The film thickness of the insulating film 12a is set at 300 nm. Incidentally, FIGS. 8 to 11 are cross-sectional views each illustrating only an interconnection layer and the layers therebelow are omitted.

[0120] Then, an insulating film 12b is formed using an inorganic SOG film and gaps formed by adjacent ones of the interconnections 10 and dummy interconnections 11 are filled therewith. The inorganic SOG film can be formed by coating inorganic SOG and then baking it. The film thickness of the insulating film 12b is set at 125 nm on the convex portion. Incidentally, the insulating film 12b may be a silicon oxide film formed by the high-density plasma CVD method or a polysilazane film.

[0121] Since the width of the gap is narrow owing to the formation of the dummy interconnections 11, it becomes possible to embed the gap with the insulating film 12b favorably. In other words, the film thickness in the concave portion is made thicker than that on the convex portion. As a result, the unevenness on the surface of the insulating film 12b is lessened and the difference in the height can be reduced.

[0122] As illustrated in FIG. 9, an insulating film 12c is then formed by the CVD method using TEOS. The insulating film 12 can be formed to have a film thickness of 700 nm. In the case where no dummy interconnection is disposed as is illustrated in FIG. 29, the thickness of the insulating film 12c is required to be about 1700 nm, but in Embodiment 1, the thickness can be decreased to 700 nm because of the presence of the dummy interconnections 11. As a result, the step for deposition the insulating film 12 can be shortened, whereby the step load can be reduced.

[0123] As illustrated in FIG. 10, the surface of the insulating film 12c is then polished by the CMP method and planarized. In Embodiment 1, the surface shape of the insulating film 12c reflects the shapes of the interconnections 10 and dummy interconnections 11, as well as that of the insulating film 12b, so that the insulating film 12c has substantially an even height at any place. As a result, the polishing rate becomes substantially uniform irrespective of the locations, whereby the surface of the insulating film 12c can be substantially planarized. In addition, the insulating film 12c has a film thickness as little as 700 nm, which makes it possible to reduce the CMP polishing amount and to reduce the load of the CMP polishing step. Incidentally, the polishing amount can be decreased to 200 nm.

[0124] Then, a surface washing after CMP polishing is effected, followed by the formation of an insulating film 12d by the CVD method using TEOS, as is illustrated in FIG. 11. The insulating film 12d can be formed to have a thickness of 200 nm. Incidentally, it is possible to omit the insulating film 12d and to form the insulating film 12cto have a thickness of 900 nm.

[0125] In this manner, the first interconnection layer is completed. Similar to the first interconnection layer, the second to fourth interconnection layers are then formed, followed by the formation of the fifth interconnection layer similarly. Over the fifth interconnection layer, a passivation film 25 is formed, whereby the logic integrated circuit device as illustrated in FIG. 1 is almost completed.

[0126] According to the fabrication process of Embodiment 1, the surfaces of the insulating films 12, 16, 19 and 22 are completely planarized and at the same time, the step for deposition of an insulating film to be polished by CMP and CMP polishing step can be shortened, whereby step loads can be reduced. In general, such an advantage becomes particularly marked when a multi-layer interconnection, such as a logic device, composed of at least 3 layers is formed.

[0127] Incidentally, an interconnection layer composed of five layers is exemplified in this Embodiment 1, however, it may be formed of any number of layers either greater or less than five layers.

[0128] (Embodiment 2)

[0129]
FIG. 12 is a cross-sectional view illustrating one example of a logic integrated circuit device according to Embodiment 2 of the present invention.

[0130] The logic integrated circuit device according to Embodiment 2 is substantially similar to that of Embodiment 1 except for the fifth interconnection layer. Accordingly, a description of the common features is omitted herein and only the differences will be described below.

[0131] The logic integrated circuit device according to Embodiment 2 has, in the fifth interconnection layer, dummy interconnections 26 in addition to interconnections 23. The dummy interconnections 26 are disposed under substantially similar conditions to the dummy interconnections 11 described in Embodiment 1. The interconnections 23 of the fifth interconnection layer however include the bonding pad 13 so that the disposing conditions of the dummy interconnections 26 are different at the periphery of the bonding pad 13.

[0132]
FIG. 13 is a plan view illustrating the layout of the interconnections 23 and the dummy interconnections 26 of the fifth interconnection layer. At the periphery of the bonding pad 13, a prohibited area 27 free from dummy interconnections 26 is disposed. The prohibited area 27 can extend within a range of 20 μm from each end of the bonding pad 13.

[0133] Such a logic integrated circuit device makes it possible to completely planarize also the surface of the passivation film 25, because the dummy interconnections 26 are formed in the fifth interconnection layer. As a result, it becomes possible to carry out processing of a BLM (Ball Limiting Metalization) film 29, which is to be an underground film for a bump 28, as illustrated in FIG. 14. In addition, by disposing the prohibited area 27 at the periphery of the bonding pad 13, automatic detection of the bonding pad 13 by a wire bonding apparatus can be conducted with certainty.

[0134] Incidentally, in the present Embodiment 2 and also the above-described Embodiment 1, the dummy interconnections 11, 15, 18, 21 and 26 can be formed in the scribing area A. When markers 30a and 30b for lithography are formed, as illustrated in FIGS. 15(a) and 15(b), respectively, in the scribing area A or another area, prohibited areas 31a and 31b free from the placement of the dummy interconnections 11, 15, 18, 21 or 26 can be disposed in the vicinity of the markers. The prohibited area 31a or 31b can be disposed within a range of 60 μm from each end of the marker 30a or 30b.

[0135] By disposing such a prohibited area 31a or 31b, it becomes possible to carry out automatic detection of the marker 30a or 30b favorably by an exposure apparatus used for photolithography. Incidentally, the prohibited area 31a or 31b is formed for at least the dummy interconnections 26 of the uppermost interconnection layer, and it is not necessary to apply it to the dummy interconnections 11, 15 and 18 in the lower interconnection layers. Alternatively, it is not necessary to dispose the dummy interconnections themselves.

[0136] (Embodiment 3)

[0137]
FIG. 16 is a cross-sectional view illustrating one example of a DRAM which represents Embodiment 3 of the present invention.

[0138] A semiconductor substrate 1, a shallow trench 2, an element isolation region 3 and an active region 4 of DRAM according to Embodiment 3 are similar to those of Embodiment 1. On the principal surface of the semiconductor substrate 1, a p-type well region 32 and an n-type well region 33 are formed.

[0139] In the active region 4 of the p-type well region 32, a selective MISFETQt constituting a memory cell M of the DRAM and a MISFETQn of a peripheral circuit are formed, while in the active region 4 of the n-type well region 33, MISFETQP of the peripheral circuit is formed. In FIG. 16, shown on the left side is a memory cell area, while on the center and right side, a peripheral circuit area is shown. The memory cell M of the DRAM has a selective MISFETQt and a storage element SN which is a capacitative element.

[0140] Gate electrodes 7 for MISFETQt, MISFETQn and MISFETQp are each formed of a polycrystalline silicon film, said film having a silicide layer 7a on the surface thereof. In the active region 4 existing on both sides of the gate electrode 7 for MISFETQt, MISFETQn or MISFETQp, impurity semiconductor regions 8 are formed and constitute a source and drain region of the MISFET. The conductivity type of the impurity semiconductor region 8 differs depending on the conductivity type of the MISFET. The MISFETQt and the MISFETQn have an n-type conductivity, while the MISFETQp has a p-type conductivity. Incidentally, concerning the MISFETQn and MISFETQP of the peripheral circuit, the impurity semiconductor regions 8 are illustrated to have an LDD structure, but it is not necessary that they have an LDD structure.

[0141] In the layer where the gate electrodes 7 exist, gate interconnections 6 and dummy gate interconnections (dummy members) 34 are formed. The gate electrodes 7 are also part of the gate interconnections 6. Since the gate interconnections 6 and dummy gate interconnections 34 are formed simultaneously with the gate electrodes 7 (in the same layer), silicide layers 6a and 34a are formed on the surfaces thereof. On the side walls and upper surfaces of the gate interconnections 6 and dummy gate interconnections 34, side walls 8b and cap insulating films 8c, each formed of a silicon oxide film, are formed, over which an insulating film 35 is formed. The insulating film 35 may be formed of, for example, a TEOS silicon oxide film. Over the insulating film 35, an insulating film 36 planarized by the CMP method is formed. The insulating film 36 may be formed, for example, of a BPSG film. In Embodiment 3, dummy gate interconnections 34 are disposed so that the insulating film 36 can be almost completely planarized. Even if the focus depth of the lithography becomes shallow, such complete planarization makes it possible to mass produce the products, on which minute patterns on the level of 0.2 μm have been formed, as illustrated by FIG. 17.

[0142] The dummy gate interconnections 34 are disposed under similar conditions to those for the dummy interconnections 11 described in Embodiment 1. Incidentally, the dummy gate interconnections 34 are not disposed in a region where a contact hole is to be formed, which makes it possible to open the contact hole smoothly. The dummy gate interconnections 34 are formed mainly on the element isolation region 3.

[0143] Over the insulating film 36, an insulating film 37 composed of, for example, a silicon oxide film formed using TEOS can be formed. Alternatively, it can be omitted.

[0144] Over the insulting film 37, in addition to the bit line 38 of the DRAM, interconnections 39 and dummy interconnections 40, which are formed in the same layer with the bit line, are formed. These interconnections can be composed of a polycrystalline silicon film having, for example, a CVD tungsten film as an adhesive layer. The dummy interconnections 40 are formed in accordance with the conditions employed for the above-described dummy interconnections 11 of Embodiment 1. However, they are not disposed in a region having a contact hole formed therein, whereby the contact hole can be opened smoothly. On the side walls and upper surfaces of the bit line 38, interconnection 39 and dummy interconnection 40, side walls 41b and cap insulating film 41c, each composed of a silicon oxide film, are formed, over which an insulating film 42 is laid. The insulating film 42 is composed of, for example, a BPSG film which has been polished by the CMP method for planarization. Incidentally, an insulating film 43 composed of a silicon oxide film formed using TEOS can be formed over the insulating film 42, but alternatively, it can be omitted. In this Embodiment 3, the dummy interconnections 40 are disposed, which makes it possible to planarize the insulating film 42 almost completely.

[0145] Over the insulating film 43, a storage capacitative element SN of the DRAM and a first metal interconnection layer are formed. The storage capacitative element SN is constituted of a lower electrode 45 which is connected with the impurity semiconductor region 8 of a MISFETQt through a plug 44, and a plate electrode 47 formed opposite to the lower electrode 45 through a capacitative insulating film 46. The storage capacitative element SN is covered with an insulating film 48. It is also covered with an insulating film 49 composed of a silicon oxide film formed, for example, by the high-density plasma method. Over the insulating film 49, the interconnections 50 and dummy interconnections 51 of the first interconnection layer are formed. Each of the interconnections 50 is connected through the contact hole with a plate electrode 47 or an impurity semiconductor region 8 on the principal surface of the semiconductor substrate 1. The interconnections 50 and dummy interconnections 51 are formed simultaneously, and they are composed of, for example, a tungsten film having as an adhesive layer CVD tungsten or an aluminum film. The dummy interconnections 51 are disposed under similar conditions to those described in Embodiment 1 with regard to the dummy interconnections 11. However, they are not disposed in a memory mat region in which the storage capacitative element SN is to be formed.

[0146] The interconnections 50 and dummy interconnections 51 are covered with an insulating film 52 composed of, for example, a silicon oxide film formed by the high-density plasma CVD method or a polysilazane film. Over the insulating film 52, an insulating film 53 composed of a TEOS silicon oxide film is formed. The insulating film 53 is polished by the CMP method and planarized. It has almost complete flatness because of having therebelow the dummy interconnections 51.

[0147] The insulating film 53 is overlaid with interconnections 54, dummy interconnections 55 and an insulating film 56 of the second layer, followed by the formation of the interconnections 57, dummy interconnections 58 and an insulating film 59 of the third layer. The interconnections 54, dummy interconnections 55, insulating film 56, interconnections 57, dummy interconnections 58 and insulating film 59 are formed in a similar manner to the interconnections 10, dummy interconnections 11 and insulating film 12 in Embodiment 1.

[0148] The DRAM according to Embodiment 3 makes it possible to provide each insulating film with complete flatness because dummy members 34, 40, 51, 55 and 58 are disposed for the gate interconnections 6, bit line 38, interconnections 50 of the first layer, interconnections 54 of the second layer and interconnections 57 of the third layer. By disposing the dummy gate interconnections 34 and dummy interconnections 40, 51, 55 and 58 between the memory cell region and peripheral circuit area, the insulating film of each layer can be planarized.

[0149] Incidentally, the process for the fabrication of the DRAM of Embodiment 3 will next be described with reference to FIGS. 18 to 21. FIGS. 18 to 21 are cross-sectional views each illustrating one example of the fabrication process of the DRAM of Embodiment 3 in the order of the steps thereof.

[0150] The steps leading up to the formation of the element isolation region 3 on the principal surface of the semiconductor substrate 1 are similar to those of Embodiment 1 so that their description will be omitted.

[0151] Then, as illustrated in FIG. 18, a silicon oxide film, which will be a gate insulating film 5, is formed, followed by the deposition thereon of a polycrystalline silicon film to be a gate interconnection 6, gate electrode 7 and dummy gate interconnection 34, and then a silicon oxide film which will be formed as a cap insulating film 8c. These films so laminated are patterned, whereby the gate interconnection 6, gate electrode 7 and dummy gate interconnection 34 are formed. The gate interconnection 6 (gate electrode 7) is patterned in accordance with an ordinarily employed layout rule, while the dummy gate interconnection 34 is patterned so as to be disposed in the element isolation region 3, while substantially satisfying, in addition to the ordinarily employed layout rule, the conditions in Embodiment 1 concerning the dummy interconnection 11.

[0152] Then, as illustrated in FIG. 19, a side-wall spacer 8b is formed, followed by the deposition of an insulating film 35 and then a BPSG film. The BPSG film is thereafter polished by the CMP method, whereby an insulating film 36 is formed. The BPSG film can be formed to give a thickness of 800 nm and the CMP polishing amount can be suppressed to 400 nm. When the dummy gate interconnections 34 are not formed, it is necessary to deposit a thicker BPSG film and the CMP polishing amount inevitably increases. As described above, by decreasing the thickness of the BPSG film and reducing the CMP polishing amount, advantages such as reduction in the step load can be brought about. Incidentally, instead of the BPSG film, a PSG film or a silicon oxide film formed by the high-density plasma CVD method can be employed. Also, the side wall spacer 8b and the cap insulating film 8c can each be formed of a silicon nitride film, instead. When the silicon nitride film is used, etching upon the opening of a contact hole can be carried out by self alignment.

[0153] As illustrated in FIG. 20, subsequent to the washing after the CMP polishing, an insulating film 37 is deposited to a thickness of 100 nm. It is also possible to omit the insulating film 37. Then, a plug 44 to be connected with a bit line 38 and a lower electrode 45 of a storage capacitative element SN are formed, followed by the formation of the bit line 38, interconnections 39 and dummy interconnections 40. The dummy interconnections 40 are disposed under similar conditions to those for the dummy interconnections 11 of Embodiment 1. Then, a side wall 41b and a cap insulating film 41c are formed and a BPSG film is deposited thereon, followed by polishing of the BPSG film by the CMP method, whereby an insulating film 42 is formed. Incidentally, instead of the BPSG film, a PSG film or a silicon oxide film formed by the high-density plasma CVD method can be employed. Since the dummy interconnections 40 have been formed, the insulating film 42 is able to have a completely planarized surface and at the same time, it is possible to decrease the thickness of the BPSG film and reduce the CMP polishing amount. Then, washing is effected after the CMP polishing, followed by the deposition of an insulating film 43 by the plasma CVD method using TEOS or the like method. It is also possible to omit this insulating film 43.

[0154] Then, as illustrated in FIG. 21, a storage capacitive element SN is formed and a BPSG film is deposited thereon, followed by a baking treatment, whereby an insulating film 49 is formed. The insulating film 49 can be formed to a thickness of 500 nm. Subsequent to the opening of a contact hole, a tungsten film to be a first interconnection layer is formed by the CVD method, followed by the formation of an aluminum film by the sputtering method. Then, the resulting aluminum and tungsten films are patterned, whereby interconnections 50 and dummy interconnections 51 are formed. The dummy interconnections 51 are disposed under similar conditions to those for the dummy interconnections 11, and in addition, it is a condition that the dummy interconnections 51 are not disposed in a memory mat region where the storage capacitative device is disposed. FIG. 22 is a plan view illustrating the above conditions. A BPSG film is then deposited to form an insulating film 52. A TEOS silicon oxide film is deposited thereover, followed by polishing by the CMP method, whereby an insulating film 53 is formed. Instead of the BPSG film, a PSG film or a silicon oxide film formed by the high-density plasma CVD method can be employed. Here, the formation of the dummy interconnections 51 makes it possible to completely planarize the surface of the insulating film 53 and, at the same time, to decrease the thickness of the TEOS silicon oxide film and reduce the CMP polishing amount.

[0155] In a similar manner to Embodiment 1, second and third interconnection layers are then formed, whereby the DRAM of Embodiment 3 is almost completed. According to the fabrication process of Embodiment 3, the complete planarization of the insulating film of each of the layers can be attained and at the same time, the step load can be reduced.

[0156] Also in this Embodiment 3, dummy members can be disposed in the scribing area, but not at the peripheries of the bonding pad and marker, as illustrated in connection with Embodiments 1 or 2. In addition, it is possible to not dispose the dummy members at the periphery of the region in which a fuse is formed. Moreover, it is needless to say that the dummy gate interconnections 34 as described in Embodiment 3 can be disposed in the semiconductor integrated circuit device of Embodiments 1 or 2.

[0157] (Embodiment 4)

[0158]
FIG. 23 is a cross-sectional view illustrating one example of a semiconductor integrated circuit device according to Embodiment 4.

[0159] The semiconductor integrated circuit device according to Embodiment 4 has dummy regions 60 formed in an element isolation region D,3 which defines an active region 4 of a semiconductor substrate 1. In other words, the dummy regions (dummy members) 60 are formed in the wide element isolation region D. Since elements and interconnections on the semiconductor substrate, except for the element isolation structure, are similar to those of Embodiment 1, a description thereof will be omitted. The dummy regions 60 may be formed in a scribing area, and they are disposed under similar conditions to those in Embodiment 1 concerning the dummy interconnections 11. The dummy regions 60 have been formed as described above so that, upon the formation of the element isolation region D,3 by the CMP method, no dishing occurs in the element isolation region D,3 and therefore, the planarization of the surface of the semiconductor substrate 1 can be attained. In addition, by decreasing the size of the dummy regions 60 and optimizing the number of them, a rise in the parasitic capacitance attributable to the existence of the dummy regions 60 can be prevented, whereby the performance of the semiconductor integrated circuit device can be maintained.

[0160] Incidentally, in a region where gate interconnections 6 are to be formed, on the principal surface of the semiconductor substrate 1, it is not recommended to dispose the dummy regions 60. In other words, below the gate interconnections 6, a prohibited area 70 is provided in which no dummy region 60 is disposed. Such a state is illustrated in FIGS. 24 and 31. The dummy regions 60 have the same effects with the active region 4 of the semiconductor substrate 1. When the gate interconnection 6 is formed right above the dummy region 60, the gate interconnection 6 and the active region 4 become opposed to each other through the gate insulating film 5 and the parasitic capacitance of the gate interconnection 6 increases. When the dummy regions 60 are not disposed in the area where the gate interconnection 6 is to be formed, on the other hand, the parasitic capacitance of the gate interconnection 6 does not show an increase. As a result, such a constitution prevents the deterioration in the performance of the semiconductor integrated circuit device. In this Embodiment, the dummy regions 60 each has a quadrate shape having as width (a) and length (b), about 15 to 20 μm. This Embodiment is not limited to the use of a quadrate shape, but another shape, such as a square, also can be employed.

[0161] A description will next be made of the fabrication process of the semiconductor integrated circuit device according to Embodiment 4 with reference to FIGS. 25 to 28.

[0162] As illustrated in FIG. 25, a silicon nitride film 61 is deposited on the principal surface of the semiconductor substrate 1, followed by the patterning of the silicon nitride film 61 and the semiconductor substrate 1 to form shallow trenches 2. The shallow trenches 2 include both those which will be element isolation regions D,3 and those which are dummy regions 60. In other words, the shallow trenches 2 are formed so that the dummy regions 60 are disposed in the element isolation region D,3 which defines the active region 4.

[0163] As illustrated in FIG. 26, a silicon oxide film is deposited, for example, by the CVD method. As a first polishing, the resulting film is polished by the CMP method and embedded in the shallow trench 2, whereby the element isolation region D,3 and dummy regions 60 are formed. For the first polishing, an alkaline slurry containing silicon oxide particles as an abrasive can be employed. In this case, it is necessary to form the silicon oxide film to a certain thickness because a ratio of the polishing rate of the silicon oxide film to that of the silicon nitride film becomes 3 to 4:1.

[0164] As illustrated in FIG. 27, secondary polishing is carried out to remove foreign matter and the damaged layer.

[0165] For secondary polishing, either a soft pad or a chemical solution may be used. Instead, pure water may also be used. Then, both sides of the semiconductor substrate 1 are scrubbed and washed with hydrofluoric acid, followed by washing with ammonia and then hydrochloric acid. Then, the element isolation regions 3 and dummy regions 60 are etched back. The etchback can be effected either by dry etching or wet etching. By the etchback of the element isolation regions 3 and dummy regions 60 as described above, their heights can be made equal or lower than that of the active region, which makes it possible to carry out minute processing of a gate interconnection.

[0166] In the final step, the silicon nitride film 61 is removed, whereby the semiconductor substrate 1 as illustrated in FIG. 28 having the element isolation region D,3, which defines the active region 4, formed thereon is prepared. A description of the subsequent steps will be omitted because they are similar to those of embodiment 1.

[0167] Incidentally, the first polishing can be conducted using a slurry containing cerium oxide as an abrasive. In this case, the ratio of the polishing rate of the silicon oxide film to that of the silicon nitride film falls within a range of from 30-50 to 1, whereby the thickness of the silicon nitride film 61 can be suppressed to 50 nm or less. Since such a small thickness is negligible in the process design, the above-described etchback of the element isolation regions 3 and the dummy regions 60 can be omitted, leading to a simplification of the process.

[0168] The present invention made by the present inventors has been described above specifically based on some embodiments. It should however be borne in mind that the present invention is not limited to the specific embodiments. It is needless to say that various changes and modifications can be made so long as they do not depart from the essence of the invention.

[0169] For example, in the above Embodiments 1 to 4, the CMP step serves as a step for polishing an insulating film. The present invention makes it possible to secure flatness to some extent prior to the CMP polishing so that the CMP polishing can be employed as a finishing step. In this case, not only the CMP method, but also dry-belt polishing or lapping method, can be adopted as the finishing step.

[0170] As illustrated in FIG. 32, the dummy gate interconnections 34 as shown in Embodiment 3 may be disposed in Embodiment 4. FIG. 33 is a fragmentary plan view of FIG. 32. Dummy gate interconnections 34 are constituted so that they extend over element isolation regions D,3 and dummy regions 60. Each of the dummy gate interconnections 34 is formed on the dummy region 60 thorough a gate insulating film 5 under the electrically floating state.

[0171] By ion implantation using as a mask a resist film covering the element isolation region D,3 upon the formation of a semiconductor region 8, which is to be a source and drain region for the MISFETQ1, impurities are not introduced into each of the dummy regions 60 and a semiconductor region 8 is not formed in this region.

[0172] As illustrated in FIG. 34, the dummy gate interconnections 34 may be formed to be slender over the interconnection as illustrated in FIG. 34, which makes it possible to improve the flatness of the surface of the insulting film.

[0173] The dummy gate interconnections 34 may be formed to extend only over the element isolation region 3 and not to extend over the dummy regions 60, so that the capacitance between the substrate 1 and the dummy gate interconnections 34 is decreased. Incidentally, it is needless to say that the dummy regions 60 as is shown in this Embodiment can be employed in Embodiment 3.

[0174] The advantages available by the typical embodiments, among those disclosed herein, will hereinafter be described simply.

[0175] The surface of a member after polishing by the CMP method can be planarized completely.

[0176] The process margin in the photolithography step, etching step and the like can be heightened, a demand for minute processing and integration heightening can be satisfied, and the reliability and yield of the semiconductor integrated circuit device can be improved.

[0177] The process can be started easily.

[0178] The amount of polishing of the member to be polished by the CMP method can be reduced, which decreases the load and time of the step, leading to an improvement in the cost competitive advantage.

[0179] A method of designing a member pattern permitting the complete planarization by the CMP method can be provided.

[0180] An increase in the parasitic capacitance of interconnections or the like, which is derived from the measures to actualize the complete planarization, can be suppressed, whereby the performance of the semiconductor integrated circuit device can be maintained.

Number	Date	Country	Kind
9-81013	May 1997	JP
10-33388	Feb 1998	JP

	Number	Date	Country
Parent	09050416	Mar 1998	US
Child	09846260	May 2001	US

Semiconductor integrated circuit device

Information

Publication Number

Date Filed

Date Published

Inventors

CPC

US Classifications

International Classifications

Abstract

Description

Claims

Priority Claims (2)

Parent Case Info

Divisions (1)