Patent Application
20240203836
High voltage discrete or microcontroller modules require a gate driver. If the gate driver and high voltage switch devices are placed on the same lead frame, the gate driver must be isolated from the package lead frame. The gate driver is typically isolated by using a separate paddle on the lead frame or by using an interposer such as ceramic, glass or polymer between the gate driver and the lead frame. In the case of a separate paddle for providing the isolation, the spacing between pads which are exposed on the outside of the package must be large enough to accommodate the difference in voltage which increases the package size and adds to the overall product cost. In the case of an interposer for providing the isolation, the interposer represents a significant cost adder due to the additional material cost for the interposer and process step for placing the interposer.
Accordingly, there is a need for an improved technique for isolating gate drivers from high voltage switch devices in high voltage discrete or microcontroller modules.
According to an embodiment of a semiconductor package, the semiconductor package comprises: a substrate; a high voltage semiconductor die attached to an electrically conductive part of the substrate; and a gate driver semiconductor die attached, by an electrically insulative die attach material, to the electrically conductive part of the substrate or to a side of the high voltage semiconductor die that faces away from the substrate, wherein the gate driver semiconductor die comprises a semiconductor body and a polymer material covering a backside of the semiconductor body, wherein the polymer material is interposed between the semiconductor body and the die attach material such that the semiconductor body is electrically insulated from the substrate or the side of the high voltage semiconductor die that faces away from the substrate by an insulator stack that comprises both the polymer material and the die attach material.
According to an embodiment of a method of producing a plurality of semiconductor packages, the method comprises: forming a gate driver circuit at a plurality of die locations in a semiconductor wafer; thinning a backside of the semiconductor wafer; covering the thinned backside of the semiconductor wafer with a polymer material; singulating the semiconductor wafer with the polymer material into a plurality of gate driver semiconductor dies; and for each gate driver semiconductor die: attaching a high voltage semiconductor die to an electrically conductive part of a substrate; and attaching, by an electrically insulative die attach material, the gate driver semiconductor die to the electrically conductive part of the substrate or to a side of the high voltage semiconductor die that faces away from the substrate, wherein the polymer material is interposed between a semiconductor body of the gate driver semiconductor die and the die attach material such that the semiconductor body is electrically insulated from the substrate or the side of the high voltage semiconductor die that faces away from the substrate by an insulator stack that comprises both the polymer material and the die attach material.
Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.
The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. The features of the various illustrated embodiments can be combined unless they exclude each other. Embodiments are depicted in the drawings and are detailed in the description which follows.
The embodiments described provide a polymer isolation material applied to the backside of a gate driver semiconductor die (chip) as part of wafer processing. The gate driver semiconductor die with the backside polymer isolation material can be singulated from a wafer and die bonded using an electrically insulative material without the need for an interposer. Breakdown due to voids in the electrically insulative die attach material is avoided by applying the polymer isolation material to the backside of the gate driver semiconductor die, which provides the primary isolation.
Described next, with reference to the figures, are embodiments of producing the backside-isolated gate driver semiconductor dies and semiconductor packages that include the gate driver semiconductor dies.
In one embodiment, singulation of the semiconductor wafer 100 includes attaching the thinned backside 108 of the semiconductor wafer 100 with the polymer material 110 to the dicing film 114 by the die attach material 112. The semiconductor wafer 110 is then cut through along the dicing streets 106 which delimit the die locations 104 using a first blade 118 having a first width W1. Both the polymer material 110 and the die attach material 112 are then cut through along the dicing streets 106 using a second blade 120 having a second width W2 that is less than the first width W1.
The first dicing blade 118 may be tapered, e.g., such that the cutting using the first blade 118 tapers inward an edge 122 of each gate driver semiconductor die 116. According to this embodiment, the tapered edge 122 of the gate driver semiconductor dies 116 creates a step between the die semiconductor material and the polymer material 110 applied to the backside 108 of the dies 116. The tapered edge 122 increases tracking distance and reduces a risk of metal fragments in the dicing streets 106 from being carried to the edge 122 of the gate driver semiconductor dies 116 which would otherwise create a leakage path.
Other techniques such as laser cutting may be used to singulate the semiconductor wafer 100 into the individual gate driver semiconductor dies 116. As explained above, the die attach material 112 may be applied to the polymer material 110 before or after singulation of the semiconductor wafer 100. The gate driver semiconductor dies 116 may be electrically tested before and/or after the wafer singulation process.
In one embodiment, the die attach material 112 used during wafer singulation remains on the polymer material 110 of the individual gate driver semiconductor dies 116 after the singulation process and forms the electrically insulative die attach material 124. Accordingly, the electrically insulative die attach material 124 may be a die attach film or an epoxy adhesive used during the wafer singulation process, e.g., as shown in
In another embodiment, the die attach material 112 used during the wafer singulation process is removed after the wafer singulation process and a different material is used as the electrically insulative die attach material 124 that attaches the gate driver semiconductor die 116 to the electrically conductive part 126 of the substrate 128. In either case, the polymer material 110 applied to the backside of the gate driver semiconductor die 116 may be thicker than the electrically insulative die attach material 124. For example, the polymer material 110 may have a thickness in a range of 25 μm to 50 μm and the electrically insulative die attach material 124 may have a thickness in a range of 20 μm to 30 μm.
The substrate 128 to which the gate driver semiconductor die 116 is attached may be a die paddle of an electrically conductive lead frame such as a Cu (copper) lead frame, for example. According to this embodiment, the entire substrate 128 is electrically conductive. In another embodiment, the substrate 128 includes a ceramic body and the electrically conductive part 126 of the substrate 128 is a segment of a patterned metallization formed on the ceramic body. In another embodiment, the substrate 128 is a laminate and the electrically conductive part 126 of the substrate 128 is a segment of a patterned metallization formed on the laminate.
As explained above, the gate driver semiconductor die 116 has a semiconductor body 130 and a polymer material 110 covering the backside of the semiconductor body 130. The polymer material 130 is interposed between the semiconductor body 130 and the electrically insulative die attach material 124, such that the semiconductor body 130 is electrically insulated from the electrically conductive part 126 of the substrate 128 by an insulator stack that includes both the polymer material 110 and the electrically insulative die attach material 124. In one embodiment, the insulator stack has a breakdown voltage greater than 3 kV.
The high voltage semiconductor die 202 is attached to the electrically conductive part 126 of the substrate 128 by a die attach material 206. The die attach material 206 may be the same or a different material as the electrically insulative die attach material 124 that attaches the gate driver semiconductor die 116 to the electrically conductive part 126 of the substrate 128. For example, if the high voltage semiconductor die 202 is a lateral device with no electrical connection to the substrate 128, the die attach materials 124, 206 may comprise the same electrically insulative material.
If, however, the high voltage semiconductor die 202 is a vertical device with an electrical connection to the electrically conductive part 126 of the substrate 128, the die attach material 206 that attaches the high voltage semiconductor die 202 to the substrate 128 is electrically conductive. For example, the die attach material 206 that attaches the high voltage semiconductor die 202 to the substrate 128 may be solder, an electrically conductive adhesive, a sintered material, etc. whereas the die attach material 124 that attaches the gate driver semiconductor die 116 to the substrate 128 may be an electrically insulative die attach film, epoxy adhesive, etc. In either case, electrical connections 208 such as bond wire connections, ribbon connections, metal clip connections, etc. may be formed between the topside of the respective semiconductor dies 116, 202 and the substrate 108 and/or between the dies 116, 202.
In
In
In either case, both the gate driver semiconductor die 116 and the high voltage semiconductor die 202 are attached to the same segment 504 of the topside patterned metallization 506 in
Although the present disclosure is not so limited, the following numbered examples demonstrate one or more aspects of the disclosure.
Example 1. A semiconductor package, comprising: a substrate; a high voltage semiconductor die attached to an electrically conductive part of the substrate; and a gate driver semiconductor die attached, by an electrically insulative die attach material, to the electrically conductive part of the substrate or to a side of the high voltage semiconductor die that faces away from the substrate, wherein the gate driver semiconductor die comprises a semiconductor body and a polymer material covering a backside of the semiconductor body, wherein the polymer material is interposed between the semiconductor body and the die attach material such that the semiconductor body is electrically insulated from the substrate or the side of the high voltage semiconductor die that faces away from the substrate by an insulator stack that comprises both the polymer material and the die attach material.
Example 2. The semiconductor package of example 1, further comprising: a mold compound encapsulating the high voltage semiconductor die and the gate driver semiconductor die.
Example 3. The semiconductor package of example 1 or 2, wherein the polymer material has a thickness of at least 25 μm.
Example 4. The semiconductor package of example 3, wherein the thickness of the polymer material is in a range of 25 μm to 50 μm.
Example 5. The semiconductor package of any of examples 1 through 4, wherein the polymer material is thicker than the die attach material.
Example 6. The semiconductor package of any of examples 1 through 5, wherein the polymer material has a dielectric strength greater than 25 kV/mm.
Example 7. The semiconductor package of any of examples 1 through 6, wherein the insulator stack has a breakdown voltage greater than 3 kV.
Example 8. The semiconductor package of any of examples 1 through 7, wherein the polymer material is an epoxy or a polyimide.
Example 9. The semiconductor package of any of examples 1 through 8, wherein the die attach material is a die attach film or an epoxy adhesive.
Example 10. The semiconductor package of any of examples 1 through 9, wherein the substrate is a lead frame, wherein both the gate driver semiconductor die and the high voltage semiconductor die are attached to a die paddle a die paddle of the lead frame, and wherein the semiconductor body of the gate driver semiconductor die is electrically insulated from the die paddle by both the polymer material and the die attach material.
Example 11. The semiconductor package of any of examples 1 through 9, wherein the substrate is a lead frame, wherein the high voltage semiconductor die is attached to a die paddle of the lead frame, wherein the gate driver semiconductor die is attached to the side of the high voltage semiconductor die that faces away from the die paddle, and wherein the semiconductor body of the gate driver semiconductor die is electrically insulated from the high voltage semiconductor die by both the polymer material and the die attach material.
Example 12. The semiconductor package of any of examples 1 through 9, wherein the substrate comprises a ceramic body, wherein the electrically conductive part of the substrate is a segment of a patterned metallization formed on the ceramic body, wherein both the gate driver semiconductor die and the high voltage semiconductor die are attached to the segment of the patterned metallization, and wherein the semiconductor body of the gate driver semiconductor die is electrically insulated from the segment of the patterned metallization by both the polymer material and the die attach material.
Example 13. The semiconductor package of any of examples 1 through 9, wherein the substrate is a laminate, wherein the electrically conductive part of the substrate is a segment of a patterned metallization formed on the laminate, wherein both the gate driver semiconductor die and the high voltage semiconductor die are attached to the segment of the patterned metallization, and wherein the semiconductor body of the gate driver semiconductor die is electrically insulated from the segment of the patterned metallization by both the polymer material and the die attach material.
Example 14. The semiconductor package of any of examples 1 through 13, wherein an edge of the gate driver semiconductor die tapers inward.
Example 15. The semiconductor package of any of examples 1 through 14, wherein the high voltage semiconductor die is a microcontroller die for a high voltage transistor or is a discrete high voltage transistor die.
Example 16. The semiconductor package of any of examples 1 through 15, wherein the polymer material comprises a different material than the die attach material.
Example 17. A method of producing a plurality of semiconductor packages, the method comprising: forming a gate driver circuit at a plurality of die locations in a semiconductor wafer; thinning a backside of the semiconductor wafer; covering the thinned backside of the semiconductor wafer with a polymer material; singulating the semiconductor wafer with the polymer material into a plurality of gate driver semiconductor dies; and for each gate driver semiconductor die: attaching a high voltage semiconductor die to an electrically conductive part of a substrate; and attaching, by an electrically insulative die attach material, the gate driver semiconductor die to the electrically conductive part of the substrate or to a side of the high voltage semiconductor die that faces away from the substrate, wherein the polymer material is interposed between a semiconductor body of the gate driver semiconductor die and the die attach material such that the semiconductor body is electrically insulated from the substrate or the side of the high voltage semiconductor die that faces away from the substrate by an insulator stack that comprises both the polymer material and the die attach material.
Example 18. The method of example 17, wherein the singulating comprises: attaching the thinned backside of the semiconductor wafer with the polymer material to a temporary carrier by a die attach film or epoxy adhesive; cutting through the semiconductor wafer along dicing streets which delimit the die locations using a first blade having a first width; and cutting through both the polymer material and the die attach film or epoxy adhesive along the dicing streets using a second blade having a second width that is less than the first width.
Example 19. The method of example 18, wherein the cutting using the first blade tapers inward an edge of each gate driver semiconductor die.
Example 20. The method of example 18 or 19, wherein the die attach film or epoxy adhesive remains on the polymer material of the gate driver semiconductor dies after the singulating and forms the electrically insulative die attach material.
Example 21. The method of any of examples 16 through 20, further comprising: encapsulating each high voltage semiconductor die and corresponding gate driver semiconductor die in a mold compound.
Example 22. The method of any of examples 16 through 21, further comprising: electrically testing the gate driver semiconductor dies before attaching the gate driver semiconductor dies to the electrically conductive part of the corresponding substrate or to the corresponding high voltage semiconductor die.
Terms such as “first”, “second”, and the like, are used to describe various elements, regions, sections, etc. and are also not intended to be limiting. Like terms refer to like elements throughout the description.
As used herein, the terms “having”, “containing”, “including”, “comprising” and the like are open ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The articles “a”, “an” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.
The expression “and/or” should be interpreted to mean all possible conjunctive and disjunctive combinations, unless expressly noted otherwise. For example, the expression “A and/or B” should be interpreted to mean only A, only B, or both A and B. The expression “at least one of” should be interpreted in the same manner as “and/or”, unless expressly noted otherwise. For example, the expression “at least one of A and B” should be interpreted to mean only A, only B, or both A and B.
It is to be understood that the features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.
