Patent Application
20100181675
The present invention generally relates to a semiconductor package, and in one embodiment to a semiconductor package that includes a chip and a wire bond that is wedge bonded to the chip.
Semiconductor chips include bond pads that are electrically connected to external circuitry in order to function as part of an electronic system. The external circuitry is typically a lead array such as lead frame or a support substrate such as a printed circuit board. Electrical connection between the chip and the external circuitry is often achieved by wire bonding, tape automated bonding (TAB) or flip-chip bonding. For instance, with flip-chip bonding, ball grid array (BGA) packages contain an array of solder balls to mount on corresponding terminals on a printed circuit board, and land grid array (LGA) packages contain an array of metal pads that receive corresponding solder traces mounted on corresponding terminals on a printed circuit board.
Wire bonding is the most common and economical connection technique. The wires are bonded, one at a time, from the chip to external circuitry by thermocompression, thermosonic or ultrasonic processes. For instance, a wire is fed from a spool through a clamp and a capillary, a thermal source forms a wire ball on the wire, the capillary is brought down over an aluminum bond pad and exerts pressure on the wire ball, and the wire ball forms a ball bond on the bond pad using thermocompression. The capillary is then raised and moved to a lead and brought down again, and the force and heat form a wedge bond on the lead using ultrasonic vibration. After raising the capillary again, the wire is ripped from the wedge bond and the process is repeated for other bond pads and leads. There are many variations on these basic methods.
Wire bonds have been devised that include a wedge bond on a ball bond on the bond pad and a ball bond on the lead. The ball bond on the bond pad prevents the wedge bond from propagating cracks through the bond pad into an underlaying aluminum layer of the chip. However, the ball bond on the bond pad requires extra wire and entails an additional process step, which increases size, cost and manufacturing time.
Therefore, there is a need for a wire bonding process that provides a wedge bond on a chip in a reliable, efficient and cost-effective manner.
The present invention provides a semiconductor package that includes a semiconductor chip, a wire bond and a metal element. The chip includes a bond pad with a copper layer. The wire bond is wedge bonded to the bond pad and ball bonded to the metal element.
The present invention also provides a method of manufacturing a semiconductor package that includes providing a semiconductor chip that includes a bond pad with a copper layer, providing a metal element that is spaced from the chip, and then wedge bonding a wire bond to the bond pad and ball bonding the wire bond to the metal element.
These and other features and advantages of the present invention will become more apparent in view of the detailed description that follows.
The accompanying drawings are included to provide a further understanding of embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and together with the description serve to explain principles of embodiments. Other embodiments and many of the intended advantages of embodiments will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.
In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
It is to be understood that the features of the various exemplary embodiments described herein may be combined with each other, unless specifically noted otherwise.
Chip 202 includes opposing major surfaces 216 and 218. Chip 202 also includes bond pad 208 and passivation layer 220 at surface 216. Bond pad 208 protrudes from passivation layer 220 at surface 216.
Metal element 204 is a lead that is spaced from chip 202 and electrically connected to bond pad 208 by the wire bond 206, protrudes from encapsulant 214 and provides electrical conduction of current between bond pad 208 and external circuitry during operation of chip 202.
Encapsulant 214 contacts and protects chip 202 and wire bond 206.
Chip 202 includes active metal layer 222 beneath surface 216. Active metal layer 222 is an interconnect line that electrically connects bond pad 208 with various transistors (not illustrated) within chip 202.
Bond pad 208 includes noble metal layer 224, adhesion layer 226 and copper layer 228. Noble metal layer 224 is a surface layer, adhesion metal layer 226 is buried beneath noble metal layer 224, and copper layer 228 is buried beneath noble metal layer 224 and adhesion metal layer 226. Thus, adhesion metal layer 226 contacts and is sandwiched between noble metal layer 224 and copper layer 228, copper layer 228 contacts and is sandwiched between adhesion metal layer 226 and active metal layer 222, and active metal layer 222 contacts and extends beneath copper layer 228. Thus, bond pad 208 excludes a ball bond. In addition, noble metal layer 224 prevents copper layer 228 from oxidizing.
Wire bond 206 can be various metals such as gold, silver, copper, gold-silver and copper-palladium, active metal layer 222 can be various metals such as aluminum and copper, noble metal layer 224 can be various noble metals such as palladium, gold and silver, and metal adhesion layer 226 can be various metals such as nickel, nickel-phosphorus and nickel-molybdenum. In one embodiment, wire bond 206 is gold, active metal layer 222 is aluminum, noble metal layer 224 is palladium, and metal adhesion layer 226 is nickel. In one embodiment, active metal layer 222 has a thickness of 2 microns, noble metal layer 224 has a thickness of 6 microns, adhesion metal layer 226 has a thickness of 1.2 microns, and copper layer 228 has a thickness of 6 microns.
Bond pad 208 is formed by an electroless plating operation. Initially, an opening is formed in passivation layer 220 that exposes the aluminum layer (active metal layer 222) using a photoresist layer as an etch mask. Thereafter, the structure is submerged in an electroless copper plating solution using the photoresist layer as a plating mask. As a result, the copper layer (copper layer 228) electrolessly plates on the aluminum layer. The electroless copper plating operation continues until the copper layer has the desired thickness. Thereafter, the structure is removed from the electroless copper plating solution and submerged in an electroless nickel plating solution using the photoresist layer as a plating mask. As a result, the nickel layer (metal adhesion layer 226) electrolessly plates on the copper layer. The electroless nickel plating operation continues until the nickel layer has the desired thickness. Thereafter, the structure is removed from the electroless nickel plating solution and submerged in an electroless palladium plating solution using the photoresist layer as a plating mask. As a result, the palladium layer (noble metal layer 224) electrolessly plates on the nickel layer. The electroless palladium plating operation continues until the palladium layer has the desired thickness. Thereafter, the structure is removed from the electroless palladium plating solution and rinsed in distilled water.
Wedge bond 210 extends into but not through noble metal layer 224 and is spaced from active metal layer 222, adhesion metal layer 226 and copper layer 228.
Wedge bond 210 is formed under substantial compressive force and vibration using ultrasonic bonding. As a result, wedge bond 210 creates cracks in noble metal layer 224 that propagate through adhesion metal layer 226 to copper layer 228. Furthermore, these cracks would propagate to active metal layer 222 and thus damage chip 202 in the absence of copper layer 228. Copper layer 228 absorbs stress created during the wedge bonding and does not crack due to its robust metallurgical properties, thereby protecting active metal layer 222 from cracks caused by wedge bond 210.
Semiconductor package 300 is generally similar to semiconductor package 200, except that noble metal layer 324 and adhesion metal layer 326 are thinner than noble metal layer 224 and adhesion metal layer 224, and wedge bond 310 extends through noble metal layer 324 and adhesion metal layer 326 into copper layer 328.
Chip 302 includes active metal layer 322. Bond pad 308 includes noble metal layer 324, adhesion layer 326 and copper layer 328.
Wire bond 306 can be various metals such as copper and copper-palladium, active metal layer 322 can be various metals such as aluminum and copper, noble metal layer 324 can be various noble metals such as palladium, gold and silver, and metal adhesion layer 326 can be various metals such as nickel, nickel-phosphorus and nickel-molybdenum. In one embodiment, wire bond 306 is copper, active metal layer 322 is aluminum, noble metal layer 324 is palladium, and metal adhesion layer 326 is nickel. In one embodiment, active metal layer 322 has a thickness of 2 microns, noble metal layer 324 has a thickness of 1 micron, adhesion metal layer 326 has a thickness of 0.5 microns, and copper layer 328 has a thickness of 6 microns.
Bond pad 308 is formed by an electroless plating operation in a manner similar to bond pad 208.
Wedge bond 310 extends through noble metal layer 324 and adhesion metal layer 326 into but not through copper layer 328 and is spaced from active metal layer 322.
Wedge bond 310 creates cracks in noble metal layer 324 and adhesion metal layer 326. Furthermore, these cracks would propagate to active metal layer 322 and thus damage chip 302 in the absence of copper layer 328. Advantageously, copper layer 328 absorbs stress created during the wedge bonding and does not crack due to its robust metallurgical properties, thereby protecting active metal layer 322 from cracks caused by wedge bond 310.
Semiconductor package 400 is generally similar to semiconductor package 200, except that bond pad 408 is copper layer 428, and wedge bond 410 extends into copper layer 428.
Chip 402 includes active metal layer 422. Bond pad 408 includes copper layer 428, which is a surface layer (rather than a buried layer).
Wire bond 406 can be various metals such as copper and copper-palladium, and active metal layer 422 can be various metals such as aluminum and copper. In one embodiment, wire bond 406 is copper, and active metal layer 422 is aluminum. In one embodiment, active metal layer 422 has a thickness of 2 microns, and copper layer 428 has a thickness of 6 microns.
Bond pad 408 is formed by an electroless plating operation in a manner similar to bond pad 208, except that the copper layer is electrolessly plated on the aluminum layer and the electroless nickel and palladium plating operations are omitted.
Wedge bond 410 extends into but not through copper layer 428 and is spaced from active metal layer 422.
Wedge bond 410 could create cracks that would propagate to active metal layer 422 and thus damage chip 402 in the absence of copper layer 428. Advantageously, copper layer 428 absorbs stress created during the wedge bonding and does not crack due to its robust metallurgical properties, thereby protecting active metal layer 422 from cracks caused by wedge bond 410.
Semiconductor package 500 is generally similar to semiconductor package 200, except that semiconductor package 500 includes semiconductor chip 530 with bond pad 532 and metal element 504 is bond pad 532. Wire bond 506 provides electrical conduction of current between chips 502 and 530 during operation of chips 502 and 530. Encapsulant 514 contacts and protects chips 502 and 530 and wire bond 506.
The above description and examples illustrate embodiments of the present invention, and it will be appreciated that various modifications and improvements can be made without departing from the scope of the present invention.
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.
