Claims
- 1. A resistive semiconductor device, comprising:
a semiconductor substrate; and a plurality of magnetic memory storage cells disposed over the substrate, each storage cell including a first end and a second end, the storage cells being coupled in series to one another so that a first end of one of the storage cells is coupled to a second end of an adjacent one of the storage cells.
- 2. The resistive semiconductor device according to claim 1, wherein the cells are magnetic random-access memory (MRAM) cells.
- 3. The resistive semiconductor device according to claim 2, wherein the magnetic memory storage cells comprise magnetic stacks, the magnetic stacks including a tunnel junction, wherein a logic state is storable in each magnetic stack.
- 4. The resistive semiconductor device according to claim 3, further comprising a plurality of transistors, a respective one of the transistors being coupled in parallel to each memory storage cell, the transistors coupled in series to one another, the transistors being adapted to control the memory storage cells.
- 5. The resistive semiconductor device according to claim 4 wherein data stored in each memory storage cell is accessed by turning on at least one of the transistors.
- 6. The resistive semiconductor device according to claim 5, wherein at least one of the transistors comprises a depletion device.
- 7. The resistive semiconductor device according to claim 5, further comprising a plurality of wordlines, bitlines and digitlines proximate the memory storage cells, wherein the magnetic stacks are not coupled directly to the wordlines, bit-lines and digitlines.
- 8. The resistive semiconductor device according to claim 7, wherein current may be passed bidirectionally through the tunnel junctions.
- 9. The resistive semiconductor device according to claim 8, further comprising a plurality of vias coupling at least one side of each magnetic stack to an active area.
- 10. The resistive semiconductor device according to claim 9, wherein the active area is continuous and enables each of the plurality of transistors.
- 11. A magnetic random-access memory (MRAM) semiconductor device, comprising:
a semiconductor substrate; a first transistor having a gate, a first source/drain region and second source/drain region disposed on the substrate; a second transistor having a gate, a first source/drain region and a second source/drain region, the second transistor first source/drain region being coupled to the first transistor second source/drain region; a first magnetic stack having a first end and a second end, the first magnetic stack first end being coupled to the first transistor first source/drain region, the first magnetic stack second end being coupled to the first transistor second source/drain region; and a second magnetic stack having a first end and a second end, the second magnetic stack first end being coupled to the second transistor first source/drain region, the second magnetic stack second end being coupled to the second transistor second source/drain region.
- 12. The MRAM semiconductor device according to claim 11, further comprising:
a first wordline coupled to the first transistor gate; a second wordline coupled to the second transistor gate; and a bitline coupled to the first transistor first source/drain region.
- 13. The MRAM semiconductor device according to claim 12, further comprising:
a third transistor having a gate, a first source/drain region and a second source/drain region, the third transistor source/drain region being coupled to the second transistor second source/drain region, the third transistor gate being coupled to a third wordline; a fourth transistor having a gate, a first source/drain region and a second source/drain region, the fourth transistor source/drain region being coupled to the third transistor second source/drain region, the fourth transistor gate being coupled to a fourth wordline; a third magnetic stack having a first end and a second end, the third magnetic stack first end being coupled to the third transistor first source/drain region, the third magnetic stack second end being coupled to the third transistor second source/drain region; a fourth magnetic stack having a first end and a second end, the fourth magnetic stack first end being coupled to the fourth transistor first source/drain region, the fourth magnetic stack second end being coupled to the fourth transistor second source/drain region; and a ground node coupled to the fourth transistor second source/drain region.
- 14. The MRAM semiconductor device according to claim 13, further comprising a select switch coupled between the bitline and the first transistor first source/drain region.
- 15. The MRAM semiconductor device according to claim 13, further comprising a select switch coupled between the ground node and the fourth transistor second source/drain region.
- 16. The MRAM semiconductor device according to claim 13, wherein the first, second, third and fourth transistors comprise depletion devices.
- 17. The MRAM semiconductor device according to claim 16, wherein each magnetic stack includes a tunnel junction, wherein the tunnel junctions are not directly coupled to the bitline or wordlines.
- 18. A method of manufacturing a magnetic random-access memory (MRAM) semiconductor device, comprising:
providing a semiconductor substrate; and forming a plurality of magnetic memory storage cells over the substrate, each storage cell including a first end and a second end, wherein the storage cells are coupled together in series to one another so that a first end of one of the storage cells is coupled to a second end of an adjacent one of the storage cells.
- 19. The method according to claim 18, further comprising coupling a transistor in parallel to each magnetic memory storage cell, the transistors being coupled in series to one another.
- 20. The method according to claim 19, wherein coupling a transistor to each magnetic memory storage cell comprises coupling a depletion device to each magnetic memory storage cell.
- 21. The method according to claim 18, further comprising disposing wordlines, bitlines and digitlines proximate the magaetic memory storage cells, wherein the wordlines, bitlines and digitlines are not directly coupled to the magnetic memory storage cells.
- 22. The method according to claim 18, further comprising coupling each magnetic memory storage cell to a single active area.
Parent Case Info
[0001] This patent claims the benefit of U.S. Provisional Patent Application Serial No. 60/263,931, filed Jan. 24, 2001, which is incorporated herein by reference.
Provisional Applications (1)
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Number |
Date |
Country |
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60263931 |
Jan 2001 |
US |