Patent Application
20170288650
The present disclosure generally relates to circuits for transmitting power across an isolation barrier and applying frequency hopping for power transmission.
Some integrated circuits include two or more voltage domains that are galvanically isolated from one another. In such integrated circuits, it may be desirable to transmit power from one domain to another. Existing circuits to transmit power from one domain to another, while maintaining galvanic isolation, suffer from a variety of drawbacks. For example, some conventional tank circuits use cross-coupled metal oxide semiconductor (MOS) transistors, which lead to poor efficiency and poor electromagnetic interference (EMI) performance.
Therefore, the inventors recognized a need in the art for circuits and methods to efficiently transmit power between galvanically-isolated domains and improve EMI performance.
Embodiments of the present disclosure may provide a circuit comprising a tank circuit. The tank circuit may include an inductor having a pair of terminals, a first pair of transistors, and a first pair of capacitors. Each transistor may be coupled between a respective terminal of the inductor and a reference voltage along a source-to-drain path of the transistor. Each capacitor may be provided in a signal path between an inductor terminal coupled to a respective first transistor in the first pair and a gate of a second transistor in the first pair.
Embodiments of the present disclosure may provide controller method for generating an oscillation frequency. The method may include at a first time instance: activating a first pair of transistors of the tank circuit, each coupled between a respective terminal of an inductor having a pair of terminals and a reference voltage along a source-to-drain path of the transistor; coupling, as a result of the activating, a first of a pair of capacitors of the tank circuit provided in a signal path between a source or drain terminal of a first transistor in the first pair and a gate of a second transistor in the first pair; and coupling, as a result of the activating, a second of the pair of capacitors provided in a signal path between a source or drain terminal of the second transistor in the first pair and a gate of the first transistor in the first pair, wherein a voltage having an oscillation frequency is generated at the terminals of the inductor to transmit power over an isolation barrier.
Embodiments of the present disclosure may provide a circuit. The circuit may include a means for activating a first pair of transistors of an inductor-capacitor (LC) tank at a first time instance, each transistor coupled between a respective terminal of an inductor having a pair of terminals and a reference voltage along a source-to-drain path of the transistor. The circuit may also include a first means for coupling, as a result of the activating, a first of a pair of capacitors of the tank circuit provided in a signal path between a source or drain terminal of a first transistor in the first pair and a gate of a second transistor in the first pair. The circuit may further include a second means coupling, as a result of the activating, a second of the pair of capacitors provided in a signal path between a source or drain terminal of the other transistor in the first pair and a gate of the first transistor in the first pair, wherein a voltage having the oscillation frequency is generated at the terminals of the inductor to transmit power over an isolation barrier.
The pair of inductors L1.1, L1.2 may be coupled in series to form a center tap and a pair of terminals (VN, VP). The center tap may be coupled to a power source VDD. The pair of DMOS transistors D0.1, D0.2 may each be coupled, along a respective source-to-drain path, between a respective terminal of the pair of inductors L1.1, L1.2 and a reference voltage GND. The capacitor C0.1 may be provided in a signal path between the inductor L1.1 coupled to DMOS transistor D0.1 and a gate of the DMOS transistor D0.2. Similarly, the capacitor C0.2 may be provided in a signal path between the inductor L1.2 coupled to DMOS transistor D0.2 and a gate of the DMOS transistor D0.1. The pair of disabling transistors TD0.1, TD0.2 may have their gates coupled to a control input (OFF) (logic high) and may be coupled, along their respective source-to-drain paths, between the gates of the DMOS transistors D0.1, D0.2, respectively, and the reference voltage GND. The disabling transistors TD0.1, TD0.2 may be implemented as any known transistor type (e.g., MOS, FET, BJT, DMOS, etc.).
The controller 120 may provide a control signal OFF (logic high) to the gates of the disabling transistors TD0.1, TD0.2 to activate the disabling transistors T0.1, T0.2. When activated, the disabling transistors TD0.1, TD0.2 may pull the gates of the DMOS transistors D0.1, D0.2 low, thereby turning off the DMOS transistors D0.1, D0.2 and disabling the LC tank 210. When the disabling transistors TD0.1, TD0.2 are deactivated (i.e., no OFF signal), the DMOS transistors D0.1, D0.2 may be activated, coupling the capacitors C0.1, C0.2 to the inductors L1.1, L1.2, respectively. Consequently, the LC tank 110 may resonate or oscillate at a resonance or oscillation frequency fosc and transmit power from the power source VDD to a second voltage domain 130 via a pair of inductors L2.1, L2.2. An isolation barrier may be provided in between inductors L1.1, L1.2 and inductors L2.1, L2.2; therefore, the inductors L2.1, L2.2 may be magnetically coupled to, but galvanically isolated from, the inductors L1.1, L1.2. In an embodiment, the inductors L1.1, L1.2 may be the first winding of a transformer and the inductors L2.1, L2.2 may the secondary winding of the transformer. A peak-to-peak voltage of an oscillation voltage of the LC tank 110, between nodes VN and VP, may be two to three times the voltage of the power source VDD.
The oscillation frequency fosc of the oscillator circuit 100 may be related to the inductances of the inductors L1.1, L1.2, the capacitances of the capacitors C0.1, C0.2, and the capacitances of the DMOS transistors D0.1, D0.2. Therefore, the oscillation frequency fosc may be tuned by tuning the sizes of the inductors L1.1, L1.2, the capacitors C0.1, C0.2, and the DMOS transistors D0.1, D0.2 during fabrication of the LC tank 110. Ideally, the inductors L1.1, L1.2 would have substantially the same inductances, the capacitors C0.1, C0.2 would have substantially the same capacitances, and the DMOS transistors D0.1, D0.2 would be sized to have substantially identical (parasitic) capacitances. In practice, however, due to manufacturing variations and other factors, the inductances and capacitances may not be perfectly matched. In one embodiment, the DMOS transistors D0.1, D0.2 and the disabling transistors TD0.1, TD0.2 may be fabricated as n-type transistors.
In the LC tank 210, the pair of inductors L1.1, L1.2 may be coupled in series to form a center tap and a pair of terminals. The center tap may be coupled to a power source VDD. The pair of DMOS transistors D0.1, D0.2 may each be coupled, along a respective source-to-drain path, between a respective terminal of the pair of inductors L1.1, L1.2 and a reference voltage GND. The capacitor C0.1 may be provided in a signal path between the inductor L1.1 coupled to DMOS transistor D0.1 and a gate of the DMOS transistor D0.2. Similarly, the capacitor C0.2 may be provided in a signal path between the inductor L1.2 coupled to DMOS transistor D0.2 and a gate of the DMOS transistor D0.1. The pair of disabling transistors TD0.1, TD0.2 may have their gates coupled to a control input (OFF) and may be coupled, along their respective source-to-drain paths, between the gates of the DMOS transistors D0.1, D0.2, respectively, and the reference voltage GND.
As shown in
The controller 220 may provide control signals CTRL1.2-CTRLN.2 (e.g., logic high) to the gates of the disabling transistors TD0.1, TD0.2-TDN.1, TDN.2 to activate the disabling transistors TD0.1, TD0.2-TDN.1, TDN.2. The control signals CTRL1.2-CTRLN.2 each may be formed by the controller as a logical OR of the control signal OFF and an inverted corresponding one of the control signals CTRL1.1-CTRLN.1. When activated, the disabling transistors TD0.1, TD0.2-TDN.1, TDN.2 may pull the gates of the DMOS transistors D0.1, D0.2-DN.1, DN.2 low, thereby turning off the DMOS transistors D0.1, D0.2-DN.1, DN.2 and disabling the LC tank 210 and the sub-tanks 240.1-240.N.
When the disabling transistors TD0.1, TD0.2-TDN.1, TDN.2 are deactivated, the DMOS transistors D0.1, D0.2 may be activated, placing the capacitors C0.1, C0.2 in series with the inductors L1.1, L1.2, respectively. Consequently, the LC tank 210 may resonate or oscillate at a resonance or oscillation frequency fosc and transmit power from the power source VDD to a second voltage domain 230 via a pair of inductors L2.1, L2.2. The inductors L2.1, L2.2 may be magnetically coupled to, but galvanically isolated from, the inductors L1.1, L1.2. The inductors L1.1, L1.2 may be the first winding of a transformer and the inductors L2.1, L2.2 may the secondary winding of the transformer.
When the disabling transistors TD1.1, TD1.2-TDN. 1, TDN.2 are deactivated, the controller 220 may also activate one or more of the sub-tanks 240.1-240.N with control signals CTRL1.1-CTRLN.1, respectively. The controller 220 may provide the control signal CTRL1.1, . . . , CTRLN.1 (e.g., logic high) to the gates of the enabling transistors TE1.3, TE1.4-TN.3, TN.4 to enable the enabling transistors TE1.3, TE1.4-TEN.3, TEN.4. Consequently, the DMOS transistors D1.1, D1.2-DN.1, DN.2 may be activated, placing the capacitor C1.1-CN.1 in parallel with the capacitor C0.1, and the capacitor C1.2-CN.2 in parallel with the capacitor C0.2, thereby increasing the effective capacitance of the oscillator circuit 200 and decreasing the oscillation frequency fosc. Therefore, the oscillation frequency fosc may be set to a plurality of discrete values based on the combination/permutation of the sub-tanks 240.1-240.N activated by the controller 220. The controller 220 may be programmed to “hop” from one oscillation frequency fosc to another at a predetermined time step tstep by selectively activating the sub-tanks 240.1-240.N based on a predetermined oscillation frequency fosc sequence. The predetermined oscillation frequency fosc sequence may last for a time period T and may be repeated thereafter. The predetermined oscillation frequency fosc sequence may be in an ascending order, a descending order, a random order, or any other suitable order.
The oscillation frequency fosc, with the sub-tanks 240.1-240.N deactivated, may be tuned by tuning the sizes of the inductors L1.1, L1.2, the capacitors C0.1, C0.2, and the DMOS transistors D0.1, D0.2 during fabrication of the LC tank 210. Ideally, the inductors L1.1, L1.2 would have substantially identical inductances, the capacitors C0.1, C0.2 would have substantially identical capacitances, the DMOS transistors D0.1, D0.2 would be sized to have substantially identical capacitances. In practice, however, due to manufacturing variations and other factors, the inductances and capacitances may not be perfectly matched. In one embodiment, the DMOS transistors D0.1, D0.2-DN.1, DN.2, the disabling transistors TD0.1, TD0.2-TDN.1, TDN.2, and the enabling transistors TE1.3, TE1.4-TEN.3, TEN.4 may be fabricated as n-type transistors.
The sub-tanks 240.1-240.N may be fabricated to be identical such that, when activated, each sub-tank 240.1, . . . , 240.N may decrease the oscillation frequency fosc by a frequency step fstep. The frequency step fstep may be tuned by tuning the sizes of capacitors C1.1, C1.2-CN.1, CN.2 and the DMOS transistors D1.1, D1.2-DN.1, DN.2. Ideally, the capacitors C1.1, C1.2-CN.1, CN.2 would have substantially identical capacitances and the DMOS transistors D1.1, D1.2-DN.1, DN.2 would be sized to have substantially identical capacitances. In practice, however, due to manufacturing variations and other factors, the capacitances may not be perfectly matched. The time step tstep, the time period T, and the frequency step fstep may be set based on the application of the oscillator circuit 200 and the electromagnetic interference (EMI) requirements, for example. Further, the number of sub-tank circuits may correspond to the number of bits in the frequency hopping scheme. For example, for a 4 bit frequency hopping scheme, 15 sub-tank circuits (24−1) may be provided. The 15 sub-tank circuits and the LC tank circuit may provide 16 carriers for the 4 bit frequency hopping scheme.
The LC tank 510 and the sub-tanks 540.1-540.N may correspond respectively to the LC tank 210 and the sub-tanks 240.1-240.N of
Several embodiments of the disclosure are specifically illustrated and/or described herein. However, it will be appreciated that modifications and variations of the disclosure are covered by the above teachings and within the purview of the appended claims without departing from the spirit and intended scope of the disclosure. Further variations are permissible that are consistent with the principles described above.
