A conventional dynamic random access memory (DRAM) module generally includes on-die termination for impedance matching of signal lines, and signal distortion can be reduced by using the on-die termination. The conventional on-die termination is generally connected to a reference voltage such as a ground voltage, however, this design is not able to optimize the signal quality.
It is therefore an objective of the present invention to provide an on-die termination topology, which can improve the signal quality more, to solve the above-mentioned problem.
According to one embodiment of the present invention, a memory system comprises a memory controller and a memory module, where the memory controller is arranged for generating at least a first clock signal and an inverted first clock signal, and the memory module is arranged to receive at least the first clock signal and the inverted first clock signal from the memory controller. In addition, the memory module comprises a termination module, and the first clock signal is coupled to the inverted clock signal through the termination module.
According to another embodiment of the present invention, a memory module comprises a memory interface circuit and a first termination module, wherein the memory interface circuit is arranged for receives at least a first clock signal and an inverted first clock signal from a memory controller, and the first clock signal is coupled to the inverted first clock signal through the first termination module.
According to another embodiment of the present invention, a control method of a memory module, wherein the memory module comprises a termination module, and the control method comprises: receiving a clock signal and an inverted clock signal from a memory controller; and coupling the clock signal to the inverted clock signal through the termination module within the memory module.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . ” The terms “couple” and “couples” are intended to mean either an indirect or a direct electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.
Please refer to
When the memory system 100 is implemented by the DRAM system the command signals may comprise at least a row address strobe, a column address strobe, and a write enable signal. In addition, the write clock signal WCK and the inverted write clock signal WCKB are arranged for a data signal (DQs) latch in the memory module 120, and the clock signal CLK and the inverted clock signal CLKB are arranged for a command signal (CMDs) latch in the memory module 120, and a frequency of the write clock signal WCK is greater than or equal to a frequency of the clock signal CLK. For example, the memory module 120 may use the write clock signal WCK and the inverted write clock signal WCKB to sample and store the data signal for subsequent signal processing, and the memory module 120 may use the clock signal CLK and the inverted clock signal CLKB to sample and store the command signal for subsequent signal processing.
In the operations of the memory system 100, the memory controller 110 is arranged to receive a request from a host or a processor, and to transmit at least a portion of the data signal DQ, command signals CMDs, the clock signal CLK, the inverted clock signal CLKB, the write clock signal WCK and the inverted write clock signal WCKB to access the memory module 120. In addition, the memory controller 110 may comprise associated circuits, such as an address decoder, a processing circuit, a write/read buffer, a control logic and an arbiter, to perform the related operations. The memory interface circuit 122 comprises a plurality of pads/pins and associated receiving circuit, and the memory interface circuit 122 is arranged to receive the data signal DQs, the write clock signal WCK, the inverted write clock signal WCKB, the command signals CMDs, the clock signal CLK, and the inverted clock signal CLKB from the memory controller 110, and to selectively output the received signals to the control circuit 124. The control circuit 124 may comprise a read/write controller, a row decoder and a column decoder, and the control circuit 124 is arranged to receive the signals from the memory interface circuit 122 to access the memory array 126.
Because the embodiments of the present invention focus on the connections of the on-die termination, detailed descriptions about the other elements are therefore omitted here.
Please refer to
In addition, a quantity of the termination resistors shown in
By using the on-die termination design shown in
In addition, a quantity of the termination resistors shown in
Briefly summarized, in the on-die termination topology of the present invention, the clock signal is allowed to connect the inverted clock signal in die. Therefore, the impedance matching can be more accurate, and the reflection of the signal can be lowered to improve the signal integrity.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
This application claims the priority of U.S. Provisional Application No. 62/298,005, filed on Feb. 22, 2016, which is included herein by reference in its entirety.
Number | Date | Country | |
---|---|---|---|
62298005 | Feb 2016 | US |