This application claims priority of European patent application 2003EP-3103642 (as yet unpublished) filed on Oct. 1, 2003, the contents whereof are hereby incorporated by reference.
The present invention concerns the field of time converters, and more precisely of time-digital-converters, designated TDC (Time-Digital-Converters).
Time digital converters, or TDC, are used whenever one wishes to measure and encode accurately the temporal position of an event, or of a plurality of events, represented by electric pulses, relatively to a reference signal, defining the origin of the temporal scale.
TDCs are used for example in the field of particle physics, to measure the transit time of the elementary particles produced during an interaction, in the different active zones of a segmented particle detector.
TDCs also have applications in many other fields in which an accurate measurement of arrival times of electric pulses is required. In particular, but not exclusively, applications of TDCs comprise temporal photon correlation microscopy, optical tomography, electronic component testing, time-of-flight spectroscopy and reflectometry in the time domain.
A well-known method for encoding time intervals is to count electronically the number of pulses of a clock signal and to copy the value of the counter during the event of interest into a register.
A limitation of this method is that the measurement accuracy is limited by the rate of the clock signal. For a resolution of 10 picoseconds, for example, a 100 gigahertz clock signal is required, so that this level of precision can only be achieved with difficulty by this method.
Another known method is to convert the interval to be measured into a proportionally longer interval, for example with a double-ramp converter, in which a capacitor is loaded and then unloaded with two constant currents of different value.
The time required for the voltage at the terminals of the capacitor to return to zero is proportional to the sought time interval and can be measured with a counter whose rate is relatively low. An inconvenience of this method is the relatively great dead time associated to each measured event, so that this method is only applicable with difficulty to multiple and close pulses, such as for example signals generated by detectors of elementary particles (multi-hit events).
Another inconvenience of the above method is connected to the difficulty of realizing current sources that are constant and independent from the ramp's voltage. Any difference of behavior between the two sources will induce conversion errors.
It is also known to transform a time interval into an analog voltage or load signal of proportional value, thanks to a time amplitude converter (TAC), and to then convert the analog signal into a digital signal by an analog-to-digital converter (ADC). This method has however the disadvantage of a complex and delicate calibration. Another inconvenience of the above method is connected to the difficulty of obtaining a voltage ramp that is exactly linear. The non-linearity of the capacity and/or the non-constancy of the current source are the origin of conversion errors. This method further requires a ramp calibration procedure due to the inevitable initial imprecision of the ramp capacity and current.
It is an aim of the present invention to present a time converter that does not have the inconveniences of the prior art.
It is another aim of the present invention to propose a time converter that associates a high resolution and depth, allowing very accurate measurements of extended temporal intervals.
It is another aim of the present invention to allow a time converter to be made whose resolution is programmable and adaptable to the needs of the application.
It is another aim of the invention to make a time converter that does not require a calibration procedure for it to maintain its accuracy.
These aims are achieved by the device that is the object of the main claim, and notably by a device for measuring the temporal position of an event, comprising: a startable signal generator for generating a periodical signal synchronous with said event and whose phase is correlated to the temporal position of said event, characterized in that said measuring device comprises a first analog-to-digital converter for measuring a plurality of samples of a first reference signal during said event, the values of said samples determining said phase of said periodical signal.
The invention will be better understood by reading the claims and the detailed description illustrated by the figures in which:
a represents a block diagram of a time converter according to one embodiment of the invention;
b represents a block diagram of a time converter according to a later embodiment of the invention;
a and 2b represent chronograms of different signals of the circuits of
The general functioning of a converter 10 according to one aspect of the present invention is now described with reference to the block diagram of
The input signal 2 is an analog or digital signal comprising voltage or current pulses corresponding generally to events whose temporal position is to be determined accurately. In
When required by circumstances, the discriminator could be preceded by a circuit for conditioning the input signal 2, not represented in
A second input of the discriminator 37 is connected to the converter DAC 35 that supplies a constant voltage level 5 representing a threshold level to be exceeded for an event to be detected by the converter 10. Generally, the threshold level 5 will be placed sufficiently low to detect also small pulses, yet sufficiently far from the noise level to limit false triggering.
The DAC 35 allows the threshold value 5 to be easily adapted to the measurement conditions. In a simplified embodiment of the invention, and whenever this flexibility of use is not required, the DAC 35 can be replaced by a generator of fixed or variable reference voltage.
In another embodiment of the invention, the discriminator 37 is a constant fraction discriminator (CFD) that triggers the trigger pulse when the input level has reached a predetermined fraction of its peak value. This arrangement is particularly useful when the amplitude of the input signals can vary from one event to another.
In the diagram of
In a first embodiment of the invention, described with reference to
The digital trigger signal 6 is sent to a coarse measuring system 15, described further below in connection with
The real time counter 61 counts the periods of the sinusoidal signal 13 and is used to feed the two buses 3 and 4, whose contents change synchronously, being incremented at each cycle of the time base 13, during the entire time during which the converter 10 is active. The bus 4 is offset by one half-period relatively to the bus 3 by a logical delay circuit, not represented.
The number of bits of the buses 3 and 4 is chosen as a function of the maximal temporal distance between two events that one wishes to record. Assuming that the time base runs at 100 MHz and that the buses 3 and 4 comprise 32 bits each, the maximal duration will be of 43 seconds. If a more limited duration is sufficient, one can limit the depth of the buses 3 and 4 and of the counter 61, for example to 24 bits for a depth of 167 ms.
The registers 64 and 65 sample the contents of the buses 3 and 4 at the instant of each event signalized by the ascending flank of the trigger signal 6. The content of the registers is then copied into a storage zone provided to this effect in the logical unit 71.
In a preferred embodiment of the invention, the coarse measuring system 15, comprising the real time counter 61, the two buses 3, 4, the delay unit and the registers 64, 65 are realized within an integrated circuit of the type FPGA (Field Programmable Gate Array). Preferably, the FPGA circuit will also comprise the logical unit 71.
The trigger signal 6 is also sent to a fine measuring device 17, comprising the pulse generator 40 and the ADC 52.
The pulse generator 40 triggers a burst of pulses 8 in correlation with each event marked by a pulse of the trigger signal 6. The signal 8 serves as clock for the ADC 52 that samples the sinusoidal signal 13 in correlation with each pulse of the signal 8. The generated signal 8 is, due to the manner in which the circuit 40 functions, synchronous with the trigger signal 6. The signal 8 contains, by the value of its phase, the information on the arrival instant of the event.
The values sampled by the ADC 52 are stored in the logical unit 71. The fact of taking several samples of the sinusoid 13 allows the phase of the latter at the moment of the trigger signal 6 to be determined with a high resolution, as will be seen later.
Assuming that the sinusoidal signal 13 is represented by the relation:
S(t)=A·sin(ω0·t)+D (1)
where the quantity ω0 represents the angular frequency of the signal 13, which is known since it is linked to the internal or external time base, A represents the amplitude of the sinusoid 13 and D represents the voltage, unknown a priori.
At the instant of the trigger TRIG, a burst of N measurements of the signal S(t) is triggered and recorded in 71. One has, for the N samples:
Si=A·sin(ω0·(t0+i·Ts))+D i=0 . . . N−1 (2)
where
All the unknown values, and in particular to (which is the one of interest), can thus be determined as soon as N≧4.
For N>4, the system (2) is over-determined. On can then use best-fit or error minimization techniques to improve the resolution of the fine measurement. The accuracy of the fine measurement thus improves by a factor √{square root over (N−3)}, for example by N=7 the resolution is improved by a factor 2; for N=19, the resolution is improved by a factor 4 and so on, the initial temporal resolution (N=4) being determined by the frequency ω0 and the number of bits of the ADC 52.
The amplitude A is chosen so as to occupy at most the scale of the ADC 52, without however exceeding it.
The sampling period TS is chosen judiciously as a function of the period T0 of the sampled sinusoid. Preferably, a considerably greater rate will be adopted than that of the sinusoid 13, in order to accelerate the conversion time. For example, pulses separated by 1 ns and an ADC 52 with a conversion rate of 1GS/s may be chosen.
Preferably, the three unknown quantities A, TS and D are determined at each new trigger signal and their value is ignored or used for monitoring purposes only. This measuring method has the advantage of not requiring any calibration, the accuracy of the measurement then resting only on the absolute precision and the stability of the frequency ω0.
The quantities A, TS and D are however more or less constant and could be determined once and for all or periodically by a suitable calibration method. It is also possible in the present invention to evaluate separately the quantities A, TS and D during an automatic calibration or on the initiative of an operator, thus reducing the number of pulses required to achieve the desired resolution and limiting the dead time of the converter 10. In a later embodiment of the invention, the calibration of A, TS and D could also be performed only when certain predetermined conditions are met, for example once for the first hit of each event, but not for successive hits.
Thanks to the multiple samples, it is possible to increase considerably the temporal resolution of the converter 10. For example, by digitizing 9 samples of the sinusoid 13 at 100 MHz with an ADC at 6 bits, it is possible to achieve a resolution of 25 ps or better.
According to the case and the characteristics of the components used, it is possible that all the pulses 8 are not sampled. If for example the ADC 52 has an internal pipeline architecture, one or several pulses at the beginning and at the end of the burst are necessary only to activate the ADC and to extract the data from the pipeline. In this case, the number of pulses in each burst can be increased in order to always have a sufficient number of samples.
The pulse generator 40 represented in
During the explanation on how the coarse measuring device functions, it has been seen that the two registers 64 and 65 record two measurements independent from the temporal position of the event relatively to the two time bases 3 and 4 that are isochronous and offset by half a period. This duplication allows ambiguities due to the metastability of the buses 3 and 4 during the transitions 90, visible in
At the end of a period of measurement, the internal memory of the unit 71 contains the raw data relative to each event, i.e., for each event:
An evaluation and reading routine allows the temporal position of each recorded event to be computed. The routine comprises, for each event having generated a trigger signal 6, the following steps:
According to the case, the evaluation and reading routine could be stored in the logical unit 71 and executed by a local processor, or executed by a master processor that can access the raw data stored in the unit 71 over a suitable communication bus, such as for example a bus PCI, VME or VXI.
A second embodiment of the present invention is now described with reference to
In this embodiment, the inventive time converter 20 comprises a generator 810 that produces the two sinusoidal signals 13 and 14 in quadrature that serve as time base for the converter 10. The first sinusoid 13 is also designated by I (In phase) and the second sinusoid 14 by Q (Quadrature). The signals 13 and 14 are generated from an external clock signal 82, as can be seen in
The generator of the signals I and Q 810 is now described with reference to
In a variant embodiment of the generator 810, represented in
The frequency of the reference signals I and Q can be changed to adapt to the measurement conditions, by suitable means not represented.
The digital trigger signal 6 is sent to a coarse measuring system 15, identical to that already described in relation to the first embodiment of this invention represented in
The trigger signal 6 is also sent to a fine measuring device 17, comprising the pulse generator 40 and the two ADCs 51 and 52.
The pulse generator 40 triggers a burst of pulses 8 in correlation with each event marked by a pulse of the trigger signal 6. The signal 8 serves as clock for the two ADCs 51 and 52 that sample the two sinusoidal signals in quadrature 13 and 14 in correlation with each pulse of the signal 8.
Reverting now to the
Although this embodiment of the invention provides for a pair of sinusoids in quadrature as time reference, the invention is not limited by this example. A converter according to the invention could also use two signals offset by an angle different from 90° or of different shapes, for example triangles, instead of the sinusoids 13 and 14.
Since the signal 8 is composed of a burst of pulses regularly spaced in time, each event gives rise to several samples Ii and Qi, and to several values of the phase φi=ω0×ti, where ω0 represents the angular frequency of the sinusoids I and Q and ti the departure time of the ith pulse of the burst of pulses 8. The relative arrival time to of the pulse 6 can thus be determined more accurately, in similar manner to that described in the first embodiment here above, or by averaging or interpolating methods, for example by linear regression of the values φi.
Thanks to the parallel sampling of two sinusoids, it is possible to store a greater number of values Ii and Qi in a time, in comparison to the first embodiment. This variant embodiment of the invention thus offers, for an equivalent resolution, a reduced dead time.
A preferred embodiment of the invention of the present invention is now described with reference to
The generator 181 of the
The real time counter 161 of the time converter 100 counts the number of pulses CK from the beginning to the end of the measurement. Its depth, in bits, determines the range of the TDC, i.e. the maximal duration between the first and the last event recorded by the TDC module. The value of the counter 161 is available on the CTR bus. Typically, a depth of 32 bits for a clock rate CK of 1 GHz and a depth of 4.3 seconds will be chosen, although other values are obviously also possible for these parameters.
The time converter 100 also comprises at least two acquisition channels 99. Several channels can share a single time base circuit 181 and a common counter 161 to constitute a multi-channel TDC capable of sampling several signals at a time, each signal being measured by one of the channels of the TDC.
The digital trigger signal TR is generated from the input signal by the comparator 37, the DAC 35 and the gate 39, as already explained. The signal TR is applied at the clock input of a sweep circuit D 107, allowing a trigger acceptation function to be implemented and giving rise, when the control signal ENA is in mode high, to an accepted trigger signal TRA.
The signal TRA, whose initial flank is synchronous with the event to be measured, triggers a synchronized sine generator (GSS) 140. The circuit 140 is build in similar fashion to the circuit 40 represented in
When TRA switches to high value, the injection of current and the biasing of the transistor are suddenly interrupted, the factor Q then becomes high and the resonator LC enters into weakly damped sinusoidal oscillation. The sinusoidal oscillation SIN is synchronous with TRA and extends over several periods, practically up to the instant when the signal TRA returns to the mode low. This circuit thus memorizes, by the value of its output phase, the arrival instant of the event that has generated the trigger.
In this example, the output of the GS 140 (SIN) is of the type single-ended, though the invention also extends to the case of a differential output.
Unlike the embodiments previously presented, the sinusoidal signal SIN is applied at the digitizing input of an ADC 151. The ADC 151 continuously samples the output of the generator 140, according to the rate imparted by the signal CK present at its clock input.
The circuit 113, composed by the cascade of flip-flops 108 and 109, generates the accepted trigger signal synchronized with the clock TRAS. This circuit comprises at least two D-type flip-flops and has for function to produce a signal whose transitions are synchronous to those of the CK, without metastable states. This signal will be used to freeze the state of the system's real time counter.
The samples measured by the ADC 151 are transmitted to a register of interpolated data (RDI) 185, having content represented by DI in
The selection of events useful for determining the arrival time is effected thanks to the controller of sequence of acquisition 127. This circuit contains a counter for the samples to be accepted for determining the number of samples to be recorded at each event. When this number is reached, the signal RESET resets the sweep circuit 107. The signals TRA and TRAS thus return to mode low, the first immediately and the second after a number of clock cycles determined by the number of D-type flip-flops in the circuit 113.
The controller of sequence of acquisition 127 offers two operating modes that can be selected. In a first mode (multi-hit mode), it resets itself to be ready to accept a new event immediately after a recorded event. In a second operating mode (single-hit mode), it keeps the RESET signal high, thus preventing the acquisition of new events until it receives a new re-initialization command.
The real time register RTR 164 memorizes the state of the bus CTR at the moment of the positive transition of the TRAS. The value recorded in the register 164, represented by RTRC in
With reference now to the chronogram of
The interpolation of the data acquired by the ADC supplies, as in the first embodiment of the invention, the exact time ΔT of the TRA's transition inside the window Zacc.
The samples stored in the register RDI 185 following each trigger pulse are thus given, in the approximation of negligible damping, Q=∞.
EK=A·sin(ω0(k·TS+ΔT))+D (3)
In this expression, the system of equations (2) can be recognized. The system (3) is thus determined if the number N of samples is equal to 4 and over-determined if N>4. In the latter case, it will be possible to use additional information to increase the accuracy of the measurement of ΔT, as in the preceding examples.
In the case where the resonator LC has a factor Q that is real (Q≠∞), the sinusoid generated by the circuit 140 has the shape:
SIN=A·exp(−t/τ)·sin(ω0t+φ0)+D
The unknown quantities to be determined number 5 (A, τ0, ω0, φ0, D) and the algorithm used will be a fit with 5 parameters, allowing ΔT to be determined as soon as N, the number of samples, is greater than or equal to 5.
The end of the interval Zacc coincides with the real time stored in the register RTR 162, so the instant of arrival of an event can be obtained by:
tev=N·TS−ΔT (4)
where TS is the period of the clock signal CK.
The position and the size of the pulse TRAS, corresponding to the acquisition window of the register RDI 162, will be chosen to store a sufficient number of samples Ei, also taking into account the delay introduced by the ADC 151 (pipeline delay) as indicated in
In this example, the elements 107, 113, and 127 essentially have the function of generating the delay signal TRAS to select the events that are really useful for determining the trigger instant of the trigger TR. This selection could however also be performed or completed in a subsequent step, for example by a software element, residing in the control unit of the converter 100, or in an external computer. CE represents a value of a sample counter register comprised in sequence controller 127.
Possibly, one will be able to select only a subset of the samples Ei, for example to avoid using the first sample of the sinusoid (E3 in
The circuits proposed could also function with other wave shapes, different from the sinusoidal shape. Any wave shape that is repetitive and synchronous with a trigger could in principle be used. For example, one could replace the generators 51, 52 and 151 by saw-toothed signal or triangular signal generators.
It has been seen that the time converter of the present invention can advantageously be integrated in a multi-channel device, comprising several channels 99 in a module that can be interfaced with a communication bus. In the case of a multi-channel device, the different channels of a module can be sequenced to achieve a dead time close to zero in mono-channel mode.
The TDC according to the invention can be realized in the shape of a module element, provided with a connector allowing it to be connected to a data bus, such as for example a PCI, VXI or VME bus. In this case, each module constitutes a card having a connector on one side, so that it can be plugged in removable fashion and electrically connected with a motherboard.
The invention has been described hereinabove using specific examples and embodiments; however, it will be understood by those skilled in the art that various alternatives may be used and equivalents may be substituted for elements and/or steps described herein, without deviating from the scope of the invention. Modifications may be necessary to adapt the invention to a particular situation or to particular needs without departing from the scope of the invention. It is intended that the invention not be limited to the particular implementations and embodiments described herein, but that the claims be given their broadest interpretation to cover all embodiments, literal or equivalent, disclosed or not, covered thereby.
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03103642 | Oct 2003 | EP | regional |
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Number | Date | Country | |
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20050122846 A1 | Jun 2005 | US |