Claims
- 1. A method for the high speed deposition of amorphous semiconductor material in deposition apparatus which includes: substrate material; means for introducing reaction materials, including at least one semiconductor material, into the apparatus; a deposition region located downstream of the introducing means, said downstream deposition region including means for decomposing the reaction materials and depositing an amorphous semiconductor layer onto the substrate; and means for evacuating the nondeposited reaction materials from the deposition apparatus; the method including the steps of:
- subjecting substantially all of the reaction materials to the effects of an upstream electromagnetic field in a predeposition region for beginning the decomposition and recombination of the reaction materials at a location upstream of the deposition region;
- introducing a sufficient volume per unit time of reaction meterials to prevent depletion thereof before the reaction materials flow completely through the downstream deposition region; and
- preventing nonuniform stagnation and compression of the reaction materials flowing through the predeposition and deposition regions, whereby the deposition apparatus provides for the high speed deposition of a stable, uniform layer of powder-free semiconductor material.
- 2. A method of claim 1, including the further step of continuously moving the substrate through the deposition apparatus.
- 3. A method as in claim 1, including the further step of introducing silicon into the deposition apparatus as one of the reaction materials.
- 4. A method as in claim 1, including the further step of introducing silicon and a dopant into the deposition apparatus as one of the reaction materials.
- 5. A method as in claim 1, wherein the deposition apparatus includes at least one triad of three deposition chambers, and the method includes the further step of continuously moving the substrate material through each of the deposition chambers.
- 6. A method as in claim 5, including the further step of introducing a silicon alloy and a dopant into the first deposition chamber, a substantially intrinsic silicon alloy into the second deposition chamber and a silicon alloy and a dopant into the third deposition chamber.
- 7. A method as in claim 6, including the further step of introducing at least one density of states reducing element into each of the deposition chambers along with the silicon alloy.
- 8. A method as in claim 5, wherein the deposition apparatus includes three triads of deposition chambers and the method includes the further step of continuously moving an elongated web of substrate material through each of the deposition chambers.
- 9. A method as in claim 8, including the further step of introducing semiconductor materials having different band gaps into each triad of deposition chambers as the reaction material.
- 10. A method as in claim 9, including the further step of introducing at least one density of states reducing element into each of the deposition chambes along with the semiconductor materials.
- 11. A method as in claim 1, including the further step of depositing at least 10 angstroms per second of amorphous semiconductor material onto the substrate material.
- 12. A method as in claim 1, including the further step of depositing at least 20 angstroms per second of amorphous semiconductor material onto the substrate material.
CROSS REFERENCE TO RELATED APPLICATIONS
This patent application is a continuation-in-part of U.S. patent application Ser. No. 452,224 of Prem Nath and Masatsugu Izu filed Dec. 22, 1982 and entitled UPSTREAM CATHODE ASSEMBLY.
US Referenced Citations (2)
Continuation in Parts (1)
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Number |
Date |
Country |
Parent |
452224 |
Dec 1982 |
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