A Workshop on the Future of Design Automation Research<br/>0638675<br/>Ralph Cavin<br/>Semiconductor Research Corporation <br/><br/>ABSTRACT: Design automation, a commercially growing field with unique and strong ties to the academic community, relies for its basic underpinning on research. In turn, design automation tools are at the foundation of the semiconductor industry, and are becoming increasingly important in a world where straightforward scaling is no longer possible and the gains associated with it more elusive. Design tools are becoming increasingly critical to meet performance, power, and reliability targets and to shorten time-to-market.<br/>This workshop, with invited researchers from academia, industry, and government, will work to chart the future directions and needs in design automation, and assess where critical gaps are in supporting this research. In particular, the focus will be on the fundamental and foundational scientific challenges which need to be addressed. In addition to current roadmaps such as the International Technology Roadmap for Semiconductors, the needs documents of the SRC, industry, and other agencies, the workshop will develop a clear statement what unique role NSF can play in the advance of the science undergirding design automation research, and why it should be a national priority.<br/>Some of the questions which the workshop will consider::<br/>What foundational work is necessary so that logic and physical design tools can make breakthroughs to realize their potential instead of incremental improvements?<br/>What will true 3-D design mean for design automation?<br/>How will multigate devices impact CAD requirements?<br/>How will new nanodevices and nanowires change the needs and abilities of design tools?<br/>What role will tools play in creating working systems from unreliable components?<br/>How will the design automation landscape be changed by multicore systems and increased parallelism?<br/>Will formal verification techniques finally develop into a better alternative to simulation?<br/>What new defects will need to be modeled and avoided by design for testability and test methods?