Chin Chang Liao

Person

Shanghai, CN

People

Patents Grantslast 30 patents

Information Patent Grant
System and method for test structure on a wafer
- Patent number 9,472,476
- Issue date Oct 18, 2016
- Semiconductor Manufacturing International (Shanghai) Corporation
- Wang Jian Ping
- G01 - MEASURING TESTING
Information Patent Grant
System and method for I/O ESD protection with floating and/or biase...
- Patent number 8,686,507
- Issue date Apr 1, 2014
- Semiconductor Manufacturing International (Shanghai) Corporation
- Ting Chieh Su
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for test structure on a wafer
- Patent number 8,415,663
- Issue date Apr 9, 2013
- Semiconductor Manufacturing International (Shanghai)
- Wang Jian Ping
- G01 - MEASURING TESTING
Information Patent Grant
System and method for input pin ESD protection with floating and/or...
- Patent number 8,319,286
- Issue date Nov 27, 2012
- Semiconductor Manufacturing International (Shanghai) Corporation
- Ting Chieh Su
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for I/O ESD protection with polysilicon regions f...
- Patent number 8,283,726
- Issue date Oct 9, 2012
- Semiconductor Manufacturing International (Shanghai) Corporation
- Ting Chieh Su
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
System and method for I/O ESD protection with polysilicon regions f...
- Patent number 7,642,602
- Issue date Jan 5, 2010
- Semiconductor Manufacturing International (Shanghai) Corporation
- Ting Chieh Su
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM AND METHOD FOR TEST STRUCTURE ON A WAFER
- Publication number 20130193997
- Publication date Aug 1, 2013
- Semiconductor Manufacturing International (Shanghai) Corporation
- Wang Jian Ping
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND METHOD FOR INPUT PIN ESD PROTECTION WITH FLOATING AND/OR...
- Publication number 20120001261
- Publication date Jan 5, 2012
- Semiconductor Manufacturing International (Shanghai) Corporation
- TING CHIEH SU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM AND METHOD FOR TEST STRUCTURE ON A WAFER
- Publication number 20100164508
- Publication date Jul 1, 2010
- Semiconductor Manufacturing International (Shanghai) Corporation
- WANG JIAN PING
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND METHOD FOR I/O ESD PROTECTION WITH POLYSILICON REGIONS F...
- Publication number 20100059824
- Publication date Mar 11, 2010
- Semiconductor Manufacturing International (Shanghai) Corporation
- TING CHIEH SU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SYSTEM AND METHOD FOR I/O ESD PROTECTION WITH POLYSILICON REGIONS F...
- Publication number 20070284663
- Publication date Dec 13, 2007
- Semiconductor Manufacturing International (Shanghai) Corporation
- Ting Chieh Su
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
System and method for I/O ESD protection with floating and/or biase...
- Publication number 20070164362
- Publication date Jul 19, 2007
- Semiconductor Manufacturing International (Shanghai) Corporation
- Ting Chieh Su
- H01 - BASIC ELECTRIC ELEMENTS

Chin Chang Liao

Person

Patents Grantslast 30 patents

System and method for test structure on a wafer

System and method for I/O ESD protection with floating and/or biase...

System and method for test structure on a wafer

System and method for input pin ESD protection with floating and/or...

System and method for I/O ESD protection with polysilicon regions f...

System and method for I/O ESD protection with polysilicon regions f...

Patents Applicationslast 30 patents

SYSTEM AND METHOD FOR TEST STRUCTURE ON A WAFER

SYSTEM AND METHOD FOR INPUT PIN ESD PROTECTION WITH FLOATING AND/OR...

SYSTEM AND METHOD FOR TEST STRUCTURE ON A WAFER

SYSTEM AND METHOD FOR I/O ESD PROTECTION WITH POLYSILICON REGIONS F...

SYSTEM AND METHOD FOR I/O ESD PROTECTION WITH POLYSILICON REGIONS F...

System and method for I/O ESD protection with floating and/or biase...