Membership
Tour
Register
Log in
John Haywood
Follow
Person
Santa Clara, CA, US
People
Overview
Industries
Organizations
People
Information
Impact
Patents Grants
last 30 patents
Information
Patent Grant
Process for etching a controllable thickness of oxide on an integra...
Patent number
6,759,337
Issue date
Jul 6, 2004
LSI Logic Corporation
Sheldon Aronowitz
H01 - BASIC ELECTRIC ELEMENTS
Information
Patent Grant
PROCESS FOR FORMING THIN GATE OXIDE WITH ENHANCED RELIABILITY BY NI...
Patent number
6,413,881
Issue date
Jul 2, 2002
LSI Logic Corporation
Sheldon Aronowitz
H01 - BASIC ELECTRIC ELEMENTS
Information
Patent Grant
Composite semiconductor gate dielectrics
Patent number
6,087,229
Issue date
Jul 11, 2000
LSI Logic Corporation
Sheldon Aronowitz
H01 - BASIC ELECTRIC ELEMENTS
Information
Patent Grant
Method of forming variable thickness gate dielectrics
Patent number
6,033,998
Issue date
Mar 7, 2000
LSI Logic Corporation
Sheldon Aronowitz
H01 - BASIC ELECTRIC ELEMENTS
Information
Patent Grant
Process for forming photoresist mask over integrated circuit struct...
Patent number
5,902,704
Issue date
May 11, 1999
LSI Logic Corporation
Philippe Schoenborn
G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information
Patent Grant
Process for forming integrated circuit structure with metal silicid...
Patent number
5,851,890
Issue date
Dec 22, 1998
LSI Logic Corporation
Jiunn-Yann Tsai
H01 - BASIC ELECTRIC ELEMENTS
Information
Patent Grant
Diffusion barrier for polysilicon gate electrode of MOS device in i...
Patent number
5,837,598
Issue date
Nov 17, 1998
LSI Logic Corporation
Sheldon Aronowitz
H01 - BASIC ELECTRIC ELEMENTS