Jose L. Neves

Person

Poughkeepsie, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Word embedding model parameter advisor
- Patent number 12,026,462
- Issue date Jul 2, 2024
- International Business Machines Corporation
- Thomas Conti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Query response using semantically similar database records
- Patent number 11,650,987
- Issue date May 16, 2023
- International Business Machines Corporation
- Rajesh Bordawekar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic updating of a word embedding model
- Patent number 11,410,031
- Issue date Aug 9, 2022
- International Business Machines Corporation
- Thomas Conti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Noise impact on function (NIOF) reduction for integrated circuit de...
- Patent number 11,176,301
- Issue date Nov 16, 2021
- International Business Machines Corporation
- Jose Neves
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Net routing for integrated circuit (IC) design
- Patent number 11,030,376
- Issue date Jun 8, 2021
- International Business Machines Corporation
- Jose Neves
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic partition reporting for integrated circuit design
- Patent number 10,885,243
- Issue date Jan 5, 2021
- International Business Machines Corporation
- Jose Neves
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic partition identifiers for integrated circuit design
- Patent number 10,831,953
- Issue date Nov 10, 2020
- International Business Machines Corporation
- Jose Neves
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-fanout latch placement optimization for integrated circuit (I...
- Patent number 10,831,966
- Issue date Nov 10, 2020
- International Business Machines Corporation
- Jose Neves
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel power down processing of integrated circuit design
- Patent number 10,831,938
- Issue date Nov 10, 2020
- International Business Machines Corporation
- Jose Neves
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Resource aware method for optimizing wires for slew, slack, or noise
- Patent number 10,331,840
- Issue date Jun 25, 2019
- International Business Machines Corporation
- Alice H. Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Incremental parasitic extraction for coupled timing and power optim...
- Patent number 10,169,526
- Issue date Jan 1, 2019
- International Business Machines Corporation
- Kerim Kalafala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Simulation of modifications to microprocessor design
- Patent number 9,934,341
- Issue date Apr 3, 2018
- International Business Machines Corporation
- Christopher J. Berry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Simulation of modifications to microprocessor design
- Patent number 9,928,322
- Issue date Mar 27, 2018
- International Business Machines Corporation
- Christopher J. Berry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Incremental parasitic extraction for coupled timing and power optim...
- Patent number 9,858,383
- Issue date Jan 2, 2018
- International Business Machines Corporation
- Kerim Kalafala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Control path power adjustment for chip design
- Patent number 9,734,270
- Issue date Aug 15, 2017
- International Business Machines Corporation
- Christopher J. Berry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Control path power adjustment for chip design
- Patent number 9,703,910
- Issue date Jul 11, 2017
- International Business Machines Corporation
- Christopher J. Berry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing repeater power
- Patent number 9,256,705
- Issue date Feb 9, 2016
- GLOBALFOUNDRIES Inc.
- Paul D. Kartschoke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing repeater power
- Patent number 9,223,918
- Issue date Dec 29, 2015
- GLOBALFOUNDRIES Inc.
- Paul D. Kartschoke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic generation of wire tag lists for a metal stack
- Patent number 9,092,591
- Issue date Jul 28, 2015
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Early design cycle optimization
- Patent number 9,038,009
- Issue date May 19, 2015
- International Business Machines Corporation
- Charles Jay Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic generation of wire tag lists for a metal stack
- Patent number 8,769,468
- Issue date Jul 1, 2014
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Early design cycle optimzation
- Patent number 8,640,075
- Issue date Jan 28, 2014
- International Business Machines Corporation
- Charles Jay Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reduction of logic and delay through latch polarity inversion
- Patent number 8,108,821
- Issue date Jan 31, 2012
- International Business Machines Corporation
- Jonathan Y. Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Minimizing clock uncertainty on clock distribution networks using a...
- Patent number 7,941,689
- Issue date May 10, 2011
- International Business Machines Corporation
- Charlie Chornglii Hwang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and medium for placement which maintain optimized timing beh...
- Patent number 7,921,398
- Issue date Apr 5, 2011
- International Business Machines Corporation
- James J. Curtin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock distribution network wiring structure
- Patent number 7,831,946
- Issue date Nov 9, 2010
- International Business Machines Corporation
- Rick L. Dennis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Chip having timing analysis of paths performed within the chip duri...
- Patent number 7,823,108
- Issue date Oct 26, 2010
- International Business Machines Corporation
- James J. Curtin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for eliminating negative slack in a netlist via transformati...
- Patent number 7,810,062
- Issue date Oct 5, 2010
- International Business Machines Corporation
- James J. Curtin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for placement which maintain optimized behavior, while impr...
- Patent number 7,376,924
- Issue date May 20, 2008
- International Business Machines Corporation
- James J. Curtin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Genie: a method for classification and graphical display of negativ...
- Patent number 7,356,793
- Issue date Apr 8, 2008
- International Business Machines Corporation
- James J. Curtin
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
NET ROUTING FOR INTEGRATED CIRCUIT (IC) DESIGN
- Publication number 20210073347
- Publication date Mar 11, 2021
- International Business Machines Corporation
- Jose Neves
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NOISE IMPACT ON FUNCTION (NIOF) REDUCTION FOR INTEGRATED CIRCUIT DE...
- Publication number 20210073346
- Publication date Mar 11, 2021
- International Business Machines Corporation
- Jose Neves
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
QUERY RESPONSE USING SEMANTICALLY SIMILAR DATABASE RECORDS
- Publication number 20200210431
- Publication date Jul 2, 2020
- International Business Machines Corporation
- Rajesh Bordawekar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WORD EMBEDDING MODEL PARAMETER ADVISOR
- Publication number 20200175390
- Publication date Jun 4, 2020
- International Business Machines Corporation
- Thomas Conti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC UPDATING OF A WORD EMBEDDING MODEL
- Publication number 20200175360
- Publication date Jun 4, 2020
- International Business Machines Corporation
- Thomas Conti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INCREMENTAL PARASITIC EXTRACTION FOR COUPLED TIMING AND POWER OPTIM...
- Publication number 20180068052
- Publication date Mar 8, 2018
- International Business Machines Corporation
- Kerim Kalafala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RESOURCE AWARE METHOD FOR OPTIMIZING WIRES FOR SLEW, SLACK, OR NOISE
- Publication number 20170206286
- Publication date Jul 20, 2017
- International Business Machines Corporation
- Alice H. Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INCREMENTAL PARASITIC EXTRACTION FOR COUPLED TIMING AND POWER OPTIM...
- Publication number 20170177784
- Publication date Jun 22, 2017
- International Business Machines Corporation
- Kerim Kalafala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIMULATION OF MODIFICATIONS TO MICROPROCESSOR DESIGN
- Publication number 20170132341
- Publication date May 11, 2017
- International Business Machines Corporation
- Christopher J. Berry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIMULATION OF MODIFICATIONS TO MICROPROCESSOR DESIGN
- Publication number 20170132340
- Publication date May 11, 2017
- International Business Machines Corporation
- Christopher J. Berry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTROL PATH POWER ADJUSTMENT FOR CHIP DESIGN
- Publication number 20170011156
- Publication date Jan 12, 2017
- International Business Machines Corporation
- Christopher J. Berry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTROL PATH POWER ADJUSTMENT FOR CHIP DESIGN
- Publication number 20170011157
- Publication date Jan 12, 2017
- International Business Machines Corporation
- Christopher J. Berry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Automatic Generation of Wire Tag Lists for a Metal Stack
- Publication number 20140223397
- Publication date Aug 7, 2014
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Automatic Generation of Wire Tag Lists for a Metal Stack
- Publication number 20140195998
- Publication date Jul 10, 2014
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EARLY DESIGN CYCLE OPTIMZATION
- Publication number 20140101629
- Publication date Apr 10, 2014
- International Business Machines Corporation
- Charles Jay Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCING REPEATER POWER
- Publication number 20140088948
- Publication date Mar 27, 2014
- International Business Machines Corporation
- Paul D. Kartschoke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EARLY DESIGN CYCLE OPTIMZATION
- Publication number 20130326450
- Publication date Dec 5, 2013
- International Business Machines Corporation
- Charles Jay Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCING REPEATER POWER
- Publication number 20130275110
- Publication date Oct 17, 2013
- International Business Machines Corporation
- Paul D. Kartschoke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCTION OF LOGIC AND DELAY THROUGH LATCH POLARITY INVERSION
- Publication number 20110173584
- Publication date Jul 14, 2011
- International Business Machines Corporation
- Jonathan Y. Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MINIMIZING CLOCK UNCERTAINTY ON CLOCK DISTRIBUTION NETWORKS USING A...
- Publication number 20090237134
- Publication date Sep 24, 2009
- International Business Machines Corporation
- Charlie Chornglii Hwang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System for Improving a Logic Circuit and Associated Methods
- Publication number 20090106709
- Publication date Apr 23, 2009
- International Business Corporation
- Christopher Carney
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR ELIMINATING NEGATIVE SLACK IN A NETLIST VIA TRANSFORMATI...
- Publication number 20090070715
- Publication date Mar 12, 2009
- International Business Machines Corporation
- James J. Curtin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock Distribution Network Wiring Structure
- Publication number 20090033398
- Publication date Feb 5, 2009
- International Business Machines Corporation
- Rick L. Dennis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
System and Medium for Placement Which Maintain Optimized Timing Beh...
- Publication number 20080163149
- Publication date Jul 3, 2008
- International Business Machines Corporation
- James J. Curtin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Chip Having Timing Analysis of Paths Performed Within the Chip Duri...
- Publication number 20080066036
- Publication date Mar 13, 2008
- International Business Machines Corporation
- James J. Curtin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Chip Having Timing Analysis of Paths Performed Within the Chip Duri...
- Publication number 20080052655
- Publication date Feb 28, 2008
- International Business Machines Corporation
- James J. Curtin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Genie: a method for classification and graphical display of negativ...
- Publication number 20060010410
- Publication date Jan 12, 2006
- International Business Machines Corporation
- James J. Curtin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods for placement which maintain optimized behavior, while impr...
- Publication number 20060010413
- Publication date Jan 12, 2006
- International Business Machines Corporation
- James J. Curtin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method to identify geometrically non-overlapping optimization parti...
- Publication number 20050108665
- Publication date May 19, 2005
- International Business Machines Corporation
- Jose Luis Pontes Corrcia Neves
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of integrated circuit design by selection of noise tolerant...
- Publication number 20020133791
- Publication date Sep 19, 2002
- International Business Machines Corporation
- John M. Cohn
- G06 - COMPUTING CALCULATING COUNTING

Jose L. Neves

Person

Patents Grantslast 30 patents

Word embedding model parameter advisor

Query response using semantically similar database records

Dynamic updating of a word embedding model

Noise impact on function (NIOF) reduction for integrated circuit de...

Net routing for integrated circuit (IC) design

Logic partition reporting for integrated circuit design

Logic partition identifiers for integrated circuit design

Multi-fanout latch placement optimization for integrated circuit (I...

Parallel power down processing of integrated circuit design

Resource aware method for optimizing wires for slew, slack, or noise

Incremental parasitic extraction for coupled timing and power optim...

Simulation of modifications to microprocessor design

Simulation of modifications to microprocessor design

Incremental parasitic extraction for coupled timing and power optim...

Control path power adjustment for chip design

Control path power adjustment for chip design

Reducing repeater power

Reducing repeater power

Automatic generation of wire tag lists for a metal stack

Early design cycle optimization

Automatic generation of wire tag lists for a metal stack

Early design cycle optimzation

Reduction of logic and delay through latch polarity inversion

Minimizing clock uncertainty on clock distribution networks using a...

System and medium for placement which maintain optimized timing beh...

Clock distribution network wiring structure

Chip having timing analysis of paths performed within the chip duri...

Method for eliminating negative slack in a netlist via transformati...

Methods for placement which maintain optimized behavior, while impr...

Genie: a method for classification and graphical display of negativ...

Patents Applicationslast 30 patents

NET ROUTING FOR INTEGRATED CIRCUIT (IC) DESIGN

NOISE IMPACT ON FUNCTION (NIOF) REDUCTION FOR INTEGRATED CIRCUIT DE...

QUERY RESPONSE USING SEMANTICALLY SIMILAR DATABASE RECORDS

WORD EMBEDDING MODEL PARAMETER ADVISOR

DYNAMIC UPDATING OF A WORD EMBEDDING MODEL

INCREMENTAL PARASITIC EXTRACTION FOR COUPLED TIMING AND POWER OPTIM...

RESOURCE AWARE METHOD FOR OPTIMIZING WIRES FOR SLEW, SLACK, OR NOISE

INCREMENTAL PARASITIC EXTRACTION FOR COUPLED TIMING AND POWER OPTIM...

SIMULATION OF MODIFICATIONS TO MICROPROCESSOR DESIGN

SIMULATION OF MODIFICATIONS TO MICROPROCESSOR DESIGN

CONTROL PATH POWER ADJUSTMENT FOR CHIP DESIGN

CONTROL PATH POWER ADJUSTMENT FOR CHIP DESIGN

Automatic Generation of Wire Tag Lists for a Metal Stack

Automatic Generation of Wire Tag Lists for a Metal Stack

EARLY DESIGN CYCLE OPTIMZATION

REDUCING REPEATER POWER

EARLY DESIGN CYCLE OPTIMZATION

REDUCING REPEATER POWER

REDUCTION OF LOGIC AND DELAY THROUGH LATCH POLARITY INVERSION

MINIMIZING CLOCK UNCERTAINTY ON CLOCK DISTRIBUTION NETWORKS USING A...

System for Improving a Logic Circuit and Associated Methods

METHOD FOR ELIMINATING NEGATIVE SLACK IN A NETLIST VIA TRANSFORMATI...

Clock Distribution Network Wiring Structure

System and Medium for Placement Which Maintain Optimized Timing Beh...

Chip Having Timing Analysis of Paths Performed Within the Chip Duri...

Chip Having Timing Analysis of Paths Performed Within the Chip Duri...

Genie: a method for classification and graphical display of negativ...

Methods for placement which maintain optimized behavior, while impr...

Method to identify geometrically non-overlapping optimization parti...

Method of integrated circuit design by selection of noise tolerant...