Michio Nakajima

Person

Hyogo, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Output circuit of semiconductor device having adjustable driving ca...
- Patent number 6,794,909
- Issue date Sep 21, 2004
- Renesas Technology Corp.
- Aki Urakami
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Semiconductor memory device having configuration suited for high in...
- Patent number 6,545,934
- Issue date Apr 8, 2003
- Mitsubishi Denki Kabushiki Kaisha
- Takekazu Yamashita
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit with efficient testing arrangement
- Patent number 6,345,005
- Issue date Feb 5, 2002
- Mitsubishi Denki Kabushiki Kaisha
- Aki Urakami
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor wafer and method of manufacturing the same, and semic...
- Patent number 6,127,694
- Issue date Oct 3, 2000
- Mitsubishi Denki Kabushiki Kaisha
- Michio Nakajima
- G01 - MEASURING TESTING
Information Patent Grant
Semiconductor device test board and method for evaluating semicondu...
- Patent number 6,114,866
- Issue date Sep 5, 2000
- Mitsubishi Electric Systems LSI Design Corporation
- Masaaki Matsuo
- G01 - MEASURING TESTING
Information Patent Grant
Field effect transistor array including doped two-cell isolation re...
- Patent number 6,043,522
- Issue date Mar 28, 2000
- Mitsubishi Electric System Lsi Design Corporation
- Michio Nakajima
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor integrated circuit including a capacitor and a fuse e...
- Patent number 6,040,614
- Issue date Mar 21, 2000
- Mitsubishi Denki Kabushiki Kaisha
- Akira Kitaguchi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor memory device having improved bit line structure
- Patent number 5,973,953
- Issue date Oct 26, 1999
- Mitsubishi Electric System Lsi Design Corporation
- Takekazu Yamashita
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device and method of refreshing semiconductor...
- Patent number 5,926,429
- Issue date Jul 20, 1999
- Mitsubishi Electric System Lsi Design Corporation
- Tsuyoshi Saitoh
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device
- Patent number 5,353,253
- Issue date Oct 4, 1994
- Mitsubishi Denki Kabushiki Kaisha
- Michio Nakajima
- G11 - INFORMATION STORAGE
Information Patent Grant
Redundancy circuit
- Patent number 5,349,555
- Issue date Sep 20, 1994
- Mitsubishi Denki Kabushiki Kaisha
- Michio Nakajima
- G11 - INFORMATION STORAGE
Information Patent Grant
Simplified serial selection circuit for serial access in semiconduc...
- Patent number 5,293,346
- Issue date Mar 8, 1994
- Mitsubishi Denki Kabushiki Kaisha
- Michio Nakajima
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Semiconductor memory device having configuration suited for high in...
- Publication number 20020034116
- Publication date Mar 21, 2002
- Takekazu Yamashita
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated circuit with efficient testing arrangement
- Publication number 20010043485
- Publication date Nov 22, 2001
- Aki Urakami
- G11 - INFORMATION STORAGE

Michio Nakajima

Person

Patents Grantslast 30 patents

Output circuit of semiconductor device having adjustable driving ca...

Semiconductor memory device having configuration suited for high in...

Integrated circuit with efficient testing arrangement

Semiconductor wafer and method of manufacturing the same, and semic...

Semiconductor device test board and method for evaluating semicondu...

Field effect transistor array including doped two-cell isolation re...

Semiconductor integrated circuit including a capacitor and a fuse e...

Semiconductor memory device having improved bit line structure

Semiconductor memory device and method of refreshing semiconductor...

Semiconductor memory device

Redundancy circuit

Simplified serial selection circuit for serial access in semiconduc...

Patents Applicationslast 30 patents

Semiconductor memory device having configuration suited for high in...

Integrated circuit with efficient testing arrangement