Qi-De Qian

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Increasing manufacturing yield of integrated circuits by modifying...
- Patent number 9,798,853
- Issue date Oct 24, 2017
- IYM Technologies LLC
- Qi-De Qian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit having adaptive via sizing
- Patent number 8,959,471
- Issue date Feb 17, 2015
- Qi-De Qtan
- Qi-De Qian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit having direction dependent wiring
- Patent number 8,464,187
- Issue date Jun 11, 2013
- Qi-De Qian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for direction dependent integrated circuit layout
- Patent number 8,266,557
- Issue date Sep 11, 2012
- Qi-De Qian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for optimizing integrated circuit layout
- Patent number 8,176,445
- Issue date May 8, 2012
- Qi-De Qian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for improving manufacturability of integrated dev...
- Patent number 7,698,676
- Issue date Apr 13, 2010
- Qi-De Qian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and system for improving integrated circuit layout
- Patent number 7,448,012
- Issue date Nov 4, 2008
- Qi-De Qian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Soft defect printability simulation and analysis for masks
- Patent number 7,043,071
- Issue date May 9, 2006
- Synopsys, Inc.
- Qi-De Qian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
In-situ balancing for phase-shifting mask
- Patent number 6,660,649
- Issue date Dec 9, 2003
- Intel Corporation
- Giang Dao
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Method and apparatus for physical image based inspection system
- Patent number 6,625,800
- Issue date Sep 23, 2003
- Intel Corporation
- Qi-De Qian
- G01 - MEASURING TESTING
Information Patent Grant
In-situ balancing for phase-shifting mask
- Patent number 6,548,417
- Issue date Apr 15, 2003
- Intel Corporation
- Giang Dao
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Transmission and phase balance for phase-shifting mask
- Patent number 6,458,495
- Issue date Oct 1, 2002
- Intel Corporation
- Wilman Tsai
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method of fabricating next-to-minimum-size transistor gate using ma...
- Patent number 6,022,815
- Issue date Feb 8, 2000
- Intel Corporation
- Brian S. Doyle
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Cascading transistor gate and method for fabricating the same
- Patent number 5,923,981
- Issue date Jul 13, 1999
- Intel Corporation
- Qi-De Qian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for narrow space formation and self-aligned channel implant
- Patent number 5,918,132
- Issue date Jun 29, 1999
- Intel Corporation
- Qi-De Qian
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Using hall effect to monitor current during IDDQ testing of CMOS in...
- Patent number 5,570,034
- Issue date Oct 29, 1996
- Intel Corporation
- Wayne Needham
- G01 - MEASURING TESTING
Information Patent Grant
Reticle with structurally identical inverted phase-shifted features
- Patent number 5,348,826
- Issue date Sep 20, 1994
- Intel Corporation
- Giang T. Dao
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUITS HAVING IN-SITU CONSTRAINTS
- Publication number 20180181699
- Publication date Jun 28, 2018
- IYM TECHNOLOGIES LLC
- Qi-De Qian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUITS HAVING IN-SITU CONSTRAINTS
- Publication number 20180181697
- Publication date Jun 28, 2018
- IYM TECHNOLOGIES LLC
- Qi-De Qian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUITS HAVING IN-SITU CONSTRAINTS
- Publication number 20180181698
- Publication date Jun 28, 2018
- IYM TECHNOLOGIES LLC
- Qi-De Qian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INCREASING MANUFACTURING YIELD OF INTEGRATED CIRCUITS BY MODIFYING...
- Publication number 20180011963
- Publication date Jan 11, 2018
- IYM TECHNOLOGIES LLC
- Qi-De Qian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUITS HAVING IN-SITU CONSTRAINTS
- Publication number 20160371424
- Publication date Dec 22, 2016
- IYM TECHNOLOGIES LLC
- Qi-De Qian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for Selectively Enlarging Via and Contact Sizes
- Publication number 20100162194
- Publication date Jun 24, 2010
- Qi-De Qian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Soft defect printability simulation and analysis for masks
- Publication number 20040052411
- Publication date Mar 18, 2004
- NUMERICAL TECHNOLOGIES, INC.
- Qi-De Qian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
In-situ balancing for phase-shifting mask
- Publication number 20030054262
- Publication date Mar 20, 2003
- Giang Dao
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Application
IN-SITU BALANCING FOR PHASE-SHIFTING MASK
- Publication number 20030054260
- Publication date Mar 20, 2003
- Giang Dao
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC

Person

Patents Grantslast 30 patents

Increasing manufacturing yield of integrated circuits by modifying...

Integrated circuit having adaptive via sizing

Integrated circuit having direction dependent wiring

Method and system for direction dependent integrated circuit layout

Method and system for optimizing integrated circuit layout

Method and system for improving manufacturability of integrated dev...

Methods and system for improving integrated circuit layout

Soft defect printability simulation and analysis for masks

In-situ balancing for phase-shifting mask

Method and apparatus for physical image based inspection system

In-situ balancing for phase-shifting mask

Transmission and phase balance for phase-shifting mask

Method of fabricating next-to-minimum-size transistor gate using ma...

Cascading transistor gate and method for fabricating the same

Method for narrow space formation and self-aligned channel implant

Using hall effect to monitor current during IDDQ testing of CMOS in...

Reticle with structurally identical inverted phase-shifted features

Patents Applicationslast 30 patents

INTEGRATED CIRCUITS HAVING IN-SITU CONSTRAINTS

INTEGRATED CIRCUITS HAVING IN-SITU CONSTRAINTS

INTEGRATED CIRCUITS HAVING IN-SITU CONSTRAINTS

INCREASING MANUFACTURING YIELD OF INTEGRATED CIRCUITS BY MODIFYING...

INTEGRATED CIRCUITS HAVING IN-SITU CONSTRAINTS

Method for Selectively Enlarging Via and Contact Sizes

Soft defect printability simulation and analysis for masks

In-situ balancing for phase-shifting mask

IN-SITU BALANCING FOR PHASE-SHIFTING MASK