Ravindra A. Kapre

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
ESD protection circuit
- Patent number 11,876,090
- Issue date Jan 16, 2024
- Cypress Semiconductor Corporation
- David Michael Rogers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicon-oxide-nitride-oxide-silicon multi-level non-volatile memory...
- Patent number 11,810,616
- Issue date Nov 7, 2023
- Infineon Technologies LLC
- Krishnaswamy Ramkumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
ESD protection circuit
- Patent number 11,521,962
- Issue date Dec 6, 2022
- Cypress Semiconductor Corporation
- David Michael Rogers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicon-oxide-nitride-oxide-silicon based multi-level non-volatile...
- Patent number 11,367,481
- Issue date Jun 21, 2022
- Infineon Technologies LLC
- Venkataraman Prabhakar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Silicon-oxide-nitride-oxide-silicon multi-level non-volatile memory...
- Patent number 11,355,185
- Issue date Jun 7, 2022
- Cypress Semiconductor Corporation
- Krishnaswamy Ramkumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Silicon-oxide-nitride-oxide-silicon based multi level non-volatile...
- Patent number 11,017,851
- Issue date May 25, 2021
- Cypress Semiconductor Corporation
- Venkataraman Prabhakar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory cell array latchup prevention
- Patent number 9,842,629
- Issue date Dec 12, 2017
- Cypress Semiconductor Corporation
- Ravindra M Kapre
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Memory cell array latchup prevention
- Patent number 8,493,804
- Issue date Jul 23, 2013
- Cypress Semiconductor Corporation
- Ravindra M. Kapre
- G11 - INFORMATION STORAGE
Information Patent Grant
Polycrystalline silicon activation RTA
- Patent number 8,252,640
- Issue date Aug 28, 2012
- Ravindra M. Kapre
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integration of non-volatile charge trap memory devices and logic CM...
- Patent number 8,143,129
- Issue date Mar 27, 2012
- Cypress Semiconductor Corporation
- Krishnaswamy Ramkumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integration of non-volatile charge trap memory devices and logic CM...
- Patent number 8,093,128
- Issue date Jan 10, 2012
- Cypress Semiconductor Corporation
- William W. C. Koutny, Jr.
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory cell array
- Patent number 8,045,410
- Issue date Oct 25, 2011
- Cypress Semiconductor Corporation
- Ravindra M. Kapre
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell array latchup prevention
- Patent number 7,773,442
- Issue date Aug 10, 2010
- Cypress Semiconductor Corporation
- Ravindra M. Kapre
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques for improving negative bias temperature instability (NBT...
- Patent number 7,629,653
- Issue date Dec 8, 2009
- Cypress Semiconductor Corporation
- Sharmin Sadoughi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques for improving negative bias temperature instability (NBT...
- Patent number 7,256,087
- Issue date Aug 14, 2007
- Cypress Semiconductor Corporation
- Sharmin Sadoughi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for etching a controllable thickness of oxide on an integra...
- Patent number 6,759,337
- Issue date Jul 6, 2004
- LSI Logic Corporation
- Sheldon Aronowitz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Buried channel devices and a process for their fabrication simultan...
- Patent number 6,747,318
- Issue date Jun 8, 2004
- LSI Logic Corporation
- Ravindra M. Kapre
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
METHOD OF REDUCING SILICON OXYNITRIDE GATE INSULATOR THICKNESS IN S...
- Patent number 6,656,805
- Issue date Dec 2, 2003
- LSI Logic Corporation
- Arvind Kamath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
METHOD OF REDUCING SILICON OXYNITRIDE GATE INSULATOR THICKNESS IN S...
- Patent number 6,521,549
- Issue date Feb 18, 2003
- LSI Logic Corporation
- Arvind Kamath
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
PROCESS FOR FORMING THIN GATE OXIDE WITH ENHANCED RELIABILITY BY NI...
- Patent number 6,413,881
- Issue date Jul 2, 2002
- LSI Logic Corporation
- Sheldon Aronowitz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Formation of integrated circuit structure using one or more silicon...
- Patent number 6,331,468
- Issue date Dec 18, 2001
- LSI Logic Corporation
- Sheldon Aronowitz
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
ESD PROTECTION CIRCUIT
- Publication number 20230343779
- Publication date Oct 26, 2023
- CYPRESS SEMICONDUCTOR CORPORATION
- David Michael Rogers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SILICON-OXIDE-NITRIDE-OXIDE-SILICON MULTI-LEVEL NON-VOLATILE MEMORY...
- Publication number 20220359006
- Publication date Nov 10, 2022
- Infineon Technologies LLC
- Krishnaswamy Ramkumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SILICON-OXIDE-NITRIDE-OXIDE-SILICON BASED MULTI-LEVEL NON-VOLATILE...
- Publication number 20220284951
- Publication date Sep 8, 2022
- Infineon Technologies LLC
- Venkatraman Prabhakar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SILICON-OXIDE-NITRIDE-OXIDE-SILICON BASED MULTI-LEVEL NON-VOLATILE...
- Publication number 20210350850
- Publication date Nov 11, 2021
- CYPRESS SEMICONDUCTOR CORPORATION
- Venkataraman Prabhakar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMBINED POSITIVE AND NEGATIVE VOLTAGE ELECTROSTATIC DISCHARGE (ESD...
- Publication number 20210344193
- Publication date Nov 4, 2021
- CYPRESS SEMICONDUCTOR CORPORATION
- David Michael Rogers
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SILICON-OXIDE-NITRIDE-OXIDE-SILICON BASED MULTI-LEVEL NON-VOLATILE...
- Publication number 20210158868
- Publication date May 27, 2021
- CYPRESS SEMICONDUCTOR CORPORATION
- Venkataraman Prabhakar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SILICON-OXIDE-NITRIDE-OXIDE-SILICON MULTI-LEVEL NON-VOLATILE MEMORY...
- Publication number 20210159346
- Publication date May 27, 2021
- CYPRESS SEMICONDUCTOR CORPORATION
- Krishnaswamy Ramkumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CELL ARRAY LATCHUP PREVENTION
- Publication number 20140211547
- Publication date Jul 31, 2014
- CYPRESS SEMICONDUCTOR CORPORATION
- Ravindra M Kapre
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CELL ARRAY LATCHUP PREVENTION
- Publication number 20140098598
- Publication date Apr 10, 2014
- CYPRESS SEMICONDUCTOR CORPORATION
- RavIndra Kapre
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CELL ARRAY LATCHUP PREVENTION
- Publication number 20130135954
- Publication date May 30, 2013
- CYPRESS SEMICONDUCTOR CORPORATION
- Ravindra M. Kapre
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Cell Array
- Publication number 20090213677
- Publication date Aug 27, 2009
- Ravindra M. Kapre
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATION OF NON-VOLATILE CHARGE TRAP MEMORY DEVICES AND LOGIC CM...
- Publication number 20080296661
- Publication date Dec 4, 2008
- Krishnaswamy Ramkumar
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATION OF NON-VOLATILE CHARGE TRAP MEMORY DEVICES AND LOGIC CM...
- Publication number 20080293207
- Publication date Nov 27, 2008
- William W.C. Koutny, JR.
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Shared contact structures for integrated circuits
- Publication number 20070210339
- Publication date Sep 13, 2007
- Geethakrishnan Narasimhan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Memory cell array latchup prevention
- Publication number 20050286295
- Publication date Dec 29, 2005
- Ravindra M. Kapre
- G11 - INFORMATION STORAGE
Information Patent Application
Method of reducing silicone oxynitride gate insulator thickness in...
- Publication number 20030077866
- Publication date Apr 24, 2003
- Arvind Kamath
- H01 - BASIC ELECTRIC ELEMENTS

Ravindra A. Kapre

Person

Patents Grantslast 30 patents

ESD protection circuit

Silicon-oxide-nitride-oxide-silicon multi-level non-volatile memory...

ESD protection circuit

Silicon-oxide-nitride-oxide-silicon based multi-level non-volatile...

Silicon-oxide-nitride-oxide-silicon multi-level non-volatile memory...

Silicon-oxide-nitride-oxide-silicon based multi level non-volatile...

Memory cell array latchup prevention

Memory cell array latchup prevention

Polycrystalline silicon activation RTA

Integration of non-volatile charge trap memory devices and logic CM...

Integration of non-volatile charge trap memory devices and logic CM...

Memory cell array

Memory cell array latchup prevention

Techniques for improving negative bias temperature instability (NBT...

Techniques for improving negative bias temperature instability (NBT...

Process for etching a controllable thickness of oxide on an integra...

Buried channel devices and a process for their fabrication simultan...

METHOD OF REDUCING SILICON OXYNITRIDE GATE INSULATOR THICKNESS IN S...

METHOD OF REDUCING SILICON OXYNITRIDE GATE INSULATOR THICKNESS IN S...

PROCESS FOR FORMING THIN GATE OXIDE WITH ENHANCED RELIABILITY BY NI...

Formation of integrated circuit structure using one or more silicon...

Patents Applicationslast 30 patents

ESD PROTECTION CIRCUIT

SILICON-OXIDE-NITRIDE-OXIDE-SILICON MULTI-LEVEL NON-VOLATILE MEMORY...

SILICON-OXIDE-NITRIDE-OXIDE-SILICON BASED MULTI-LEVEL NON-VOLATILE...

SILICON-OXIDE-NITRIDE-OXIDE-SILICON BASED MULTI-LEVEL NON-VOLATILE...

COMBINED POSITIVE AND NEGATIVE VOLTAGE ELECTROSTATIC DISCHARGE (ESD...

SILICON-OXIDE-NITRIDE-OXIDE-SILICON BASED MULTI-LEVEL NON-VOLATILE...

SILICON-OXIDE-NITRIDE-OXIDE-SILICON MULTI-LEVEL NON-VOLATILE MEMORY...

MEMORY CELL ARRAY LATCHUP PREVENTION

MEMORY CELL ARRAY LATCHUP PREVENTION

MEMORY CELL ARRAY LATCHUP PREVENTION

Memory Cell Array

INTEGRATION OF NON-VOLATILE CHARGE TRAP MEMORY DEVICES AND LOGIC CM...

INTEGRATION OF NON-VOLATILE CHARGE TRAP MEMORY DEVICES AND LOGIC CM...

Shared contact structures for integrated circuits

Memory cell array latchup prevention

Method of reducing silicone oxynitride gate insulator thickness in...