Steven R. Carlough

Person

Wappingers Falls, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Host synchronized autonomous data chip address sequencer for a dist...
- Patent number 11,687,254
- Issue date Jun 27, 2023
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Address/command chip controlled data chip address sequencing for a...
- Patent number 11,587,600
- Issue date Feb 21, 2023
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Address/command chip synchronized autonomous data chip address sequ...
- Patent number 11,379,123
- Issue date Jul 5, 2022
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Speculative bank activate dynamic random access memory (DRAM) sched...
- Patent number 11,269,561
- Issue date Mar 8, 2022
- International Business Machines Corporation
- Jie Zheng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing latency of memory read operations returning data on a read...
- Patent number 11,099,601
- Issue date Aug 24, 2021
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Use of a cyclic redundancy code multiple-input shift register to pr...
- Patent number 11,088,782
- Issue date Aug 10, 2021
- International Business Machines Corporation
- Steven R. Carlough
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Speculative bank activate dynamic random access memory (DRAM) sched...
- Patent number 11,042,325
- Issue date Jun 22, 2021
- International Business Machines Corporation
- Jie Zheng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Address/command chip synchronized autonomous data chip address sequ...
- Patent number 10,976,939
- Issue date Apr 13, 2021
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Residue prediction of packed data
- Patent number 10,929,213
- Issue date Feb 23, 2021
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Residue prediction of packed data
- Patent number 10,915,385
- Issue date Feb 9, 2021
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing chip latency at a clock boundary by reference clock phase...
- Patent number 10,771,068
- Issue date Sep 8, 2020
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Host controlled data chip address sequencing for a distributed memo...
- Patent number 10,747,442
- Issue date Aug 18, 2020
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interface scheduler for a distributed memory system
- Patent number 10,740,031
- Issue date Aug 11, 2020
- International Business Machines Corporation
- Jie Zheng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Convert to zoned format from decimal floating point format
- Patent number 10,725,780
- Issue date Jul 28, 2020
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Convert to zoned format from decimal floating point format
- Patent number 10,719,324
- Issue date Jul 21, 2020
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing latency of memory read operations returning data on a read...
- Patent number 10,698,440
- Issue date Jun 30, 2020
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stochastic rounding floating-point multiply instruction using entro...
- Patent number 10,671,347
- Issue date Jun 2, 2020
- International Business Machines Corporation
- Jonathan D. Bradbury
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Combined residue circuit protecting binary and decimal data
- Patent number 10,649,738
- Issue date May 12, 2020
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Register access in a distributed memory buffer system
- Patent number 10,642,535
- Issue date May 5, 2020
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable linear feedback shift register
- Patent number 10,613,861
- Issue date Apr 7, 2020
- International Business Machines Corporation
- Jonathan D. Bradbury
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel decimal multiplication hardware with a 3x generator
- Patent number 10,572,223
- Issue date Feb 25, 2020
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Use of a cyclic redundancy code multiple-input shift register to pr...
- Patent number 10,541,782
- Issue date Jan 21, 2020
- International Business Machines Corporation
- Steven R. Carlough
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Host synchronized autonomous data chip address sequencer for a dist...
- Patent number 10,534,555
- Issue date Jan 14, 2020
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamically adjustable cyclic redundancy code types
- Patent number 10,530,396
- Issue date Jan 7, 2020
- International Business Machines Corporation
- Steven R. Carlough
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dynamically adjustable cyclic redundancy code rates
- Patent number 10,530,523
- Issue date Jan 7, 2020
- International Business Machines Corporation
- Steven R. Carlough
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Address/command chip synchronized autonomous data chip address sequ...
- Patent number 10,489,069
- Issue date Nov 26, 2019
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stochastic rounding floating-point add instruction using entropy fr...
- Patent number 10,489,153
- Issue date Nov 26, 2019
- International Business Machines Corporation
- Jonathan D. Bradbury
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Management of resources within a computing environment
- Patent number 10,489,209
- Issue date Nov 26, 2019
- International Business Machines Corporation
- Fadi Y. Busaba
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stochastic rounding floating-point add instruction using entropy fr...
- Patent number 10,489,152
- Issue date Nov 26, 2019
- International Business Machines Corporation
- Jonathan D. Bradbury
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stochastic rounding floating-point multiply instruction using entro...
- Patent number 10,445,066
- Issue date Oct 15, 2019
- International Business Machines Corporation
- Jonathan D. Bradbury
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
BIT LINE ALIGNMENT FOR THE REDUCTION OF SOFT ERRORS
- Publication number 20240184971
- Publication date Jun 6, 2024
- International Business Machines Corporation
- K. Paul Muller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADDRESS/COMMAND CHIP SYNCHRONIZED AUTONOMOUS DATA CHIP ADDRESS SEQU...
- Publication number 20210191630
- Publication date Jun 24, 2021
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPECULATIVE BANK ACTIVATE DYNAMIC RANDOM ACCESS MEMORY (DRAM) SCHED...
- Publication number 20210109680
- Publication date Apr 15, 2021
- International Business Machines Corporation
- Jie ZHENG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPECULATIVE BANK ACTIVATE DYNAMIC RANDOM ACCESS MEMORY (DRAM) SCHED...
- Publication number 20210042058
- Publication date Feb 11, 2021
- International Business Machines Corporation
- Jie ZHENG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USE OF A CYCLIC REDUNDANCY CODE MULTIPLE-INPUT SHIFT REGISTER TO PR...
- Publication number 20200119843
- Publication date Apr 16, 2020
- International Business Machines Corporation
- Steven R. Carlough
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
INTERFACE SCHEDULER FOR A DISTRIBUTED MEMORY SYSTEM
- Publication number 20200097214
- Publication date Mar 26, 2020
- International Business Machines Corporation
- Jie Zheng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HOST SYNCHRONIZED AUTONOMOUS DATA CHIP ADDRESS SEQUENCER FOR A DIST...
- Publication number 20200073565
- Publication date Mar 5, 2020
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADDRESS/COMMAND CHIP SYNCHRONIZED AUTONOMOUS DATA CHIP ADDRESS SEQU...
- Publication number 20200042205
- Publication date Feb 6, 2020
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCING LATENCY OF MEMORY READ OPERATIONS RETURNING DATA ON A READ...
- Publication number 20190384352
- Publication date Dec 19, 2019
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPERATION OF A MULTI-SLICE PROCESSOR IMPLEMENTING DATAPATH STEERING
- Publication number 20190294571
- Publication date Sep 26, 2019
- International Business Machines Corporation
- STEVEN R. CARLOUGH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCING CHIP LATENCY AT A CLOCK BOUNDARY BY REFERENCE CLOCK PHASE...
- Publication number 20190260380
- Publication date Aug 22, 2019
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Address/Command Chip Controlled Data Chip Address Sequencing for a...
- Publication number 20190252010
- Publication date Aug 15, 2019
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMBINED RESIDUE CIRCUIT PROTECTING BINARY AND DECIMAL DATA
- Publication number 20190235841
- Publication date Aug 1, 2019
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Register Access in a Distributed Memory Buffer System
- Publication number 20190227741
- Publication date Jul 25, 2019
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLEL DECIMAL MULTIPLICATION HARDWARE WITH A 3X GENERATOR
- Publication number 20190212983
- Publication date Jul 11, 2019
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCING LATENCY OF MEMORY READ OPERATIONS RETURNING DATA ON A READ...
- Publication number 20190212769
- Publication date Jul 11, 2019
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
JTAG SUPPORT OVER A BROADCAST BUS IN A DISTRIBUTED MEMORY BUFFER SY...
- Publication number 20190170819
- Publication date Jun 6, 2019
- International Business Machines Corporation
- Logan I. Friedman
- G01 - MEASURING TESTING
Information Patent Application
Host Controlled Data Chip Address Sequencing for a Distributed Memo...
- Publication number 20190163362
- Publication date May 30, 2019
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Address/Command Chip Synchronized Autonomous Data Chip Address Sequ...
- Publication number 20190163378
- Publication date May 30, 2019
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Host Synchronized Autonomous Data Chip Address Sequencer for A Dist...
- Publication number 20190163384
- Publication date May 30, 2019
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Address/Command Chip Controlled Data Chip Address Sequencing for A...
- Publication number 20190163383
- Publication date May 30, 2019
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLEL DECIMAL MULTIPLICATION HARDWARE WITH A 3X GENERATOR
- Publication number 20190163445
- Publication date May 30, 2019
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMICALLY ADJUSTABLE CYCLIC REDUNDANCY CODE TYPES
- Publication number 20190158125
- Publication date May 23, 2019
- International Business Machines Corporation
- Steven R. Carlough
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DYNAMICALLY ADJUSTABLE CYCLIC REDUNDANCY CODE RATES
- Publication number 20190158218
- Publication date May 23, 2019
- International Business Machines Corporation
- Steven R. Carlough
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
USE OF A CYCLIC REDUNDANCY CODE MULTIPLE-INPUT SHIFT REGISTER TO PR...
- Publication number 20190158223
- Publication date May 23, 2019
- International Business Machines Corporation
- Steven R. Carlough
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
USE OF MULTIPLE CYCLIC REDUNDANCY CODES FOR OPTIMIZED FAIL ISOLATION
- Publication number 20190158126
- Publication date May 23, 2019
- International Business Machines Corporation
- Steven R. Carlough
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PARTIAL DATA REPLAY IN A DISTRIBUTED MEMORY BUFFER SYSTEM
- Publication number 20190114091
- Publication date Apr 18, 2019
- International Business Machines Corporation
- Susan M. Eickhoff
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REPRODUCIBLE STOCHASTIC ROUNDING FOR OUT OF ORDER PROCESSORS
- Publication number 20180329683
- Publication date Nov 15, 2018
- International Business Machines Corporation
- Jonathan D. Bradbury
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Residue Prediction of Packed Data
- Publication number 20180276545
- Publication date Sep 27, 2018
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Residue Prediction of Packed Data
- Publication number 20180276547
- Publication date Sep 27, 2018
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING

Steven R. Carlough

Person

Patents Grantslast 30 patents

Host synchronized autonomous data chip address sequencer for a dist...

Address/command chip controlled data chip address sequencing for a...

Address/command chip synchronized autonomous data chip address sequ...

Speculative bank activate dynamic random access memory (DRAM) sched...

Reducing latency of memory read operations returning data on a read...

Use of a cyclic redundancy code multiple-input shift register to pr...

Speculative bank activate dynamic random access memory (DRAM) sched...

Address/command chip synchronized autonomous data chip address sequ...

Residue prediction of packed data

Residue prediction of packed data

Reducing chip latency at a clock boundary by reference clock phase...

Host controlled data chip address sequencing for a distributed memo...

Interface scheduler for a distributed memory system

Convert to zoned format from decimal floating point format

Convert to zoned format from decimal floating point format

Reducing latency of memory read operations returning data on a read...

Stochastic rounding floating-point multiply instruction using entro...

Combined residue circuit protecting binary and decimal data

Register access in a distributed memory buffer system

Programmable linear feedback shift register

Parallel decimal multiplication hardware with a 3x generator

Use of a cyclic redundancy code multiple-input shift register to pr...

Host synchronized autonomous data chip address sequencer for a dist...

Dynamically adjustable cyclic redundancy code types

Dynamically adjustable cyclic redundancy code rates

Address/command chip synchronized autonomous data chip address sequ...

Stochastic rounding floating-point add instruction using entropy fr...

Management of resources within a computing environment

Stochastic rounding floating-point add instruction using entropy fr...

Stochastic rounding floating-point multiply instruction using entro...

Patents Applicationslast 30 patents

BIT LINE ALIGNMENT FOR THE REDUCTION OF SOFT ERRORS

ADDRESS/COMMAND CHIP SYNCHRONIZED AUTONOMOUS DATA CHIP ADDRESS SEQU...

SPECULATIVE BANK ACTIVATE DYNAMIC RANDOM ACCESS MEMORY (DRAM) SCHED...

SPECULATIVE BANK ACTIVATE DYNAMIC RANDOM ACCESS MEMORY (DRAM) SCHED...

USE OF A CYCLIC REDUNDANCY CODE MULTIPLE-INPUT SHIFT REGISTER TO PR...

INTERFACE SCHEDULER FOR A DISTRIBUTED MEMORY SYSTEM

HOST SYNCHRONIZED AUTONOMOUS DATA CHIP ADDRESS SEQUENCER FOR A DIST...

ADDRESS/COMMAND CHIP SYNCHRONIZED AUTONOMOUS DATA CHIP ADDRESS SEQU...

REDUCING LATENCY OF MEMORY READ OPERATIONS RETURNING DATA ON A READ...

OPERATION OF A MULTI-SLICE PROCESSOR IMPLEMENTING DATAPATH STEERING

REDUCING CHIP LATENCY AT A CLOCK BOUNDARY BY REFERENCE CLOCK PHASE...

Address/Command Chip Controlled Data Chip Address Sequencing for a...

COMBINED RESIDUE CIRCUIT PROTECTING BINARY AND DECIMAL DATA

Register Access in a Distributed Memory Buffer System

PARALLEL DECIMAL MULTIPLICATION HARDWARE WITH A 3X GENERATOR

REDUCING LATENCY OF MEMORY READ OPERATIONS RETURNING DATA ON A READ...

JTAG SUPPORT OVER A BROADCAST BUS IN A DISTRIBUTED MEMORY BUFFER SY...

Host Controlled Data Chip Address Sequencing for a Distributed Memo...

Address/Command Chip Synchronized Autonomous Data Chip Address Sequ...

Host Synchronized Autonomous Data Chip Address Sequencer for A Dist...

Address/Command Chip Controlled Data Chip Address Sequencing for A...

PARALLEL DECIMAL MULTIPLICATION HARDWARE WITH A 3X GENERATOR

DYNAMICALLY ADJUSTABLE CYCLIC REDUNDANCY CODE TYPES

DYNAMICALLY ADJUSTABLE CYCLIC REDUNDANCY CODE RATES

USE OF A CYCLIC REDUNDANCY CODE MULTIPLE-INPUT SHIFT REGISTER TO PR...

USE OF MULTIPLE CYCLIC REDUNDANCY CODES FOR OPTIMIZED FAIL ISOLATION

PARTIAL DATA REPLAY IN A DISTRIBUTED MEMORY BUFFER SYSTEM

REPRODUCIBLE STOCHASTIC ROUNDING FOR OUT OF ORDER PROCESSORS

Residue Prediction of Packed Data

Residue Prediction of Packed Data