Vasudeva M. Kamath

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Methods for incremental circuit physical synthesis
- Patent number 10,936,772
- Issue date Mar 2, 2021
- Altera Corporation
- Mahesh A. Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing rewind structural verification...
- Patent number 10,922,461
- Issue date Feb 16, 2021
- Intel Corporation
- Mahesh A. Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for reducing constraints during rewind structu...
- Patent number 10,489,535
- Issue date Nov 26, 2019
- Intel Corporation
- Mahesh A. Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Retiming with fixed power-up states
- Patent number 10,296,701
- Issue date May 21, 2019
- Altera Corporation
- Mahesh A. Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Retiming with programmable power-up states
- Patent number 10,255,404
- Issue date Apr 9, 2019
- Altera Corporation
- Mahesh A. Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit retiming with selective modeling of flip-flop se...
- Patent number 10,162,918
- Issue date Dec 25, 2018
- Altera Corporation
- Mahesh A. Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing rewind structural verification...
- Patent number 10,157,247
- Issue date Dec 18, 2018
- Intel Corporation
- Mahesh A. Iyer
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND APPARATUS FOR PERFORMING REWIND STRUCTURAL VERIFICATION...
- Publication number 20190102497
- Publication date Apr 4, 2019
- Intel Corporation
- Mahesh A. Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Performing Rewind Structural Verification...
- Publication number 20180018417
- Publication date Jan 18, 2018
- Intel Corporation
- Mahesh A. Iyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Reducing Constraints During Rewind Structu...
- Publication number 20180018416
- Publication date Jan 18, 2018
- Intel Corporation
- Mahesh A. Iyer
- G06 - COMPUTING CALCULATING COUNTING

Vasudeva M. Kamath

Person

Patents Grantslast 30 patents

Methods for incremental circuit physical synthesis

Method and apparatus for performing rewind structural verification...

Method and apparatus for reducing constraints during rewind structu...

Retiming with fixed power-up states

Retiming with programmable power-up states

Integrated circuit retiming with selective modeling of flip-flop se...

Method and apparatus for performing rewind structural verification...

Patents Applicationslast 30 patents

METHOD AND APPARATUS FOR PERFORMING REWIND STRUCTURAL VERIFICATION...

Method and Apparatus for Performing Rewind Structural Verification...

Method and Apparatus for Reducing Constraints During Rewind Structu...