a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time

Industry

CPC
H03L7/197

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HELECTRICITY H03Electronic circuits H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES H03L7/00Automatic control of frequency or phase Synchronisation

Current Industry

H03L7/197a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time

Industries

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Patents Grantslast 30 patents

Information Patent Grant
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- Issue date Nov 19, 2024
- University of Electronic Science and Technology of China
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- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
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Information Patent Grant
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Information Patent Grant
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Information Patent Grant
Generating divided signals from phase-locked loop (PLL) output when...
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Information Patent Grant
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Information Patent Grant
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Information Patent Grant
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Information Patent Grant
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Information Patent Grant
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Information Patent Grant
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Information Patent Grant
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Apparatus for digital frequency synthesizer with sigma-delta modula...
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Information Patent Grant
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Information Patent Grant
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Information Patent Grant
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- Issue date Aug 15, 2023
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Information Patent Grant
Phase lock loop (PLL) synchronization
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Information Patent Grant
Reducing noise contribution in compensating for unequal successive...
- Patent number 11,711,087
- Issue date Jul 25, 2023
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Information Patent Grant
Systems for and methods of fractional frequency division
- Patent number 11,683,048
- Issue date Jun 20, 2023
- Avago Technologies International Sales Pte. Limited
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GRANULAR CLOCK FREQUENCY DIVISION USING DITHERING MECHANISM
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LOW-NOISE MILLIMETER-WAVE FRACTIONAL-N FREQUENCY SYNTHESIZER
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DIVIDED QUAD CLOCK-BASED INTER-DIE CLOCKING IN A THREE-DIMENSIONAL...
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- H03 - BASIC ELECTRONIC CIRCUITRY
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Information Patent Application
OSCILLATOR
- Publication number 20230065998
- Publication date Mar 2, 2023
- SEIKO EPSON CORPORATION
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- H03 - BASIC ELECTRONIC CIRCUITRY

a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Low-noise millimeter-wave fractional-N frequency synthesizer

Generating divided signals from phase-locked loop (PLL) output when...

Pulse elimination circuit, voltage detection circuit and detecting...

Fractional divider with duty cycle regulation and low subharmonic c...

Time-to-digital converter and calibration

Reducing non-linearities of a phase rotator

Apparatus and method to mitigate phase frequency modulation due to...

Dual-MEMS device with temperature correction of MEMS output based o...

Generating divided signals from phase-locked loop (PLL) output when...

Partial-fractional phase-locked loop with sigma delta modulator and...

Divided quad clock-based inter-die clocking in a three-dimensional...

Granular clock frequency division using dithering mechanism

Device, method and storage medium for frequency calibration for vol...

Oscillator

Fast switching of output frequency of a phase locked loop (PLL)

SerDes module clock network architecture

Low jitter PLL

Radio-frequency (RF) apparatus for digital frequency synthesizer in...

Oscillator

Apparatus for digital frequency synthesizer with sigma-delta modula...

Fractional frequency synthesis by sigma-delta modulating frequency...

Circuitry and methods for fractional division of high-frequency clo...

Fractional divider with phase shifter and fractional phase locked l...

Fractional phase locked loop (PLL) with digital control driven by c...

Serializer/deserializer (SerDes) lanes with lane-by-lane datarate i...

Clock and data recovery lock detection circuit for verifying lock c...

Clock and data recovery devices with fractional-N PLL

Phase lock loop (PLL) synchronization

Reducing noise contribution in compensating for unequal successive...

Systems for and methods of fractional frequency division

Patents Applicationslast 30 patents

LINEARITY CALIBRATION METHOD AND APPARATUS FOR DTC, AND DIGITAL PHA...

UTILIZE THE VOLTAGE-CONTROLLED OSCILLATOR TO CONTINUOUSLY OUTPUT SI...

Reducing non-linearities of a phase rotator

DIVIDED QUAD CLOCK-BASED INTER-DIE CLOCKING IN A THREE-DIMENSIONAL...

PHASE-LOCKED LOOP, RADAR SYSTEM AND METHOD FOR RANDOMIZING INITIAL...

GENERATING DIVIDED SIGNALS FROM PHASE-LOCKED LOOP (PLL) OUTPUT WHEN...

SYNCHRONIZING MULTIPLE PHASE-LOCKED LOOP CIRCUITS

LOW JITTER PLL

GRANULAR CLOCK FREQUENCY DIVISION USING DITHERING MECHANISM

PULSE ELIMINATION CIRCUIT, VOLTAGE DETECTION CIRCUIT AND DETECTING...

Partial-Fractional Phase-locked Loop with Sigma Delta Modulator and...

Partial-Fractional Phase-locked Loop with Sigma Delta Modulator and...

LOW-NOISE MILLIMETER-WAVE FRACTIONAL-N FREQUENCY SYNTHESIZER

SEMICONDUCTOR DEVICE

PHASE LOCK LOOP (PLL) SYNCHRONIZATION

FRACTIONAL DIVIDER WITH DUTY CYCLE REGULATION AND LOW SUBHARMONIC C...

DIVIDED QUAD CLOCK-BASED INTER-DIE CLOCKING IN A THREE-DIMENSIONAL...

Digitally Augmented Analog Phase Locked Loop with Accurate Bandwidth

SYSTEMS FOR AND METHODS OF FRACTIONAL FREQUENCY DIVISION

RADIO DEVICE WITH RESONATOR

FRACTIONAL PHASE LOCKED LOOP (PLL) WITH DIGITAL CONTROL DRIVEN BY C...

FRACTIONAL DIVIDER WITH PHASE SHIFTER AND FRACTIONAL PHASE LOCKED L...

LOW NOISE PHASE LOCK LOOP (PLL) CIRCUIT

ADAPTIVE CYCLIC DELAY LINE FOR FRACTIONAL-N PLL

GENERATING DIVIDED SIGNALS FROM PHASE-LOCKED LOOP (PLL) OUTPUT WHEN...

CIRCUITRY AND METHODS FOR FRACTIONAL DIVISION OF HIGH-FREQUENCY CLO...

FAST SWITCHING OF OUTPUT FREQUENCY OF A PHASE LOCKED LOOP (PLL)

SERDES MODULE CLOCK NETWORK ARCHITECTURE

CALIBRATION FOR DTC FRACTIONAL FREQUENCY SYNTHESIS

OSCILLATOR