Adding Subtracting

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CPC
G06F7/494

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Parent Industries

GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled

Current Industry

G06F7/494Adding Subtracting

Industries

Patents Grantslast 30 patents

Information Patent Grant
Decimal adder with end around carry
- Patent number 8,554,822
- Issue date Oct 8, 2013
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Binary coded decimal addition
- Patent number 7,991,819
- Issue date Aug 2, 2011
- International Business Machines Corporation
- Neelamekakannan Alagarsamy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Binary coded decimal addition
- Patent number 7,299,254
- Issue date Nov 20, 2007
- International Business Machines Corporation
- Neelamekakannan Alagarsamy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Binary and decimal adder unit
- Patent number 6,292,819
- Issue date Sep 18, 2001
- International Business Machines Corporation
- Wolfgang Bultmann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit arrangement for adding or subtracting operands coded in BCD...
- Patent number 5,146,423
- Issue date Sep 8, 1992
- Siemens Aktiengesellschaft
- Horst Fischer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit arrangement for decimal arithmetic
- Patent number 5,086,406
- Issue date Feb 4, 1992
- NEC Corporation
- Shinichi Okugawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast BCD/binary adder
- Patent number 5,007,010
- Issue date Apr 9, 1991
- Unisys Corp. (Formerly Burroughs Corp.)
- Laurence P. Flora
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Predetermination of result conditions of decimal operations
- Patent number 4,890,253
- Issue date Dec 26, 1989
- International Business Machines Corporation
- John D. Jabusch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High-speed binary and decimal arithmetic logic unit
- Patent number 4,866,656
- Issue date Sep 12, 1989
- American Telephone and Telegraph Company, AT&T Bell Laboratories
- InSeok S. Hwang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
BCD adder circuit
- Patent number 4,805,131
- Issue date Feb 14, 1989
- Digital Equipment Corporation
- Matthew J. Adiletta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for performing addition and subtraction
- Patent number 4,719,590
- Issue date Jan 12, 1988
- James A. Aman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Intermediate decimal correction for sequential addition
- Patent number 4,718,033
- Issue date Jan 5, 1988
- Hewlett-Packard Company
- Terrence C. Miller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bit sliced decimal adding/subtracting unit for multi-digit decimal...
- Patent number 4,707,799
- Issue date Nov 17, 1987
- Kabushiki Kaisha Toshiba
- Tadashi Ishikawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Equal nine apparatus for supporting absolute value subtracts on dec...
- Patent number 4,638,450
- Issue date Jan 20, 1987
- Honeywell Information Systems Inc.
- Brian L. Stoffers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Central processing unit having built-in BCD operation
- Patent number 4,638,300
- Issue date Jan 20, 1987
- Advanced Micro Devices, Inc.
- Michael J. Miller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Arithmetic logic unit
- Patent number 4,559,608
- Issue date Dec 17, 1985
- Harris Corporation
- William R. Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Decimal arithmetic unit
- Patent number 4,536,854
- Issue date Aug 20, 1985
- Hitachi, Ltd.
- Tomoatsu Yanagita
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital adder circuit for binary-coded numbers of radix other than...
- Patent number 4,441,159
- Issue date Apr 3, 1984
- International Computers Ltd.
- Peter A. Hart
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Expandable arithmetic logic unit
- Patent number 4,263,660
- Issue date Apr 21, 1981
- Motorola, Inc.
- Jerry E. Prioste
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Binary coded decimal correction apparatus for use in an arithmetic...
- Patent number 4,245,328
- Issue date Jan 13, 1981
- Honeywell Information Systems Inc.
- Virendra S. Negi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Correction circuit for arithmetic operations with non-hexadecimal o...
- Patent number 4,197,587
- Issue date Apr 8, 1980
- Siemens Aktiengesellschaft
- Helmut Stettmaier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Binary or BCD adder with precorrected result
- Patent number 4,172,288
- Issue date Oct 23, 1979
- Motorola, Inc.
- Jack L. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-digit arithmetic logic circuit for fast parallel execution
- Patent number 4,139,894
- Issue date Feb 13, 1979
- U.S. Philips Corporation
- Jogchum Reitsma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High speed binary and binary coded decimal adder
- Patent number 4,138,731
- Issue date Feb 6, 1979
- Fujitsu Limited
- Shigemi Kamimoto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated binary-BCD look-ahead adder
- Patent number 4,118,786
- Issue date Oct 3, 1978
- International Business Machines Corporation
- Samuel R. Levine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and means for tracking digit significance in arithmetic oper...
- Patent number 4,110,831
- Issue date Aug 29, 1978
- International Business Machines Corporation
- Glen G. Langdon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprogram controlled binary decimal coded byte operator device
- Patent number 4,041,290
- Issue date Aug 9, 1977
- Compagnie Internationale Pour L'Informatique
- Jean-Louis Fressineau
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit arrangement for adding and subtracting
- Patent number 4,010,359
- Issue date Mar 1, 1977
- Olympia Werke AG
- Gerald Weber
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Arithmetic unit for a digital data processor
- Patent number 4,001,570
- Issue date Jan 4, 1977
- International Business Machines Corporation
- David N. Gooding
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit microprocessor with parallel binary adder having...
- Patent number 3,991,307
- Issue date Nov 9, 1976
- MOS Technology, Inc.
- Charles Ingerham Peddle
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
DEVICE AND METHOD FOR EXTRACTION AND INSERTION OF BINARY WORDS
- Publication number 20210109713
- Publication date Apr 15, 2021
- STMicroelectronics (Grenoble 2) SAS
- Rene Peyrard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DECIMAL ADDER WITH END AROUND CARRY
- Publication number 20110320514
- Publication date Dec 29, 2011
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Binary Coded Decimal Addition
- Publication number 20080016140
- Publication date Jan 17, 2008
- Neelamekakannan Alagarsamy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Highly parallel structure for fast multi cycle binary and decimal a...
- Publication number 20060031279
- Publication date Feb 9, 2006
- International Business Machines Corporation
- Wilhelm Haller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Binary coded decimal addition
- Publication number 20050114423
- Publication date May 26, 2005
- International Business Machines Corporation
- Neelamekakannan Alagarsamy
- G06 - COMPUTING CALCULATING COUNTING

Adding Subtracting

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Decimal adder with end around carry

Binary coded decimal addition

Binary coded decimal addition

Binary and decimal adder unit

Circuit arrangement for adding or subtracting operands coded in BCD...

Circuit arrangement for decimal arithmetic

Fast BCD/binary adder

Predetermination of result conditions of decimal operations

High-speed binary and decimal arithmetic logic unit

BCD adder circuit

Apparatus and method for performing addition and subtraction

Intermediate decimal correction for sequential addition

Bit sliced decimal adding/subtracting unit for multi-digit decimal...

Equal nine apparatus for supporting absolute value subtracts on dec...

Central processing unit having built-in BCD operation

Arithmetic logic unit

Decimal arithmetic unit

Digital adder circuit for binary-coded numbers of radix other than...

Expandable arithmetic logic unit

Binary coded decimal correction apparatus for use in an arithmetic...

Correction circuit for arithmetic operations with non-hexadecimal o...

Binary or BCD adder with precorrected result

Multi-digit arithmetic logic circuit for fast parallel execution

High speed binary and binary coded decimal adder

Integrated binary-BCD look-ahead adder

Method and means for tracking digit significance in arithmetic oper...

Microprogram controlled binary decimal coded byte operator device

Circuit arrangement for adding and subtracting

Arithmetic unit for a digital data processor

Integrated circuit microprocessor with parallel binary adder having...

Patents Applicationslast 30 patents

DEVICE AND METHOD FOR EXTRACTION AND INSERTION OF BINARY WORDS

DECIMAL ADDER WITH END AROUND CARRY

Binary Coded Decimal Addition

Highly parallel structure for fast multi cycle binary and decimal a...

Binary coded decimal addition