Arithmetic instructions

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F9/00Arrangements for programme control

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G06F9/3001Arithmetic instructions

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Patents Grantslast 30 patents

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Methods and apparatus to load data within a machine learning accele...
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Information Patent Grant
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Look-up table initialize
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Two address translations from a single table look-aside buffer read
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Systems and methods for data placement for in-memory-compute
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Methods and circuits of spatial alignment
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Instructions and logic to perform floating point and integer operat...
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Method of storing register data elements to interleave with data el...
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Atomic compare and swap in a coherent cache system
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Aggressive write flush scheme for a victim cache
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Information Patent Grant
Implicit global pointer relative addressing for global memory access
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Information Patent Grant
Compute-in-memory systems and methods
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SYSTEMS, APPARATUSES, AND METHODS FOR ADDITION OF PARTIAL PRODUCTS
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SCALABLE SPARSE MATRIX MULTIPLY ACCELERATION USING SYSTOLIC ARRAYS...
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NETWORK DEVICE-BASED DATA PROCESSING METHOD AND NETWORK DEVICE
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- Huawei Technologies Co., Ltd
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- G06 - COMPUTING CALCULATING COUNTING

Arithmetic instructions

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Methods and apparatus to load data within a machine learning accele...

Supporting 8-bit floating point format operands in a computing arch...

Coprocessor operation bundling

Data initialization techniques

Look-up table initialize

Two address translations from a single table look-aside buffer read

Large integer multiplication enhancements for graphics environment

Systems and methods for data placement for in-memory-compute

Single function to perform combined matrix multiplication and bias...

Synchronizing scheduling tasks with atomic ALU

BFLOAT16 fused multiply instructions

Generating masks for formats including masking restrictions

Block data load with transpose into memory

Device and method of performing content channel generation

Decimal floating-point instruction in a round-for-reround mode

Embedded processor supporting fixed-function kernels

Family of processors of different types configured for executing a...

Method of operating a microprocessor, related processing system and...

Methods and circuits of spatial alignment

Instructions and logic to perform floating point and integer operat...

Apparatus and method for conjugate transpose and multiply

Instruction fusion

Method of storing register data elements to interleave with data el...

Atomic compare and swap in a coherent cache system

Systems and methods for improving cache efficiency and utilization

Aggressive write flush scheme for a victim cache

Neural processing device, processing element included therein and m...

Routing instructions in a microprocessor

Implicit global pointer relative addressing for global memory access

Compute-in-memory systems and methods

Patents Applicationslast 30 patents

ADDITION METHOD, SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE

CACULATING DEVICE

INTERPOLATION ACCELERATION IN A PROCESSOR MEMORY INTERFACE

PROGRAMMABLE COARSE GRAINED AND SPARSE MATRIX COMPUTE HARDWARE WITH...

SYSTEMS, APPARATUSES, AND METHODS FOR CHAINED FUSED MULTIPLY ADD

RANDOM SPARSITY HANDLING IN A SYSTOLIC ARRAY

METHOD AND SYSTEM FOR ACCELERATING RECURRENT NEURAL NETWORK BASED O...

APPARATUS AND METHOD FOR COMPLEX MATRIX TRANSPOSE AND MULTIPLY

METHOD AND ELECTRONIC DEVICE WITH NON-LINEAR FUNCTION

PERFORMANCE SCALING FOR DATAFLOW DEEP NEURAL NETWORK HARDWARE ACCEL...

32-BIT CHANNEL-ALIGNED INTEGER MULTIPLICATION VIA MULTIPLE MULTIPLI...

METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED...

PADDING IN A STREAM OF MATRIX ELEMENTS

PROCESSOR

COMPUTATIONAL MEMORY WITH COOPERATION AMONG ROWS OF PROCESSING ELEM...

GRAPHICS PROCESSOR OPERATION SCHEDULING FOR DETERMINISTIC LATENCY

VICTIM CACHE WITH DYNAMIC ALLOCATION OF ENTRIES

ATOMIC OPERATIONS AND HISTOGRAM OPERATIONS IN A CACHE PIPELINE

APPARATUS, SYSTEM, AND METHOD OF COMPILING CODE FOR A PROCESSOR

BIT MATRIX MULTIPLICATION

PRECISION MODULATED SHADING

STREAMING ENGINE WITH DEFERRED EXCEPTION REPORTING

COMPUTE OPTIMIZATION MECHANISM

BINARY CONVOLUTION INSTRUCTIONS FOR BINARY NEURAL NETWORK COMPUTATIONS

SYSTEMS, METHODS, AND APPARATUSES FOR TILE LOAD

SYSTEMS, APPARATUSES, AND METHODS FOR ADDITION OF PARTIAL PRODUCTS

MULTI-TILE MEMORY MANAGEMENT

VECTOR COMPUTATIONAL UNIT

SCALABLE SPARSE MATRIX MULTIPLY ACCELERATION USING SYSTOLIC ARRAYS...

NETWORK DEVICE-BASED DATA PROCESSING METHOD AND NETWORK DEVICE