Arithmetic instructions

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F9/00Arrangements for programme control

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G06F9/3001Arithmetic instructions

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Patents Grantslast 30 patents

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Techniques for efficiently synchronizing multiple program threads
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- Issue date Apr 8, 2025
- NVIDIA Corporation
- Ajay Sudarshan Tirumala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid victim cache and write miss buffer with fence operation
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- Issue date Apr 1, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Forming constant extensions in the same execute packet in a VLIW pr...
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- Texas Instruments Incorporated
- Timothy David Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for multi-banked victim cache with dual datapath
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- Naveen Bhoria
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Information Patent Grant
Generative AI accelerator apparatus using in-memory compute chiplet...
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Information Patent Grant
Memory having internal processors and data communication methods in...
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- Issue date Mar 25, 2025
- Robert M. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems, methods, and apparatuses for matrix add, subtract, and mul...
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- Issue date Mar 25, 2025
- Intel Corporation
- Robert Valentine
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor micro-architecture for compute, save or restore multiple...
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Information Patent Grant
Methods and apparatus to load data within a machine learning accele...
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Information Patent Grant
Supporting 8-bit floating point format operands in a computing arch...
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Information Patent Grant
Coprocessor operation bundling
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Information Patent Grant
Data initialization techniques
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Information Patent Grant
Look-up table initialize
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Information Patent Grant
Two address translations from a single table look-aside buffer read
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Information Patent Grant
Large integer multiplication enhancements for graphics environment
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Information Patent Grant
Systems and methods for data placement for in-memory-compute
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- Issue date Feb 25, 2025
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- Krishna T. Malladi
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Information Patent Grant
Single function to perform combined matrix multiplication and bias...
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- Issue date Feb 25, 2025
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Information Patent Grant
Synchronizing scheduling tasks with atomic ALU
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- Issue date Feb 18, 2025
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- Ollie Mower
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
BFLOAT16 fused multiply instructions
- Patent number 12,229,554
- Issue date Feb 18, 2025
- Intel Corporation
- Alexander Heinecke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generating masks for formats including masking restrictions
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- Issue date Feb 18, 2025
- International Business Machines Corporation
- Ariel Farkash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Block data load with transpose into memory
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- Issue date Feb 18, 2025
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- Bin He
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Information Patent Grant
Device and method of performing content channel generation
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- Jhe-Yi Lin
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Information Patent Grant
Decimal floating-point instruction in a round-for-reround mode
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- Issue date Feb 11, 2025
- International Business Machines Corporation
- Eric Mark Schwarz
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Information Patent Grant
Embedded processor supporting fixed-function kernels
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- Issue date Feb 11, 2025
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- Aaron Severance
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Information Patent Grant
Family of processors of different types configured for executing a...
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- Issue date Feb 11, 2025
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- Thomas Awad
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Information Patent Grant
Method of operating a microprocessor, related processing system and...
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- Issue date Feb 11, 2025
- STMicroelectronics S.r.l.
- Matteo Bocchi
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Information Patent Grant
Methods and circuits of spatial alignment
- Patent number 12,223,010
- Issue date Feb 11, 2025
- ARM Limited
- Supreet Jeloka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for conjugate transpose and multiply
- Patent number 12,216,734
- Issue date Feb 4, 2025
- Intel Corporation
- Menachem Adelman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instructions and logic to perform floating point and integer operat...
- Patent number 12,217,053
- Issue date Feb 4, 2025
- Intel Corporation
- Himanshu Kaul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction fusion
- Patent number 12,217,060
- Issue date Feb 4, 2025
- Apple Inc.
- Francesco Spadini
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

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PROCESSOR, METHOD, DEVICE AND STORAGE MEDIUM FOR DATA PROCESSING
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SUPPORTING 8-BIT FLOATING POINT FORMAT FOR PARALLEL COMPUTING AND S...
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SCALABLE DETERMINISTIC SOLUTION FOR NON-DETERMINISTIC OPERATIONS
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- G06 - COMPUTING CALCULATING COUNTING
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Streaming-based Computation Circuit, Method and Artificial Intellig...
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- G06 - COMPUTING CALCULATING COUNTING
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SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION
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TRACKING STREAMING ENGINE VECTOR PREDICATES TO CONTROL PROCESSOR EX...
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SYSTOLIC DISAGGREGATION WITHIN A MATRIX ACCELERATOR ARCHITECTURE
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- Intel Corporation
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- G06 - COMPUTING CALCULATING COUNTING
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INSTRUCTIONS AND LOGIC TO PERFORM FLOATING POINT AND INTEGER OPERAT...
- Publication number 20250094170
- Publication date Mar 20, 2025
- Intel Corporation
- Himanshu Kaul
- G06 - COMPUTING CALCULATING COUNTING
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FULLY PIPELINED READ-MODIFY-WRITE SUPPORT
- Publication number 20250094359
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- TEXAS INSTRUMENTS INCORPORATED
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METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRIT...
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- TEXAS INSTRUMENTS INCORPORATED
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ANALYTICAL PLATFORM FOR DISTRIBUTED DATA
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- G06 - COMPUTING CALCULATING COUNTING
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UNBLOCKING THE INTEGER PIPELINE DURING MATH PIPELINE PHASES IN A GR...
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- Intel Corporation
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SM3 HASH ALGORITHM ACCELERATION PROCESSORS, METHODS, SYSTEMS, AND I...
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INTERPOLATION ACCELERATION IN A PROCESSOR MEMORY INTERFACE
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ADDITION METHOD, SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE
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CACULATING DEVICE
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- Kabushiki Kaisha Toshiba
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PROGRAMMABLE COARSE GRAINED AND SPARSE MATRIX COMPUTE HARDWARE WITH...
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- Intel Corporation
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SYSTEMS, APPARATUSES, AND METHODS FOR CHAINED FUSED MULTIPLY ADD
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- JESUS CORBAL
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RANDOM SPARSITY HANDLING IN A SYSTOLIC ARRAY
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- Chunhui Mei
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METHOD AND SYSTEM FOR ACCELERATING RECURRENT NEURAL NETWORK BASED O...
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- HANGZHOU VANGO TECHNOLOGIES, INC.
- Yang REN
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APPARATUS AND METHOD FOR COMPLEX MATRIX TRANSPOSE AND MULTIPLY
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METHOD AND ELECTRONIC DEVICE WITH NON-LINEAR FUNCTION
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PERFORMANCE SCALING FOR DATAFLOW DEEP NEURAL NETWORK HARDWARE ACCEL...
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- Arnab Raha
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32-BIT CHANNEL-ALIGNED INTEGER MULTIPLICATION VIA MULTIPLE MULTIPLI...
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- Intel Corporation
- Jiasheng Chen
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PADDING IN A STREAM OF MATRIX ELEMENTS
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- TEXAS INSTRUMENTS INCORPORATED
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METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED...
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- TEXAS INSTRUMENTS INCORPORATED
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PROCESSOR
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- Publication date Jan 30, 2025
- Fujitsu Limited
- Sota SAKASHITA
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COMPUTATIONAL MEMORY WITH COOPERATION AMONG ROWS OF PROCESSING ELEM...
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- William Martin SNELGROVE
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GRAPHICS PROCESSOR OPERATION SCHEDULING FOR DETERMINISTIC LATENCY
- Publication number 20250028675
- Publication date Jan 23, 2025
- Intel Corporation
- JOYDEEP RAY
- G06 - COMPUTING CALCULATING COUNTING

Arithmetic instructions

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Techniques for efficiently synchronizing multiple program threads

Hybrid victim cache and write miss buffer with fence operation

Forming constant extensions in the same execute packet in a VLIW pr...

Methods and apparatus for multi-banked victim cache with dual datapath

Generative AI accelerator apparatus using in-memory compute chiplet...

Memory having internal processors and data communication methods in...

Systems, methods, and apparatuses for matrix add, subtract, and mul...

Processor micro-architecture for compute, save or restore multiple...

Methods and apparatus to load data within a machine learning accele...

Supporting 8-bit floating point format operands in a computing arch...

Coprocessor operation bundling

Data initialization techniques

Look-up table initialize

Two address translations from a single table look-aside buffer read

Large integer multiplication enhancements for graphics environment

Systems and methods for data placement for in-memory-compute

Single function to perform combined matrix multiplication and bias...

Synchronizing scheduling tasks with atomic ALU

BFLOAT16 fused multiply instructions

Generating masks for formats including masking restrictions

Block data load with transpose into memory

Device and method of performing content channel generation

Decimal floating-point instruction in a round-for-reround mode

Embedded processor supporting fixed-function kernels

Family of processors of different types configured for executing a...

Method of operating a microprocessor, related processing system and...

Methods and circuits of spatial alignment

Apparatus and method for conjugate transpose and multiply

Instructions and logic to perform floating point and integer operat...

Instruction fusion

Patents Applicationslast 30 patents

PROCESSOR, METHOD, DEVICE AND STORAGE MEDIUM FOR DATA PROCESSING

SUPPORTING 8-BIT FLOATING POINT FORMAT FOR PARALLEL COMPUTING AND S...

SCALABLE DETERMINISTIC SOLUTION FOR NON-DETERMINISTIC OPERATIONS

Streaming-based Computation Circuit, Method and Artificial Intellig...

SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION

CACHE STRUCTURE AND UTILIZATION

TRACKING STREAMING ENGINE VECTOR PREDICATES TO CONTROL PROCESSOR EX...

SYSTOLIC DISAGGREGATION WITHIN A MATRIX ACCELERATOR ARCHITECTURE

INSTRUCTIONS AND LOGIC TO PERFORM FLOATING POINT AND INTEGER OPERAT...

FULLY PIPELINED READ-MODIFY-WRITE SUPPORT

METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRIT...

ANALYTICAL PLATFORM FOR DISTRIBUTED DATA

UNBLOCKING THE INTEGER PIPELINE DURING MATH PIPELINE PHASES IN A GR...

SM3 HASH ALGORITHM ACCELERATION PROCESSORS, METHODS, SYSTEMS, AND I...

INTERPOLATION ACCELERATION IN A PROCESSOR MEMORY INTERFACE

ADDITION METHOD, SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE

CACULATING DEVICE

PROGRAMMABLE COARSE GRAINED AND SPARSE MATRIX COMPUTE HARDWARE WITH...

SYSTEMS, APPARATUSES, AND METHODS FOR CHAINED FUSED MULTIPLY ADD

RANDOM SPARSITY HANDLING IN A SYSTOLIC ARRAY

METHOD AND SYSTEM FOR ACCELERATING RECURRENT NEURAL NETWORK BASED O...

APPARATUS AND METHOD FOR COMPLEX MATRIX TRANSPOSE AND MULTIPLY

METHOD AND ELECTRONIC DEVICE WITH NON-LINEAR FUNCTION

PERFORMANCE SCALING FOR DATAFLOW DEEP NEURAL NETWORK HARDWARE ACCEL...

32-BIT CHANNEL-ALIGNED INTEGER MULTIPLICATION VIA MULTIPLE MULTIPLI...

PADDING IN A STREAM OF MATRIX ELEMENTS

METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED...

PROCESSOR

COMPUTATIONAL MEMORY WITH COOPERATION AMONG ROWS OF PROCESSING ELEM...

GRAPHICS PROCESSOR OPERATION SCHEDULING FOR DETERMINISTIC LATENCY