Bit or string instructions; instructions using a mask

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G06F9/30018

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F9/00Arrangements for programme control

Current Industry

G06F9/30018Bit or string instructions; instructions using a mask

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Patents Grantslast 30 patents

Information Patent Grant
Tracking streaming engine vector predicates to control processor ex...
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- Issue date Dec 10, 2024
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Computing task scheduling in a computer system utilizing efficient...
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SM3 hash algorithm acceleration processors, methods, systems, and i...
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Information Patent Grant
Systems and methods for performing instructions to convert to 16-bi...
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- Intel Corporation
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Systems, apparatuses, and methods for addition of partial products
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Information processing apparatus, information processing method, an...
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Information Patent Grant
Execution or write mask generation for data selection in a multi-th...
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- Micron Technology, Inc.
- Tony M. Brewer
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Method and apparatus for vector permutation
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Throughput increase for tensor operations
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Method and apparatus for permuting streamed data elements
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Vector friendly instruction format and execution thereof
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Apparatus and method for loop flattening and reduction in a single...
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Software-based log management
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Highly integrated scalable, flexible DSP megamodule architecture
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Embedded system and vibration driving method
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File lifetime tracking for cloud-based object stores
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Context load mechanism in a coarse-grained reconfigurable array pro...
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Method and apparatus for vector sorting
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Flexible support for device emulation and bank swapping
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Method and apparatus for dual issue multiply instructions
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Hardware channel-parallel data compression/decompression
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Method and apparatus for vector based matrix multiplication
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Systems, methods, and devices for queue availability monitoring
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Information Patent Grant
Controlling the number of powered vector lanes via a register field
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System and method to control the number of active vector lanes in a...
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Information Patent Grant
Replicate elements instruction
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- Issue date May 7, 2024
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Information Patent Grant
Instructions to count a number of contiguous register elements havi...
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- Issue date Apr 30, 2024
- International Business Machines Corporation
- Michael K. Gschwind
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Patents Applicationslast 30 patents

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VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF
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METHOD AND APPARATUS FOR PERMUTING STREAMED DATA ELEMENTS
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CONSTANT MEMORY SEGMENTATION FOR PARALLEL PROCESSORS
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Fault Isolation In A Director Processor Slice or Board
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Vector Based Matrix Multiplication
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- TEXAS INSTRUMENTS INCORPORATED
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SORTING VECTOR ELEMENTS USING A COUNT VALUE
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- TEXAS INSTRUMENTS INCORPORATED
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APPARATUS AND METHOD FOR PERFORMING A SPLICE OPERATION
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METHOD AND APPARATUS FOR IMPLIED BIT HANDLING IN FLOATING POINT MUL...
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- TEXAS INSTRUMENTS INCORPORATED
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CONTEXT LOAD MECHANISM IN A COARSE-GRAINED RECONFIGURABLE ARRAY PRO...
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- Micron Technology, Inc.
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SYSTEMS, METHODS, AND DEVICES FOR QUEUE AVAILABILITY MONITORING
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- Samsung Electronics Co., Ltd.
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Method and Apparatus for Dual Issue Multiply Instructions
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- TEXAS INSTRUMENTS INCORPORATED
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CONTROLLING THE NUMBER OF POWERED VECTOR LANES VIA A REGISTER FIELD
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- Publication date Jul 25, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Timothy David Anderson
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MASK PATTERNS GENERATED IN MEMORY FROM SEED VECTORS
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- Publication date Jul 25, 2024
- Lodestar Licensing Group LLC
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SYSTEM AND METHOD TO CONTROL THE NUMBER OF ACTIVE VECTOR LANES IN A...
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- TEXAS INSTRUMENTS INCORPORATED
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EMBEDDING VECTOR PREFETCHING METHOD AND APPARATUS, SYSTEM, AND RELA...
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- Huawei Technologies Co., Ltd
- Qihang DUAN
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VECTOR SIMD VLIW DATA PATH ARCHITECTURE
- Publication number 20240211254
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- TEXAS INSTRUMENTS INCORPORATED
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Multiple Multiplication Units in a Data Path
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- TEXAS INSTRUMENTS INCORPORATED
- Mujibur Rahman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Canceling Prefetch of Cache Blocks Based on an Address and a Bit Field
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- Publication date Jun 6, 2024
- SiFive, Inc.
- Eric Andrew Gouldey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR PROVIDING MASK REGISTER OPTIMIZATION FOR...
- Publication number 20240111526
- Publication date Apr 4, 2024
- ADVANCED MICRO DEVICES, INC.
- MICHAEL ESTLICK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTEXT LOAD MECHANISM IN A COARSE-GRAINED RECONFIGURABLE ARRAY PRO...
- Publication number 20240070112
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Bryan Hornung
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SECURING REGISTERS ACROSS SECURITY ZONES
- Publication number 20240069920
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- TEXAS INSTRUMENTS INCORPORATED
- David P. FOLEY
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Information Patent Application
VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF
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- Publication date Feb 22, 2024
- Intel Corporation
- Robert C. VALENTINE
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Method and Apparatus for Vector Sorting using Vector Permutation Logic
- Publication number 20240045810
- Publication date Feb 8, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Timothy David Anderson
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INSTRUCTIONS TO CONVERT FROM FP16 TO FP8
- Publication number 20240045684
- Publication date Feb 8, 2024
- Intel Corporation
- Alexander Heinecke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Execution or Write Mask Generation for Data Selection in a Multi-Th...
- Publication number 20240045676
- Publication date Feb 8, 2024
- Micron Technology, Inc.
- Tony M. Brewer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Coprocessor Operation Bundling
- Publication number 20240036870
- Publication date Feb 1, 2024
- Apple Inc.
- Aditya Kesiraju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR ORDERING BITS IN A MEMORY DEVICE
- Publication number 20240036875
- Publication date Feb 1, 2024
- Lodestar Licensing Group LLC
- Glen E. Hush
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, APPARATUSES, AND METHODS FOR ADDITION OF PARTIAL PRODUCTS
- Publication number 20230418602
- Publication date Dec 28, 2023
- Intel Corporation
- Robert Valentine
- G06 - COMPUTING CALCULATING COUNTING

Bit or string instructions; instructions using a mask

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Tracking streaming engine vector predicates to control processor ex...

Computing task scheduling in a computer system utilizing efficient...

SM3 hash algorithm acceleration processors, methods, systems, and i...

Systems and methods for performing instructions to convert to 16-bi...

Systems, apparatuses, and methods for addition of partial products

Information processing apparatus, information processing method, an...

Execution or write mask generation for data selection in a multi-th...

Method and apparatus for vector permutation

Throughput increase for tensor operations

Method and apparatus for permuting streamed data elements

Vector friendly instruction format and execution thereof

Apparatus and method for loop flattening and reduction in a single...

Software-based log management

Highly integrated scalable, flexible DSP megamodule architecture

Apparatus and method for performing a splice of vectors based on lo...

Embedded system and vibration driving method

File lifetime tracking for cloud-based object stores

Packed data element predication processors, methods, systems, and i...

Context load mechanism in a coarse-grained reconfigurable array pro...

Method and apparatus for vector sorting

Flexible support for device emulation and bank swapping

Method and apparatus for dual issue multiply instructions

Hardware channel-parallel data compression/decompression

Method and apparatus for vector based matrix multiplication

Systems, methods, and devices for queue availability monitoring

Architecture to support color scheme-based synchronization for mach...

Controlling the number of powered vector lanes via a register field

System and method to control the number of active vector lanes in a...

Replicate elements instruction

Instructions to count a number of contiguous register elements havi...

Patents Applicationslast 30 patents

VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF

METHOD AND APPARATUS FOR VECTOR PERMUTATION

PROCESSOR ARCHITECTURE WITH MEMORY ACCESS CIRCUIT

METHOD AND APPARATUS FOR PERMUTING STREAMED DATA ELEMENTS

CONSTANT MEMORY SEGMENTATION FOR PARALLEL PROCESSORS

Fault Isolation In A Director Processor Slice or Board

Vector Based Matrix Multiplication

SORTING VECTOR ELEMENTS USING A COUNT VALUE

APPARATUS AND METHOD FOR PERFORMING A SPLICE OPERATION

METHOD AND APPARATUS FOR IMPLIED BIT HANDLING IN FLOATING POINT MUL...

CONTEXT LOAD MECHANISM IN A COARSE-GRAINED RECONFIGURABLE ARRAY PRO...

SYSTEMS, METHODS, AND DEVICES FOR QUEUE AVAILABILITY MONITORING

Method and Apparatus for Dual Issue Multiply Instructions

CONTROLLING THE NUMBER OF POWERED VECTOR LANES VIA A REGISTER FIELD

MASK PATTERNS GENERATED IN MEMORY FROM SEED VECTORS

SYSTEM AND METHOD TO CONTROL THE NUMBER OF ACTIVE VECTOR LANES IN A...

EMBEDDING VECTOR PREFETCHING METHOD AND APPARATUS, SYSTEM, AND RELA...

VECTOR SIMD VLIW DATA PATH ARCHITECTURE

Multiple Multiplication Units in a Data Path

Canceling Prefetch of Cache Blocks Based on an Address and a Bit Field

METHODS AND APPARATUS FOR PROVIDING MASK REGISTER OPTIMIZATION FOR...

CONTEXT LOAD MECHANISM IN A COARSE-GRAINED RECONFIGURABLE ARRAY PRO...

SECURING REGISTERS ACROSS SECURITY ZONES

VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF

Method and Apparatus for Vector Sorting using Vector Permutation Logic

INSTRUCTIONS TO CONVERT FROM FP16 TO FP8

Execution or Write Mask Generation for Data Selection in a Multi-Th...

Coprocessor Operation Bundling

APPARATUSES AND METHODS FOR ORDERING BITS IN A MEMORY DEVICE

SYSTEMS, APPARATUSES, AND METHODS FOR ADDITION OF PARTIAL PRODUCTS