Chip packaging

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F2217/00Indexing scheme relating to computer aided design [CAD]

Current Industry

G06F2217/40Chip packaging

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Patents Grantslast 30 patents

Information Patent Grant
Light source and method for making a light source
- Patent number 10,598,318
- Issue date Mar 24, 2020
- EATON INTELLIGENT POWER LIMITED
- Christopher Lee Bohler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selection of die and package parasitic for IO power domain
- Patent number 10,585,999
- Issue date Mar 10, 2020
- Seagate Technology LLC
- Nitin Kumar Chhabra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single simulation-based structure function mapping
- Patent number 10,571,514
- Issue date Feb 25, 2020
- Mentor Graphics Corporation
- Byron Blackmore
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Chip temperature computation method and chip temperature computatio...
- Patent number 10,540,474
- Issue date Jan 21, 2020
- Industrial Technology Research Institute
- Heng-Chieh Chien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor devices with bump allocation
- Patent number 10,541,185
- Issue date Jan 21, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd
- Yung-Hsin Kuo
- G01 - MEASURING TESTING
Information Patent Grant
Method of tuning components within an integracted circuit device
- Patent number 10,522,458
- Issue date Dec 31, 2019
- NXP USA, INC.
- Yi Yin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Thermal resistance analysis model and semiconductor integrated circuit
- Patent number 10,482,199
- Issue date Nov 19, 2019
- Rohm Co., Ltd.
- Ippei Yasutake
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Via architecture for increased density interface
- Patent number 10,475,736
- Issue date Nov 12, 2019
- Intel Corporation
- Aleksandar Aleksov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of selecting routing resources in a multi-chip integrated ci...
- Patent number 10,467,373
- Issue date Nov 5, 2019
- Jay T. Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid modeling for a device under test associated with a two-phase...
- Patent number 10,423,735
- Issue date Sep 24, 2019
- International Business Machines Corporation
- Timothy Joseph Chainer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Package substrate differential impedance optimization for 25 to 60...
- Patent number 10,410,984
- Issue date Sep 10, 2019
- SARCINA TECHNOLOGY LLC
- Longqiang Zu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Package substrate differential impedance optimization for 25 to 60...
- Patent number 10,276,519
- Issue date Apr 30, 2019
- SARCINA TECHNOLOGY LLC
- Longqiang Zu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Entry finder for single layer differential group routing
- Patent number 10,204,204
- Issue date Feb 12, 2019
- Synopsys, Inc.
- Jessica Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus providing a graded package for a semiconductor
- Patent number 10,170,384
- Issue date Jan 1, 2019
- Texas Instruments Incorporated
- Daniel Lee Revier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit design layout in multiple synchronous representations
- Patent number 10,127,343
- Issue date Nov 13, 2018
- Mentor Graphics Corporation
- Gerald Suiter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated fan-out package and layout method thereof
- Patent number 10,120,971
- Issue date Nov 6, 2018
- Taiwan Semiconductor Manufacturing Co., Ltd
- Wan-Yu Lo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
2.5D electronic package
- Patent number 10,020,267
- Issue date Jul 10, 2018
- Altera Corporation
- Arifur Rahman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor devices with ball strength improvement
- Patent number 9,978,704
- Issue date May 22, 2018
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Tsung-Yuan Yu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods, systems, and computer program product for implementing a l...
- Patent number 9,934,354
- Issue date Apr 3, 2018
- Cadence Design Systems, Inc.
- Taranjit Singh Kukal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Redistribution layer routing for integrated fan-out wafer-level chi...
- Patent number 9,928,334
- Issue date Mar 27, 2018
- Bo-Qiao Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer-implemented method of designing a modularized stacked inte...
- Patent number 9,904,751
- Issue date Feb 27, 2018
- Mediatek Inc.
- Jia-Wei Fang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout method for printed circuit board
- Patent number 9,846,756
- Issue date Dec 19, 2017
- Mediatek Inc.
- Fu-Kang Pan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device design methods and conductive bump pattern enh...
- Patent number 9,760,670
- Issue date Sep 12, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Tzu-Yu Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Area array device connection structures with complimentary warp cha...
- Patent number 9,609,744
- Issue date Mar 28, 2017
- International Business Machines Corporation
- Mark K. Hoffmeyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for co-designing flip-chip and interposer
- Patent number 9,589,092
- Issue date Mar 7, 2017
- Mediatek Inc.
- Jia-Wei Fang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
2.5D electronic package
- Patent number 9,583,431
- Issue date Feb 28, 2017
- Altera Corporation
- Arifur Rahman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods of improving bump allocation for semiconductor devices and...
- Patent number 9,557,370
- Issue date Jan 31, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yung-Hsin Kuo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for flip chip packaging co-design and co-desig...
- Patent number 9,552,452
- Issue date Jan 24, 2017
- Mediatek Inc.
- Jia-Wei Fang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for designing semiconductor package using computi...
- Patent number 9,465,900
- Issue date Oct 11, 2016
- Samsung Electronics Co., Ltd.
- Jae-Hoon Jeong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor devices with ball strength improvement
- Patent number 9,437,567
- Issue date Sep 6, 2016
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Tsung-Yuan Yu
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Method and Apparatus for improved Circuit Structure Thermal Reliabi...
- Publication number 20210066209
- Publication date Mar 4, 2021
- NXP B.V.
- Leo van Gemert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK CROSSING INTERFACE FOR INTEGRATED CIRCUIT GENERATION
- Publication number 20210011981
- Publication date Jan 14, 2021
- SiFive, Inc.
- Henry Cook
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTER-IMPLEMENTED METHOD, PROCESSOR-IMPLEMENTED SYSTEM, AND NON-...
- Publication number 20200233934
- Publication date Jul 23, 2020
- Samsung Electronics Co., Ltd.
- YOUNGBAE KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BUMP LAYOUT FOR COPLANARITY IMPROVEMENT
- Publication number 20200105654
- Publication date Apr 2, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ling-Wei Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF SELECTING ROUTING RESOURCES IN A MULTI-CHIP INTEGRATED CI...
- Publication number 20190258767
- Publication date Aug 22, 2019
- Xilinx, Inc.
- Jay T. Young
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Single Simulation-Based Structure Function Mapping
- Publication number 20190072606
- Publication date Mar 7, 2019
- Mentor Graphics Corporation
- Byron Blackmore
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERPOSER FOR AN INTEGRATED SYSTEM AND CORRESPONDING DESIGN METHOD
- Publication number 20190043808
- Publication date Feb 7, 2019
- MONOZUKURI S.p.A.
- ANNA ADRIANA FONTANELLI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS PROVIDING A GRADED PACKAGE FOR A SEMICONDUCTOR
- Publication number 20180254230
- Publication date Sep 6, 2018
- TEXAS INSTRUMENTS INCORPORATED
- Daniel Lee Revier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THERMAL RESISTANCE ANALYSIS MODEL AND SEMICONDUCTOR INTEGRATED CIRCUIT
- Publication number 20180075176
- Publication date Mar 15, 2018
- Rohm Co., Ltd.
- Ippei Yasutake
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED FAN-OUT PACKAGE AND LAYOUT METHOD THEREOF
- Publication number 20180060479
- Publication date Mar 1, 2018
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Wan-Yu Lo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Redistribution Layer Routing for Integrated Fan-Out Wafer-Level Chi...
- Publication number 20180032660
- Publication date Feb 1, 2018
- ANAGLOBE TECHNOLOGY, INC.
- Bo-Qiao Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PACKAGE SUBSTRATE DIFFERENTIAL IMPEDANCE OPTIMIZATION FOR 25 TO 60...
- Publication number 20170229407
- Publication date Aug 10, 2017
- Sarcina Technology LLC
- Longqiang Zu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
2.5D ELECTRONIC PACKAGE
- Publication number 20170133329
- Publication date May 11, 2017
- Altera Corporation
- Arifur Rahman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ELECTRONIC SYSTEM, AS WELL AS MANUFACTURING METHOD, AND DEVICE FOR...
- Publication number 20170073222
- Publication date Mar 16, 2017
- ROBERT BOSCH GmbH
- Rolf KAACK
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
Semiconductor Device Design Methods and Conductive Bump Pattern Enh...
- Publication number 20160283639
- Publication date Sep 29, 2016
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Tzu-Yu Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-LAYER CIRCUIT USING METAL LAYERS AS A MOISTURE DIFFUSION BARR...
- Publication number 20160210398
- Publication date Jul 21, 2016
- Kyocera Circuit Solutions Inc.
- Jean AUDET
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR DESIGN METHOD AND COMPUTER-READABLE RECORDING MEDIUM
- Publication number 20160154924
- Publication date Jun 2, 2016
- SOCIONEXT INC.
- Kaname Ozawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR FLIP CHIP PACKAGING CO-DESIGN
- Publication number 20150154336
- Publication date Jun 4, 2015
- MEDIATEK INC.
- Jia-Wei Fang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Semiconductor Device Design Methods and Conductive Bump Pattern Enh...
- Publication number 20150143324
- Publication date May 21, 2015
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Tzu-Yu Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DESIGN STRUCTURE FOR LOGIC CIRCUIT AND SERIALIZER-DESERIALIZER STACK
- Publication number 20150113495
- Publication date Apr 23, 2015
- International Business Machines Corporation
- Michael J. Shapiro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASYMMETRIC MESH NOC TOPOLOGIES
- Publication number 20140331027
- Publication date Nov 6, 2014
- Joji Philip
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR AIDING IN DESIGNING ELECTRONIC CIRCUITS
- Publication number 20140325469
- Publication date Oct 30, 2014
- Ikuo OHTSUKA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AREA ARRAY DEVICE CONNECTION STRUCTURES WITH COMPLIMENTARY WARP CHA...
- Publication number 20140268603
- Publication date Sep 18, 2014
- International Business Machines Corporation
- Mark K. Hoffmeyer
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT FLOORPLAN FOR COMPACT CLOCK DISTRIBUTION
- Publication number 20140253228
- Publication date Sep 11, 2014
- QUALCOMM Incorporated
- Vaishnav Srinivas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT PAD MODELING
- Publication number 20140237438
- Publication date Aug 21, 2014
- International Business Machines Corporation
- Hanyi DING
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR DESIGNING SEMICONDUCTOR PACKAGE USING COMPUTI...
- Publication number 20140131867
- Publication date May 15, 2014
- Jae-Hoon JEONG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASYMMETRIC MESH NoC TOPOLOGIES
- Publication number 20140115298
- Publication date Apr 24, 2014
- NETSPEED SYSTEMS
- Joji PHILIP
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ASYMMETRIC MESH NoC TOPOLOGIES
- Publication number 20140115218
- Publication date Apr 24, 2014
- NETSPEED SYSTEMS
- Joji PHILIP
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT METHOD FOR PRINTED CIRCUIT BOARD
- Publication number 20140109035
- Publication date Apr 17, 2014
- MEDIATEK INC.
- Fu-Kang PAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR ACROSS-CHIP THERMAL AND POWER MANAGEMENT IN S...
- Publication number 20140096102
- Publication date Apr 3, 2014
- Taiwan Semiconductor Manufacturing Co., LTD
- Chung-min FU
- G06 - COMPUTING CALCULATING COUNTING

Chip packaging

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Light source and method for making a light source

Selection of die and package parasitic for IO power domain

Single simulation-based structure function mapping

Chip temperature computation method and chip temperature computatio...

Semiconductor devices with bump allocation

Method of tuning components within an integracted circuit device

Thermal resistance analysis model and semiconductor integrated circuit

Via architecture for increased density interface

Method of selecting routing resources in a multi-chip integrated ci...

Hybrid modeling for a device under test associated with a two-phase...

Package substrate differential impedance optimization for 25 to 60...

Package substrate differential impedance optimization for 25 to 60...

Entry finder for single layer differential group routing

Methods and apparatus providing a graded package for a semiconductor

Circuit design layout in multiple synchronous representations

Integrated fan-out package and layout method thereof

2.5D electronic package

Semiconductor devices with ball strength improvement

Methods, systems, and computer program product for implementing a l...

Redistribution layer routing for integrated fan-out wafer-level chi...

Computer-implemented method of designing a modularized stacked inte...

Layout method for printed circuit board

Semiconductor device design methods and conductive bump pattern enh...

Area array device connection structures with complimentary warp cha...

Method for co-designing flip-chip and interposer

2.5D electronic package

Methods of improving bump allocation for semiconductor devices and...

Method and apparatus for flip chip packaging co-design and co-desig...

System and method for designing semiconductor package using computi...

Semiconductor devices with ball strength improvement

Patents Applicationslast 30 patents

Method and Apparatus for improved Circuit Structure Thermal Reliabi...

CLOCK CROSSING INTERFACE FOR INTEGRATED CIRCUIT GENERATION

COMPUTER-IMPLEMENTED METHOD, PROCESSOR-IMPLEMENTED SYSTEM, AND NON-...

BUMP LAYOUT FOR COPLANARITY IMPROVEMENT

METHOD OF SELECTING ROUTING RESOURCES IN A MULTI-CHIP INTEGRATED CI...

Single Simulation-Based Structure Function Mapping

INTERPOSER FOR AN INTEGRATED SYSTEM AND CORRESPONDING DESIGN METHOD

METHODS AND APPARATUS PROVIDING A GRADED PACKAGE FOR A SEMICONDUCTOR

THERMAL RESISTANCE ANALYSIS MODEL AND SEMICONDUCTOR INTEGRATED CIRCUIT

INTEGRATED FAN-OUT PACKAGE AND LAYOUT METHOD THEREOF

Redistribution Layer Routing for Integrated Fan-Out Wafer-Level Chi...

PACKAGE SUBSTRATE DIFFERENTIAL IMPEDANCE OPTIMIZATION FOR 25 TO 60...

2.5D ELECTRONIC PACKAGE

ELECTRONIC SYSTEM, AS WELL AS MANUFACTURING METHOD, AND DEVICE FOR...

Semiconductor Device Design Methods and Conductive Bump Pattern Enh...

MULTI-LAYER CIRCUIT USING METAL LAYERS AS A MOISTURE DIFFUSION BARR...

SEMICONDUCTOR DESIGN METHOD AND COMPUTER-READABLE RECORDING MEDIUM

METHOD FOR FLIP CHIP PACKAGING CO-DESIGN

Semiconductor Device Design Methods and Conductive Bump Pattern Enh...

DESIGN STRUCTURE FOR LOGIC CIRCUIT AND SERIALIZER-DESERIALIZER STACK

ASYMMETRIC MESH NOC TOPOLOGIES

APPARATUS AND METHOD FOR AIDING IN DESIGNING ELECTRONIC CIRCUITS

AREA ARRAY DEVICE CONNECTION STRUCTURES WITH COMPLIMENTARY WARP CHA...

INTEGRATED CIRCUIT FLOORPLAN FOR COMPACT CLOCK DISTRIBUTION

INTEGRATED CIRCUIT PAD MODELING

SYSTEM AND METHOD FOR DESIGNING SEMICONDUCTOR PACKAGE USING COMPUTI...

ASYMMETRIC MESH NoC TOPOLOGIES

ASYMMETRIC MESH NoC TOPOLOGIES

LAYOUT METHOD FOR PRINTED CIRCUIT BOARD

SYSTEM AND METHOD FOR ACROSS-CHIP THERMAL AND POWER MANAGEMENT IN S...