Clock network

Industry

CPC
G06F2217/62

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Parent Industries

GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F2217/00Indexing scheme relating to computer aided design [CAD]

Current Industry

G06F2217/62Clock network

Industries

Patents Grantslast 30 patents

Information Patent Grant
Multi-bit clock gating cell to reduce clock power
- Patent number 10,650,112
- Issue date May 12, 2020
- Apple Inc.
- Harsha Krishnamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic multi-clock circuit generation
- Patent number 10,629,161
- Issue date Apr 21, 2020
- National Instruments Corporation
- Hojin Kee
- G01 - MEASURING TESTING
Information Patent Grant
Clock network analysis using harmonic balance
- Patent number 10,620,659
- Issue date Apr 14, 2020
- International Business Machines Corporation
- Peter Feldmann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing clock power consumption of a computer processor
- Patent number 10,614,183
- Issue date Apr 7, 2020
- International Business Machines Corporation
- Erez Barak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Constructing staging trees in hierarchical circuit designs
- Patent number 10,616,103
- Issue date Apr 7, 2020
- International Business Machines Corporation
- Harald Folberth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit design analyzer
- Patent number 10,599,792
- Issue date Mar 24, 2020
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Formal clock network analysis, visualization, verification and gene...
- Patent number 10,599,800
- Issue date Mar 24, 2020
- Synopsys, Inc.
- Mohamed Shaker Sarwary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing clock power consumption of a computer processor
- Patent number 10,585,995
- Issue date Mar 10, 2020
- International Business Machines Corporation
- Erez Barak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Targeted delay optimization through programmable clock delays
- Patent number 10,565,334
- Issue date Feb 18, 2020
- Xilinx, Inc.
- Ruibing Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase algebra for virtual clock and mode extraction in hierarchical...
- Patent number 10,558,782
- Issue date Feb 11, 2020
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Glitch-aware phase algebra for clock analysis
- Patent number 10,552,559
- Issue date Feb 4, 2020
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Controlling real time during embedded system development
- Patent number 10,552,560
- Issue date Feb 4, 2020
- Mentor Graphics Corporation
- Lance S. P. Brooks
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Conditional phase algebra for clock analysis
- Patent number 10,552,558
- Issue date Feb 4, 2020
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parameter collapsing and corner reduction in an integrated circuit
- Patent number 10,546,095
- Issue date Jan 28, 2020
- International Business Machines Corporation
- Eric Foreman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generating a layout for an integrated circuit
- Patent number 10,546,094
- Issue date Jan 28, 2020
- International Business Machines Corporation
- Andreas H. A. Arp
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Verifying sequential equivalence for randomly initialized designs
- Patent number 10,540,469
- Issue date Jan 21, 2020
- International Business Machines Corporation
- Alexander Ivrii
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock jitter emulation
- Patent number 10,528,686
- Issue date Jan 7, 2020
- Synopsys, Inc.
- Ludovic Marc Larzul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing-closure methodology involving clock network in hardware designs
- Patent number 10,528,697
- Issue date Jan 7, 2020
- Xilinx, Inc.
- Wei Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock-gating phase algebra for clock analysis
- Patent number 10,515,164
- Issue date Dec 24, 2019
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase algebra for specifying clocks and modes in hierarchical designs
- Patent number 10,503,856
- Issue date Dec 10, 2019
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Verification support apparatus and design verification support method
- Patent number 10,482,207
- Issue date Nov 19, 2019
- Fujitsu Limited
- Osamu Sugahara
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bisection methodology for on-chip variation tolerant clock signal d...
- Patent number 10,474,779
- Issue date Nov 12, 2019
- Juniper Networks, Inc.
- Vincent C. Leung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Simulation system with clock and messaging synchronization
- Patent number 10,409,321
- Issue date Sep 10, 2019
- Raytheon Company
- Terence J. McKiernan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Validating a clock tree delay
- Patent number 10,387,606
- Issue date Aug 20, 2019
- Synopsys, Inc.
- Chunyang Feng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock tree synthesis graphical user interface
- Patent number 10,380,299
- Issue date Aug 13, 2019
- Mentor Graphics Corporation
- Sivaprakasam Sunder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structure and generation method of clock distribution network
- Patent number 10,380,288
- Issue date Aug 13, 2019
- Shanghai Huali Microelectronics Corporation
- Xueyuan Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and process for simulating the behavioral effects of timing...
- Patent number 10,366,186
- Issue date Jul 30, 2019
- The Charles Stark Draper Laboratory, Inc.
- Eric Karl Mautner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parameter collapsing and corner reduction in an integrated circuit
- Patent number 10,354,047
- Issue date Jul 16, 2019
- International Business Machines Corporation
- Eric Foreman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable clock division methodology with in-context frequency c...
- Patent number 10,354,046
- Issue date Jul 16, 2019
- International Business Machines Corporation
- Naiju K. Abdul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock-gating phase algebra for clock analysis
- Patent number 10,331,822
- Issue date Jun 25, 2019
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
CLOCK CROSSING INTERFACE FOR INTEGRATED CIRCUIT GENERATION
- Publication number 20210011981
- Publication date Jan 14, 2021
- SiFive, Inc.
- Henry Cook
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK GATE LATENCY MODELING BASED ON ANALYTICAL FRAMEWORKS
- Publication number 20200401669
- Publication date Dec 24, 2020
- Samsung Electronics Co., Ltd.
- Naman GUPTA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL CLOCK TREE CONSTRUCTION BASED ON CONSTRAINTS
- Publication number 20200401179
- Publication date Dec 24, 2020
- Samsung Electronics Co., Ltd.
- Sridhar SUBRAMANIAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTIMALLY DRIVING NON-UNIFORM CLOCK MESH LOADS
- Publication number 20200117230
- Publication date Apr 16, 2020
- International Business Machines Corportation
- Matthias Ringe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock tree synthesis method
- Publication number 20190392109
- Publication date Dec 26, 2019
- REALTEK SEMICONDUCTOR CORPORATION
- EN-CHENG LIU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR A HYBRID CURRENT-MODE AND VOLTAGE-MODE INTEGR...
- Publication number 20190384349
- Publication date Dec 19, 2019
- The Regents of the University of California
- Matthew Guthaus
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PHASE ALGEBRA FOR VIRTUAL CLOCK AND MODE EXTRACTION IN HIERARCHICAL...
- Publication number 20190258772
- Publication date Aug 22, 2019
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VERIFYING SEQUENTIAL EQUIVALENCE FOR RANDOMLY INITIALIZED DESIGNS
- Publication number 20190188349
- Publication date Jun 20, 2019
- International Business Machines Corporation
- ALEXANDER IVRII
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTRIBUTED PROGRAMMABLE DELAY LINES IN A CLOCK TREE
- Publication number 20190179990
- Publication date Jun 13, 2019
- Intel Corporation
- Herman Henry Schmit
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONSTRUCTING STAGING TREES IN HIERARCHICAL CIRCUIT DESIGNS
- Publication number 20190173781
- Publication date Jun 6, 2019
- International Business Machines Corporation
- Harald Folberth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES BASED ON ELECTROMIGRATION CHARACTERISTICS OF CELL INTERC...
- Publication number 20190108304
- Publication date Apr 11, 2019
- Taiwan Semiconductor Manufacturing Co., LTD
- Kuo-Nan Yang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CELL LAYOUT OF SEMICONDUCTOR DEVICE
- Publication number 20190108302
- Publication date Apr 11, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Yi-Lin CHUANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT, SCAN SHIFT CONTROL METHOD, AND CIRCUIT DESIGN M...
- Publication number 20190080039
- Publication date Mar 14, 2019
- Kabushiki Kaisha Toshiba
- Masaki OISO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Formal Clock Network Analysis, Visualization, Verification and Gene...
- Publication number 20190034571
- Publication date Jan 31, 2019
- Synopsys, Inc.
- Mohamed Shaker Sarwary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-DIE IC LAYOUT METHODS WITH AWARENESS OF MIX AND MATCH DIE INT...
- Publication number 20180341738
- Publication date Nov 29, 2018
- The Regents of the University of California
- Andrew B. Kahng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRUCTURE AND GENERATION METHOD OF CLOCK DISTRIBUTION NETWORK
- Publication number 20180260507
- Publication date Sep 13, 2018
- SHANGHAI HUALI MICROELECTRONICS CORPORATION
- Xueyuan Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC CONFIGURATION OF A RECONFIGURABLE HUM FABRIC
- Publication number 20180225403
- Publication date Aug 9, 2018
- Wave Computing, Inc.
- Christopher John Nicol
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BLOCK-LEVEL DESIGN METHOD FOR HETEROGENEOUS PG-STRUCTURE CELLS
- Publication number 20180210993
- Publication date Jul 26, 2018
- Taiwan Semiconductor Manufacturing Co., LTD
- Yen-Hung LIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GENERATING A LAYOUT FOR AN INTEGRATED CIRCUIT
- Publication number 20180189437
- Publication date Jul 5, 2018
- International Business Machines Corporation
- Andreas H.A. Arp
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCOMMODATING ENGINEERING CHANGE ORDERS IN INTEGRATED CIRCUIT DESIGN
- Publication number 20180181687
- Publication date Jun 28, 2018
- International Business Machines Corporation
- Ayan Datta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCOMMODATING ENGINEERING CHANGE ORDERS IN INTEGRATED CIRCUIT DESIGN
- Publication number 20180181686
- Publication date Jun 28, 2018
- International Business Machines Corporation
- Ayan Datta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CALLBACK BASED CONSTRAINT PROCESSING FOR CLOCK DOMAIN INDEPENDENCE
- Publication number 20180173833
- Publication date Jun 21, 2018
- International Business Machines Corporation
- Naiju K. Abdul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Clock Jitter Emulation
- Publication number 20180129766
- Publication date May 10, 2018
- Synopsys, Inc.
- LUDOVIC MARC LARZUL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PHASE ALGEBRA FOR ANALYSIS OF HIERARCHICAL DESIGNS
- Publication number 20180107776
- Publication date Apr 19, 2018
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT DESIGN ANALYZER
- Publication number 20180082003
- Publication date Mar 22, 2018
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GLITCH-AWARE PHASE ALGEBRA FOR CLOCK ANALYSIS
- Publication number 20180075178
- Publication date Mar 15, 2018
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CALLBACK BASED CONSTRAINT PROCESSING FOR CLOCK DOMAIN INDEPENDENCE
- Publication number 20180018421
- Publication date Jan 18, 2018
- International Business Machines Corporation
- Naiju K. Abdul
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTEXT AWARE CLOCK TREE SYNTHESIS
- Publication number 20170357746
- Publication date Dec 14, 2017
- Synopsys, Inc.
- Anand K. Rajaram
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and Computer-Readable Media for Synthesizing a Multi-Corner...
- Publication number 20170351797
- Publication date Dec 7, 2017
- Drexel University
- Baris Taskin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR FUNCTIONAL VERIFICATION AND POWER ANALYSIS OF...
- Publication number 20170344682
- Publication date Nov 30, 2017
- Microsemi Solutions (U.S.), Inc.
- Theodore WILSON
- G06 - COMPUTING CALCULATING COUNTING

Clock network

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Multi-bit clock gating cell to reduce clock power

Automatic multi-clock circuit generation

Clock network analysis using harmonic balance

Reducing clock power consumption of a computer processor

Constructing staging trees in hierarchical circuit designs

Circuit design analyzer

Formal clock network analysis, visualization, verification and gene...

Reducing clock power consumption of a computer processor

Targeted delay optimization through programmable clock delays

Phase algebra for virtual clock and mode extraction in hierarchical...

Glitch-aware phase algebra for clock analysis

Controlling real time during embedded system development

Conditional phase algebra for clock analysis

Parameter collapsing and corner reduction in an integrated circuit

Generating a layout for an integrated circuit

Verifying sequential equivalence for randomly initialized designs

Clock jitter emulation

Timing-closure methodology involving clock network in hardware designs

Clock-gating phase algebra for clock analysis

Phase algebra for specifying clocks and modes in hierarchical designs

Verification support apparatus and design verification support method

Bisection methodology for on-chip variation tolerant clock signal d...

Simulation system with clock and messaging synchronization

Validating a clock tree delay

Clock tree synthesis graphical user interface

Structure and generation method of clock distribution network

System and process for simulating the behavioral effects of timing...

Parameter collapsing and corner reduction in an integrated circuit

Programmable clock division methodology with in-context frequency c...

Clock-gating phase algebra for clock analysis

Patents Applicationslast 30 patents

CLOCK CROSSING INTERFACE FOR INTEGRATED CIRCUIT GENERATION

CLOCK GATE LATENCY MODELING BASED ON ANALYTICAL FRAMEWORKS

HIERARCHICAL CLOCK TREE CONSTRUCTION BASED ON CONSTRAINTS

OPTIMALLY DRIVING NON-UNIFORM CLOCK MESH LOADS

Clock tree synthesis method

SYSTEM AND METHOD FOR A HYBRID CURRENT-MODE AND VOLTAGE-MODE INTEGR...

PHASE ALGEBRA FOR VIRTUAL CLOCK AND MODE EXTRACTION IN HIERARCHICAL...

VERIFYING SEQUENTIAL EQUIVALENCE FOR RANDOMLY INITIALIZED DESIGNS

DISTRIBUTED PROGRAMMABLE DELAY LINES IN A CLOCK TREE

CONSTRUCTING STAGING TREES IN HIERARCHICAL CIRCUIT DESIGNS

TECHNIQUES BASED ON ELECTROMIGRATION CHARACTERISTICS OF CELL INTERC...

CELL LAYOUT OF SEMICONDUCTOR DEVICE

INTEGRATED CIRCUIT, SCAN SHIFT CONTROL METHOD, AND CIRCUIT DESIGN M...

Formal Clock Network Analysis, Visualization, Verification and Gene...

MULTI-DIE IC LAYOUT METHODS WITH AWARENESS OF MIX AND MATCH DIE INT...

STRUCTURE AND GENERATION METHOD OF CLOCK DISTRIBUTION NETWORK

DYNAMIC CONFIGURATION OF A RECONFIGURABLE HUM FABRIC

BLOCK-LEVEL DESIGN METHOD FOR HETEROGENEOUS PG-STRUCTURE CELLS

GENERATING A LAYOUT FOR AN INTEGRATED CIRCUIT

ACCOMMODATING ENGINEERING CHANGE ORDERS IN INTEGRATED CIRCUIT DESIGN

ACCOMMODATING ENGINEERING CHANGE ORDERS IN INTEGRATED CIRCUIT DESIGN

CALLBACK BASED CONSTRAINT PROCESSING FOR CLOCK DOMAIN INDEPENDENCE

Clock Jitter Emulation

PHASE ALGEBRA FOR ANALYSIS OF HIERARCHICAL DESIGNS

CIRCUIT DESIGN ANALYZER

GLITCH-AWARE PHASE ALGEBRA FOR CLOCK ANALYSIS

CALLBACK BASED CONSTRAINT PROCESSING FOR CLOCK DOMAIN INDEPENDENCE

CONTEXT AWARE CLOCK TREE SYNTHESIS

Methods and Computer-Readable Media for Synthesizing a Multi-Corner...

METHOD AND SYSTEM FOR FUNCTIONAL VERIFICATION AND POWER ANALYSIS OF...