Computer-aided design and analysis of circuits and semiconductor masks

Industry

US Classification
716

US Patent Classification (USPC) is no longer used by USPTO since June 2015. Please refer to similar CPC classifications / industries.

Current Industry

716Computer-aided design

Industries

Patents Grantslast 30 patents

Information Patent Grant
Method and system for forming high accuracy patterns using charged...
- Patent number 9,043,734
- Issue date May 26, 2015
- D2S, Inc.
- Akira Fujimura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synthesis of fast squarer functional blocks
- Patent number 9,043,735
- Issue date May 26, 2015
- Cadence Design Systems, Inc.
- Sabyasachi Das
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit design support method, computer product, and circuit design...
- Patent number 9,043,736
- Issue date May 26, 2015
- Fujitsu Semiconductor Limited
- Yukinori Setohara
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement based arithmetic operator selection
- Patent number 9,043,739
- Issue date May 26, 2015
- Altera Corporation
- Steve Casselman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fabrication of a magnetic tunnel junction device
- Patent number 9,043,740
- Issue date May 26, 2015
- QUALCOMM Incorporated
- Kangho Lee
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Methods and systems for global knowledge sharing to provide correct...
- Patent number 9,043,336
- Issue date May 26, 2015
- Applied Materials, Inc.
- Erik Wolf
- G05 - CONTROLLING REGULATING
Information Patent Grant
Integrated circuit design verification through forced clock glitches
- Patent number 9,043,737
- Issue date May 26, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Jayanta Bahadra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automated residual material detection
- Patent number 9,043,743
- Issue date May 26, 2015
- International Business Machines Corporation
- Jeffrey C. Maling
- G01 - MEASURING TESTING
Information Patent Grant
Magnetic tunnel junction device and fabrication
- Patent number 9,041,131
- Issue date May 26, 2015
- QUALCOMM Incorporated
- Xia Li
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory controller with transaction-queue-monitoring power mode circ...
- Patent number 9,043,633
- Issue date May 26, 2015
- Rambus Inc.
- Frederick A. Ware
- G11 - INFORMATION STORAGE
Information Patent Grant
Machine-learning based datapath extraction
- Patent number 9,043,738
- Issue date May 26, 2015
- International Business Machines Corporation
- Samuel I. Ward
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Legalizing a portion of a circuit layout
- Patent number 9,043,741
- Issue date May 26, 2015
- Synopsys, Inc.
- Shabbir H. Batterywala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods, systems, and articles of manufacture for implementing phys...
- Patent number 9,043,742
- Issue date May 26, 2015
- Cadence Design Systems, Inc.
- Thaddeus C. McCracken
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for generating gate-level activity data for us...
- Patent number 9,038,006
- Issue date May 19, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Lior Moheban
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prediction of dynamic current waveform and spectrum in a semiconduc...
- Patent number 9,038,007
- Issue date May 19, 2015
- Altera Corporation
- Peter Boyle
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Early design cycle optimization
- Patent number 9,038,009
- Issue date May 19, 2015
- International Business Machines Corporation
- Charles Jay Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for phase predictive impedance loss model calib...
- Patent number 9,037,447
- Issue date May 19, 2015
- Covidien LP
- Donald W. Heckel
- A61 - MEDICAL OR VETERINARY SCIENCE HYGIENE
Information Patent Grant
System and method for containing analog verification IP
- Patent number 9,038,008
- Issue date May 19, 2015
- Cadence Design Systems, Inc.
- Donald J. O'Riordan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sequential state elements in triple-mode redundant (TMR) state mach...
- Patent number 9,038,012
- Issue date May 19, 2015
- Arizona Board of Regents on behalf of Arizona State University
- Lawrence T. Clark
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Interconnection substrate design supporting device, method of desig...
- Patent number 9,036,365
- Issue date May 19, 2015
- NEC Corporation
- Manabu Kusumoto
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method and system for critical dimension uniformity using charged p...
- Patent number 9,038,003
- Issue date May 19, 2015
- D2S, Inc.
- Ryan Pearman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automated integrated circuit design documentation
- Patent number 9,038,004
- Issue date May 19, 2015
- International Business Machines Corporation
- Keith A. Ford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Electrical-thermal co-simulation with joule heating and convection...
- Patent number 9,037,446
- Issue date May 19, 2015
- Georgia Tech Research Corporation
- Jianyong Xie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Network synthesis design of microwave acoustic wave filters
- Patent number 9,038,005
- Issue date May 19, 2015
- Resonant Inc.
- Patrick J. Turner
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Horizontal interconnects crosstalk optimization
- Patent number 9,038,011
- Issue date May 19, 2015
- QUALCOMM Incorporated
- Shree Krishna Pandey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit partitioning and trace assignment in circuit design
- Patent number 9,038,013
- Issue date May 19, 2015
- Synopsys, Inc.
- Awartika Pandey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Load balancing on hetrogenous processing cluster based on exceeded...
- Patent number 9,038,088
- Issue date May 19, 2015
- NEC Laboratories America, Inc.
- Rajat Phull
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for semiconductor design hierarchy analysis and t...
- Patent number 9,038,002
- Issue date May 19, 2015
- Cadence Design Systems, Inc.
- Vishnu Govind Kamat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DRC format for stacked CMOS design
- Patent number 9,038,010
- Issue date May 19, 2015
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Yao-Jen Chuang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for forming patterns with charged particle beam l...
- Patent number 9,034,542
- Issue date May 19, 2015
- D2S, Inc.
- Akira Fujimura
- B82 - NANO-TECHNOLOGY

Patents Applicationslast 30 patents

Information Patent Application
POWER GATE SWITCH ARCHITECTURE
- Publication number 20150145555
- Publication date May 28, 2015
- Samsung Electronics Co., Ltd.
- Young KOOG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPTIMIZING LITHOGRAPHY MASKS FOR VLSI CHIP DESIGN
- Publication number 20150149971
- Publication date May 28, 2015
- International Business Machines Corporation
- Stefan Apostol
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT OF AN INTEGRATED CIRCUIT
- Publication number 20150149976
- Publication date May 28, 2015
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Li-Chun Tien
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, DESIGN APPARATUS, AND PROGRAM PRODUCT FOR INCREMENTAL DESIG...
- Publication number 20150149972
- Publication date May 28, 2015
- NEC Corporation
- Benjamin Carrion Schafer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIAGNOSIS DEVICE, CONTROL METHOD OF DIAGNOSIS DEVICE, AND RECORDING...
- Publication number 20150149974
- Publication date May 28, 2015
- Fujitsu Limited
- Yukinobu Nonomura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT DESIGN FOR ELECTRON-BEAM HIGH VOLUME MANUFACTURING
- Publication number 20150149969
- Publication date May 28, 2015
- Taiwan Semiconductor Manufacturing Co., LTD
- Hung-Chun Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIMULATION METHOD, SIMULATION PROGRAM, PROCESS CONTROL SYSTEM, SIMU...
- Publication number 20150149970
- Publication date May 28, 2015
- SONY CORPORATION
- Nobuyuki Kuboi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARTITIONING METHOD AND SYSTEM FOR 3D IC
- Publication number 20150149977
- Publication date May 28, 2015
- Taiwan Semiconductor Manufacturing Co., LTD
- Heng Kai LIU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMPLEMENTING BURIED FET UTILIZING DRAIN OF FINFET AS GATE OF BURIED...
- Publication number 20150145047
- Publication date May 28, 2015
- International Business Machines Corporation
- Karl R. Erickson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PLACEMENT OF MONOLITHIC INTER-TIER VIAS (MIVs) WITHIN MONOLITHIC TH...
- Publication number 20150145143
- Publication date May 28, 2015
- QUALCOMM Incorporated
- Kambiz Samadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR CREATING DIGITAL CIRCUITS OF A FEEDBACK CONTROL SYSTEM T...
- Publication number 20150145558
- Publication date May 28, 2015
- UNIVERSITA' DEGLI STUDI DI GENOVA
- Marco Storace
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THIRD PARTY COMPONENT DEBUGGING FOR INTEGRATED CIRCUIT DESIGN
- Publication number 20150149973
- Publication date May 28, 2015
- Mentor Graphics Corporation
- Charles W. Selvidge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR PROVIDING A DESIGN DIAGRAM OF A SEMICONDUC...
- Publication number 20150149975
- Publication date May 28, 2015
- Samsung Electronics Co., Ltd.
- JEONG-SIK YU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEQUENTIAL CLOCK GATING USING NET ACTIVITY AND XOR TECHNIQUE ON SEM...
- Publication number 20150143307
- Publication date May 21, 2015
- ATRENTA, INC.
- Solaiman Rahim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Semiconductor Device Design Methods and Conductive Bump Pattern Enh...
- Publication number 20150143324
- Publication date May 21, 2015
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Tzu-Yu Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Target Point Generation for Optical Proximity Correction
- Publication number 20150143304
- Publication date May 21, 2015
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ming-Hui Chih
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RETICLE DATA DECOMPOSITION FOR FOCAL PLANE DETERMINATION IN LITHOGR...
- Publication number 20150143305
- Publication date May 21, 2015
- International Business Machines Corporation
- Stephen E. Greco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS FOR FABRICATING HIGH-DENSITY INTEGRATED CIRCUIT DEVICES
- Publication number 20150143306
- Publication date May 21, 2015
- Synopsys, Inc.
- VICTOR MOROZ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIMULATION SYSTEM AND METHOD FOR TESTING A SIMULATION OF A DEVICE A...
- Publication number 20150143308
- Publication date May 21, 2015
- FREESCALE SEMICONDUCTOR, INC.
- Mehul Shroff
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR DESIGNING SEMICONDU...
- Publication number 20150143311
- Publication date May 21, 2015
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chi-Wen CHANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF DESIGNING FIN FIELD EFFECT TRANSISTOR (FINFET)-BASED CIRC...
- Publication number 20150143314
- Publication date May 21, 2015
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chin-Sheng CHEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Generating Guiding Patterns For Directed Self-Assembly
- Publication number 20150143323
- Publication date May 21, 2015
- Mentor Graphics Corporation
- Juan Andres Torres Robles
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CELL-BASED IC LAYOUT SYSTEM AND CELL-BASED IC LAYOUT METHOD
- Publication number 20150137202
- Publication date May 21, 2015
- Rohm Co. Ltd.
- Yoshiharu Kito
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF DESIGNING PATTERNS OF SEMICONDUCTOR DEVICES
- Publication number 20150143312
- Publication date May 21, 2015
- Samsung Electronics Co., Ltd.
- Joong-Won JEON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Grouping Layout Features For Directed Self Assembly
- Publication number 20150143313
- Publication date May 21, 2015
- Mentor Graphics Corporation
- Juan Andres Torres Robles
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHODS FOR PARTITIONING AN INTEGRATED CIRCUIT DESIGN...
- Publication number 20150143316
- Publication date May 21, 2015
- SILICONPRO INC.
- Mohamed Samy HOSNY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Determination Of Electromigration Features
- Publication number 20150143317
- Publication date May 21, 2015
- Mentor Graphics Corporation
- Patrick Gibson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR MODELING RESISTANC...
- Publication number 20150143325
- Publication date May 21, 2015
- International Business Machines Corporation
- Ning Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT CEFF MODEL FOR GATE OUTPUT SLEW COMPUTATION IN EARLY SYNT...
- Publication number 20150143326
- Publication date May 21, 2015
- International Business Machines Corporation
- Charles J. Alpert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WORDLINE DECODER CIRCUITS FOR EMBEDDED CHARGE TRAP MULTI-TIME-PROGR...
- Publication number 20150138867
- Publication date May 21, 2015
- International Business Machines Corporation
- Toshiaki Kirihata
- G06 - COMPUTING CALCULATING COUNTING

Computer-aided design and analysis of circuits and semiconductor masks

Industry

Current Industry

Patents Grantslast 30 patents

Method and system for forming high accuracy patterns using charged...

Synthesis of fast squarer functional blocks

Circuit design support method, computer product, and circuit design...

Placement based arithmetic operator selection

Fabrication of a magnetic tunnel junction device

Methods and systems for global knowledge sharing to provide correct...

Integrated circuit design verification through forced clock glitches

Automated residual material detection

Magnetic tunnel junction device and fabrication

Memory controller with transaction-queue-monitoring power mode circ...

Machine-learning based datapath extraction

Legalizing a portion of a circuit layout

Methods, systems, and articles of manufacture for implementing phys...

Method and apparatus for generating gate-level activity data for us...

Prediction of dynamic current waveform and spectrum in a semiconduc...

Early design cycle optimization

Systems and methods for phase predictive impedance loss model calib...

System and method for containing analog verification IP

Sequential state elements in triple-mode redundant (TMR) state mach...

Interconnection substrate design supporting device, method of desig...

Method and system for critical dimension uniformity using charged p...

Automated integrated circuit design documentation

Electrical-thermal co-simulation with joule heating and convection...

Network synthesis design of microwave acoustic wave filters

Horizontal interconnects crosstalk optimization

Circuit partitioning and trace assignment in circuit design

Load balancing on hetrogenous processing cluster based on exceeded...

Method and system for semiconductor design hierarchy analysis and t...

DRC format for stacked CMOS design

Method and system for forming patterns with charged particle beam l...

Patents Applicationslast 30 patents

POWER GATE SWITCH ARCHITECTURE

OPTIMIZING LITHOGRAPHY MASKS FOR VLSI CHIP DESIGN

LAYOUT OF AN INTEGRATED CIRCUIT

METHOD, DESIGN APPARATUS, AND PROGRAM PRODUCT FOR INCREMENTAL DESIG...

DIAGNOSIS DEVICE, CONTROL METHOD OF DIAGNOSIS DEVICE, AND RECORDING...

LAYOUT DESIGN FOR ELECTRON-BEAM HIGH VOLUME MANUFACTURING

SIMULATION METHOD, SIMULATION PROGRAM, PROCESS CONTROL SYSTEM, SIMU...

PARTITIONING METHOD AND SYSTEM FOR 3D IC

IMPLEMENTING BURIED FET UTILIZING DRAIN OF FINFET AS GATE OF BURIED...

PLACEMENT OF MONOLITHIC INTER-TIER VIAS (MIVs) WITHIN MONOLITHIC TH...

METHOD FOR CREATING DIGITAL CIRCUITS OF A FEEDBACK CONTROL SYSTEM T...

THIRD PARTY COMPONENT DEBUGGING FOR INTEGRATED CIRCUIT DESIGN

METHOD AND APPARATUS FOR PROVIDING A DESIGN DIAGRAM OF A SEMICONDUC...

SEQUENTIAL CLOCK GATING USING NET ACTIVITY AND XOR TECHNIQUE ON SEM...

Semiconductor Device Design Methods and Conductive Bump Pattern Enh...

Target Point Generation for Optical Proximity Correction

RETICLE DATA DECOMPOSITION FOR FOCAL PLANE DETERMINATION IN LITHOGR...

METHODS FOR FABRICATING HIGH-DENSITY INTEGRATED CIRCUIT DEVICES

SIMULATION SYSTEM AND METHOD FOR TESTING A SIMULATION OF A DEVICE A...

METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR DESIGNING SEMICONDU...

METHOD OF DESIGNING FIN FIELD EFFECT TRANSISTOR (FINFET)-BASED CIRC...

Generating Guiding Patterns For Directed Self-Assembly

CELL-BASED IC LAYOUT SYSTEM AND CELL-BASED IC LAYOUT METHOD

METHOD OF DESIGNING PATTERNS OF SEMICONDUCTOR DEVICES

Grouping Layout Features For Directed Self Assembly

APPARATUS AND METHODS FOR PARTITIONING AN INTEGRATED CIRCUIT DESIGN...

Determination Of Electromigration Features

METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR MODELING RESISTANC...

EFFICIENT CEFF MODEL FOR GATE OUTPUT SLEW COMPUTATION IN EARLY SYNT...

WORDLINE DECODER CIRCUITS FOR EMBEDDED CHARGE TRAP MULTI-TIME-PROGR...