Decoding for concurrent execution

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CPC
G06F9/3818

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F9/00Arrangements for programme control

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G06F9/3818Decoding for concurrent execution

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Patents Grantslast 30 patents

Information Patent Grant
Implicit fence for write messages
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Systems, methods, and apparatuses for dot production operations
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- Robert Valentine
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Look-up table write
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Performance and power efficient processor when switching between fe...
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Systems, methods, and apparatus for tile configuration
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Information Patent Grant
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Information Patent Grant
Supporting 8-bit floating point format operands in a computing arch...
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Data initialization techniques
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Information Patent Grant
Look-up table initialize
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Information Patent Grant
Two address translations from a single table look-aside buffer read
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Information Patent Grant
Loop driven region based frontend translation control for performan...
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Processing of data synchronization barrier instructions
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Systems and methods for dynamic control of a secure mode of operati...
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Generating masks from decoded instructions to apply to fetched inst...
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Graphics processor data access and sharing
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Thread forward progress and/or quality of service
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Microprocessor with time count based instruction execution and replay
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Multi-tile memory management
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Systems, methods, and apparatuses for tile load, multiplication and...
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Coprocessors with bypass optimization, variable grid architecture,...
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Tracking streaming engine vector predicates to control processor ex...
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Device, system and method to efficiently update a secure arbitratio...
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Cache structure and utilization
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Systems, methods, and apparatuses for tile matrix multiplication an...
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Systolic disaggregation within a matrix accelerator architecture
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Information Patent Grant
Coprocessors with bypass optimization, variable grid architecture,...
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ISA opcode parameterization and opcode space layout randomization
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- Jason Agron
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Information Patent Grant
Systems and methods for performing instructions to convert to 16-bi...
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- Issue date Oct 29, 2024
- Intel Corporation
- Alexander F. Heinecke
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
GRAPHICS PROCESSOR DATA ACCESS AND SHARING
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DATA INITIALIZATION TECHNIQUES
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Processing of Data Synchronization Barrier Instructions
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MECHANISM FOR INSTRUCTION FUSION
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DECODING METHOD OF SIMULTANEOUSLY MULTI-THREADING PROCESSOR, PROCES...
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MULTI-TILE MEMORY MANAGEMENT
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SYSTEMS, METHODS, AND APPARATUSES FOR TILE TRANSPOSE
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SYSTEMS, METHODS, AND APPARATUSES FOR TILE MATRIX MULTIPLICATION AN...
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SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION
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CACHE STRUCTURE AND UTILIZATION
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TRACKING STREAMING ENGINE VECTOR PREDICATES TO CONTROL PROCESSOR EX...
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SYSTOLIC DISAGGREGATION WITHIN A MATRIX ACCELERATOR ARCHITECTURE
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Coprocessors with Bypass Optimization, Variable Grid Architecture,...
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GRAPHICS PROCESSOR OPERATION SCHEDULING FOR DETERMINISTIC LATENCY
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- Intel Corporation
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AUTO-PREDICATION FOR LOOPS WITH DYNAMICALLY VARYING INTERATION COUNTS
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MULTI-TILE MEMORY MANAGEMENT
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SYSTEMS, METHODS, AND APPARATUSES FOR TILE LOAD
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SYSTEMS, APPARATUSES, AND METHODS FOR ADDITION OF PARTIAL PRODUCTS
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METHOD AND APPARATUS FOR VECTOR PERMUTATION
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PROCESSOR ARCHITECTURE WITH MEMORY ACCESS CIRCUIT
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CACHE STRUCTURE AND UTILIZATION
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COMPRESSION TECHNIQUES
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LOOK-UP TABLE READ
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METHOD AND APPARATUS FOR PERMUTING STREAMED DATA ELEMENTS
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RUNTIME CONFIGURABLE MODULAR PROCESSING TILE
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GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...
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- Subramaniam Maiyuran
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Vector Based Matrix Multiplication
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SORTING VECTOR ELEMENTS USING A COUNT VALUE
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- TEXAS INSTRUMENTS INCORPORATED
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Information Patent Application
Multi-tile Memory Management for Detecting Cross Tile Access Provid...
- Publication number 20240345990
- Publication date Oct 17, 2024
- Intel Corporation
- Lakshminarayanan Striramassarma
- G06 - COMPUTING CALCULATING COUNTING

Decoding for concurrent execution

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Implicit fence for write messages

Systems, methods, and apparatuses for dot production operations

Look-up table write

Performance and power efficient processor when switching between fe...

Generating and providing proposed digital actions in high-dimension...

Systems, methods, and apparatus for tile configuration

Systems, methods, and apparatuses for matrix add, subtract, and mul...

Supporting 8-bit floating point format operands in a computing arch...

Data initialization techniques

Look-up table initialize

Two address translations from a single table look-aside buffer read

Loop driven region based frontend translation control for performan...

Processing of data synchronization barrier instructions

Systems and methods for dynamic control of a secure mode of operati...

Generating masks from decoded instructions to apply to fetched inst...

Systems and methods for improving cache efficiency and utilization

Graphics processor data access and sharing

Thread forward progress and/or quality of service

Microprocessor with time count based instruction execution and replay

Multi-tile memory management

Systems, methods, and apparatuses for tile load, multiplication and...

Coprocessors with bypass optimization, variable grid architecture,...

Tracking streaming engine vector predicates to control processor ex...

Device, system and method to efficiently update a secure arbitratio...

Cache structure and utilization

Systems, methods, and apparatuses for tile matrix multiplication an...

Systolic disaggregation within a matrix accelerator architecture

Coprocessors with bypass optimization, variable grid architecture,...

ISA opcode parameterization and opcode space layout randomization

Systems and methods for performing instructions to convert to 16-bi...

Patents Applicationslast 30 patents

GRAPHICS PROCESSOR DATA ACCESS AND SHARING

DATA INITIALIZATION TECHNIQUES

Processing of Data Synchronization Barrier Instructions

MECHANISM FOR INSTRUCTION FUSION

DECODING METHOD OF SIMULTANEOUSLY MULTI-THREADING PROCESSOR, PROCES...

MULTI-TILE MEMORY MANAGEMENT

SYSTEMS AND METHODS FOR PERFORMING INSTRUCTIONS TO CONVERT TO 16-BI...

SYSTEMS, METHODS, AND APPARATUSES FOR TILE TRANSPOSE

SYSTEMS, METHODS, AND APPARATUSES FOR TILE MATRIX MULTIPLICATION AN...

SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION

CACHE STRUCTURE AND UTILIZATION

TRACKING STREAMING ENGINE VECTOR PREDICATES TO CONTROL PROCESSOR EX...

SYSTOLIC DISAGGREGATION WITHIN A MATRIX ACCELERATOR ARCHITECTURE

Coprocessors with Bypass Optimization, Variable Grid Architecture,...

GRAPHICS PROCESSOR OPERATION SCHEDULING FOR DETERMINISTIC LATENCY

AUTO-PREDICATION FOR LOOPS WITH DYNAMICALLY VARYING INTERATION COUNTS

MULTI-TILE MEMORY MANAGEMENT

SYSTEMS, METHODS, AND APPARATUSES FOR TILE LOAD

SYSTEMS, APPARATUSES, AND METHODS FOR ADDITION OF PARTIAL PRODUCTS

METHOD AND APPARATUS FOR VECTOR PERMUTATION

PROCESSOR ARCHITECTURE WITH MEMORY ACCESS CIRCUIT

CACHE STRUCTURE AND UTILIZATION

COMPRESSION TECHNIQUES

LOOK-UP TABLE READ

METHOD AND APPARATUS FOR PERMUTING STREAMED DATA ELEMENTS

RUNTIME CONFIGURABLE MODULAR PROCESSING TILE

GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...

Vector Based Matrix Multiplication

SORTING VECTOR ELEMENTS USING A COUNT VALUE

Multi-tile Memory Management for Detecting Cross Tile Access Provid...