Details of translation look-aside buffer [TLB]

Industry

CPC
G06F2212/68

This industry / category may be too specific. Please go to a parent level for more data

Parent Industries

GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures

Current Industry

G06F2212/68Details of translation look-aside buffer [TLB]

Industries

Patents Grantslast 30 patents

Information Patent Grant
Dynamic tuning of larger pages during runtime
- Patent number 12,147,352
- Issue date Nov 19, 2024
- International Business Machines Corporation
- Naijie Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for shared virtual memory to manage data coher...
- Patent number 12,147,346
- Issue date Nov 19, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Translation support for a virtual cache
- Patent number 12,141,076
- Issue date Nov 12, 2024
- International Business Machines Corporation
- Markus Helms
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses and methods for a processor architecture
- Patent number 12,130,740
- Issue date Oct 29, 2024
- Intel Corporation
- Jason W. Brandt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware translation request retry mechanism
- Patent number 12,124,381
- Issue date Oct 22, 2024
- ATI Technologies ULC
- Edwin Pang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Translation lookaside buffer entry allocation system and method
- Patent number 12,105,634
- Issue date Oct 1, 2024
- ATI Technologies ULC
- Edwin Pang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for vector permutation
- Patent number 12,105,635
- Issue date Oct 1, 2024
- Texas Instruments Incorporated
- Timothy David Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Process dedicated in-memory translation lookaside buffers (TLBs) (m...
- Patent number 12,093,186
- Issue date Sep 17, 2024
- Microsoft Technology Licensing, LLC
- Madhavan Thirukkurungudi Venkataraman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for permuting streamed data elements
- Patent number 12,086,074
- Issue date Sep 10, 2024
- Texas Instruments Incorporated
- Soujanya Narnur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing translation lookaside buffer searches for splintered pages
- Patent number 12,079,140
- Issue date Sep 3, 2024
- Apple Inc.
- John D. Pape
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Highly integrated scalable, flexible DSP megamodule architecture
- Patent number 12,072,812
- Issue date Aug 27, 2024
- Texas Instruments Incorporated
- Timothy D. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Handling address translation requests
- Patent number 12,066,953
- Issue date Aug 20, 2024
- ARM Limited
- Matthew Lucien Evans
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Page table hooks to memory types
- Patent number 12,066,951
- Issue date Aug 20, 2024
- Micron Technology, Inc.
- Samuel E. Bradshaw
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache management operations using streaming engine
- Patent number 12,050,914
- Issue date Jul 30, 2024
- Texas Instruments Incorporated
- Joseph Raymond Michael Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implied bit handling in floating point mul...
- Patent number 12,045,172
- Issue date Jul 23, 2024
- Texas Instruments Incorporated
- Mujibur Rahman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Access log and address translation log for a processor
- Patent number 12,032,487
- Issue date Jul 9, 2024
- Advanced Micro Devices, Inc.
- Benjamin T. Sander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for vector sorting
- Patent number 12,032,490
- Issue date Jul 9, 2024
- Texas Instruments Incorporated
- Timothy David Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transient side-channel aware architecture for cryptographic computing
- Patent number 12,032,486
- Issue date Jul 9, 2024
- Intel Corporation
- Abhishek Basak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
64-bit virtual addresses having metadata bit(s) and canonicality ch...
- Patent number 12,032,485
- Issue date Jul 9, 2024
- Intel Corporation
- Vedvyas Shanbhogue
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods of operating host device and storage device, and electronic...
- Patent number 12,026,101
- Issue date Jul 2, 2024
- Samsung Electronics Co., Ltd.
- Daejun Park
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for dual issue multiply instructions
- Patent number 12,019,559
- Issue date Jun 25, 2024
- Texas Instruments Incorporated
- Timothy David Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-core processor and storage device
- Patent number 12,019,581
- Issue date Jun 25, 2024
- Samsung Electronics Co., Ltd.
- Hyungjin Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Error avoidance for partially programmed blocks of a memory device
- Patent number 12,013,792
- Issue date Jun 18, 2024
- Micron Technology, Inc.
- Li-Te Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for vector based matrix multiplication
- Patent number 12,007,904
- Issue date Jun 11, 2024
- Texas Instruments Incorporated
- Asheesh Bhardwaj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory access compression using clear code for tile pixels
- Patent number 12,001,344
- Issue date Jun 4, 2024
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Supporting secure memory intent
- Patent number 11,995,001
- Issue date May 28, 2024
- Intel Corporation
- Krystof C. Zmudzinski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Storage array invalidation maintenance
- Patent number 11,989,131
- Issue date May 21, 2024
- Apple Inc.
- Sreevathsa Ramachandra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Translation lookaside buffer prewarming
- Patent number 11,954,044
- Issue date Apr 9, 2024
- Texas Instruments Incorporated
- Daniel Brad Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Buffer overflow trapping
- Patent number 11,947,465
- Issue date Apr 2, 2024
- International Business Machines Corporation
- Michael Peter Lyons
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Handling memory requests
- Patent number 11,941,430
- Issue date Mar 26, 2024
- Imagination Technologies Limited
- Mark Landers
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
CACHE MANAGEMENT OPERATIONS USING STREAMING ENGINE
- Publication number 20240385840
- Publication date Nov 21, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Joseph Raymond Michael Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR PERMUTING STREAMED DATA ELEMENTS
- Publication number 20240378158
- Publication date Nov 14, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Soujanya Narnur
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Vector Based Matrix Multiplication
- Publication number 20240354259
- Publication date Oct 24, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Asheesh Bhardwaj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SORTING VECTOR ELEMENTS USING A COUNT VALUE
- Publication number 20240354260
- Publication date Oct 24, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Timothy David Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR IMPLIED BIT HANDLING IN FLOATING POINT MUL...
- Publication number 20240330203
- Publication date Oct 3, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Mujibur Rahman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ERROR AVOIDANCE FOR PARTIALLY PROGRAMMED BLOCKS OF A MEMORY DEVICE
- Publication number 20240311311
- Publication date Sep 19, 2024
- Li-Te Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR REDUCED POWER TLB MANAGEMENT
- Publication number 20240311312
- Publication date Sep 19, 2024
- Intel Corporation
- Jason BRANDT
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and Apparatus for Dual Issue Multiply Instructions
- Publication number 20240311313
- Publication date Sep 19, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Timothy David Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR ADJUSTING CACHE ALLOCATED FOR READ LOOK AHEAD
- Publication number 20240303193
- Publication date Sep 12, 2024
- SK HYNIX INC.
- Byoung Min JIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTROLLER FOR LOCKING OF SELECTED CACHE REGIONS
- Publication number 20240232078
- Publication date Jul 11, 2024
- Andrew J. HERDRICH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC TUNING OF LARGER PAGES DURING RUNTIME
- Publication number 20240232098
- Publication date Jul 11, 2024
- International Business Machines Corporation
- Naijie Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiple Multiplication Units in a Data Path
- Publication number 20240211411
- Publication date Jun 27, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Mujibur Rahman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Resource Management Method and Corresponding Apparatus
- Publication number 20240202031
- Publication date Jun 20, 2024
- Huawei Technologies Co., Ltd
- Yunfeng Ye
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSLATION LOOKASIDE BUFFER PREWARMING
- Publication number 20240184715
- Publication date Jun 6, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Daniel Brad WU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VIRTUALIZED-IN-HARDWARE INPUT OUTPUT MEMORY MANAGEMENT
- Publication number 20240160353
- Publication date May 16, 2024
- MIPS Tech, LLC
- Sanjay Patel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID SCHEME FOR PERFORMING TRANSLATION LOOKASIDE BUFFER (TLB) SHO...
- Publication number 20240152465
- Publication date May 9, 2024
- VMware LLC
- Andrei Warkentin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR SHARED VIRTUAL MEMORY TO MANAGE DATA COHER...
- Publication number 20240152457
- Publication date May 9, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MAPPING NON-TYPED MEMORY ACCESS TO TYPED MEMORY ACCESS
- Publication number 20240152464
- Publication date May 9, 2024
- Micron Technology, Inc.
- Kenneth Marion Curewitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC TUNING OF LARGER PAGES DURING RUNTIME
- Publication number 20240134805
- Publication date Apr 25, 2024
- International Business Machines Corporation
- Naijie Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SOFTWARE-HARDWARE MEMORY MANAGEMENT MODES
- Publication number 20240126703
- Publication date Apr 18, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Timothy D. ANDERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Translating Virtual Memory Addresses to Physical Memory Addresses
- Publication number 20240111687
- Publication date Apr 4, 2024
- MIPS Tech, LLC
- James Robinson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESS DEDICATED IN-MEMORY TRANSLATION LOOKASIDE BUFFERS (TLBs) (m...
- Publication number 20240028522
- Publication date Jan 25, 2024
- Microsoft Technology Licensing, LLC
- Madhavan Thirukkurungudi VENKATARAMAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NEURAL PROCESSING DEVICE AND METHOD FOR USING SHARED PAGE TABLE THE...
- Publication number 20230418695
- Publication date Dec 28, 2023
- Rebellions Inc.
- Seokju Yoon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRANSLATION LOOKASIDE BUFFER (TLB) PREFETCHER WITH MULTI- LEVEL TLB...
- Publication number 20230418763
- Publication date Dec 28, 2023
- Benoy Alexander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY ARRAY PAGE TABLE WALK
- Publication number 20230401158
- Publication date Dec 14, 2023
- Micron Technology, Inc.
- Perry V. Lea
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ERROR AVOIDANCE FOR PARTIALLY PROGRAMMED BLOCKS OF A MEMORY DEVICE
- Publication number 20230393991
- Publication date Dec 7, 2023
- Li-Te Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR BROADCAST CACHE INVALIDATION
- Publication number 20230367714
- Publication date Nov 16, 2023
- Open Text SA ULC
- Michael Gerard Jaskiewicz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR ADDRESS TRANSLATION
- Publication number 20230333990
- Publication date Oct 19, 2023
- Samsung Electronics Co., Ltd.
- Daniel Lee HELMICK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROVIDING FINE GRAIN ACCESS TO PACKAGE MEMORY
- Publication number 20230315334
- Publication date Oct 5, 2023
- Intel Corporation
- Abhishek Anil SHARMA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Storage Array Invalidation Maintenance
- Publication number 20230305965
- Publication date Sep 28, 2023
- Apple Inc.
- Sreevathsa Ramachandra
- G06 - COMPUTING CALCULATING COUNTING

Details of translation look-aside buffer [TLB]

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Dynamic tuning of larger pages during runtime

Method and apparatus for shared virtual memory to manage data coher...

Translation support for a virtual cache

Apparatuses and methods for a processor architecture

Hardware translation request retry mechanism

Translation lookaside buffer entry allocation system and method

Method and apparatus for vector permutation

Process dedicated in-memory translation lookaside buffers (TLBs) (m...

Method and apparatus for permuting streamed data elements

Reducing translation lookaside buffer searches for splintered pages

Highly integrated scalable, flexible DSP megamodule architecture

Handling address translation requests

Page table hooks to memory types

Cache management operations using streaming engine

Method and apparatus for implied bit handling in floating point mul...

Access log and address translation log for a processor

Method and apparatus for vector sorting

Transient side-channel aware architecture for cryptographic computing

64-bit virtual addresses having metadata bit(s) and canonicality ch...

Methods of operating host device and storage device, and electronic...

Method and apparatus for dual issue multiply instructions

Multi-core processor and storage device

Error avoidance for partially programmed blocks of a memory device

Method and apparatus for vector based matrix multiplication

Memory access compression using clear code for tile pixels

Supporting secure memory intent

Storage array invalidation maintenance

Translation lookaside buffer prewarming

Buffer overflow trapping

Handling memory requests

Patents Applicationslast 30 patents

CACHE MANAGEMENT OPERATIONS USING STREAMING ENGINE

METHOD AND APPARATUS FOR PERMUTING STREAMED DATA ELEMENTS

Vector Based Matrix Multiplication

SORTING VECTOR ELEMENTS USING A COUNT VALUE

METHOD AND APPARATUS FOR IMPLIED BIT HANDLING IN FLOATING POINT MUL...

ERROR AVOIDANCE FOR PARTIALLY PROGRAMMED BLOCKS OF A MEMORY DEVICE

APPARATUS AND METHOD FOR REDUCED POWER TLB MANAGEMENT

Method and Apparatus for Dual Issue Multiply Instructions

APPARATUS AND METHOD FOR ADJUSTING CACHE ALLOCATED FOR READ LOOK AHEAD

CONTROLLER FOR LOCKING OF SELECTED CACHE REGIONS

DYNAMIC TUNING OF LARGER PAGES DURING RUNTIME

Multiple Multiplication Units in a Data Path

Resource Management Method and Corresponding Apparatus

TRANSLATION LOOKASIDE BUFFER PREWARMING

VIRTUALIZED-IN-HARDWARE INPUT OUTPUT MEMORY MANAGEMENT

HYBRID SCHEME FOR PERFORMING TRANSLATION LOOKASIDE BUFFER (TLB) SHO...

METHOD AND APPARATUS FOR SHARED VIRTUAL MEMORY TO MANAGE DATA COHER...

MAPPING NON-TYPED MEMORY ACCESS TO TYPED MEMORY ACCESS

DYNAMIC TUNING OF LARGER PAGES DURING RUNTIME

SOFTWARE-HARDWARE MEMORY MANAGEMENT MODES

Translating Virtual Memory Addresses to Physical Memory Addresses

PROCESS DEDICATED IN-MEMORY TRANSLATION LOOKASIDE BUFFERS (TLBs) (m...

NEURAL PROCESSING DEVICE AND METHOD FOR USING SHARED PAGE TABLE THE...

TRANSLATION LOOKASIDE BUFFER (TLB) PREFETCHER WITH MULTI- LEVEL TLB...

MEMORY ARRAY PAGE TABLE WALK

ERROR AVOIDANCE FOR PARTIALLY PROGRAMMED BLOCKS OF A MEMORY DEVICE

SYSTEM AND METHOD FOR BROADCAST CACHE INVALIDATION

SYSTEMS AND METHODS FOR ADDRESS TRANSLATION

PROVIDING FINE GRAIN ACCESS TO PACKAGE MEMORY

Storage Array Invalidation Maintenance