Devices capable of handling different types of numbers

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G06F2207/3812

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled

Current Industry

G06F2207/3812Devices capable of handling different types of numbers

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Packed 16 bits instruction pipeline
- Patent number 11,880,683
- Issue date Jan 23, 2024
- Advanced Micro Devices, Inc.
- Jiasheng Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for efficient binary and ternary support in fu...
- Patent number 11,836,464
- Issue date Dec 5, 2023
- Intel Corporation
- Aditya Varma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for efficient binary and ternary support in fu...
- Patent number 11,366,636
- Issue date Jun 21, 2022
- Intel Corporation
- Aditya Varma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multimodal digital multiplication circuits and methods
- Patent number 11,301,212
- Issue date Apr 12, 2022
- Groq, Inc.
- Christopher Aaron Clark
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multimodal digital multiplication circuits and methods
- Patent number 10,831,445
- Issue date Nov 10, 2020
- Groq, Inc.
- Christopher Aaron Clark
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for efficient binary and ternary support in fu...
- Patent number 10,713,012
- Issue date Jul 14, 2020
- Intel Corporation
- Aditya Varma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Decimal and binary floating point arithmetic calculations
- Patent number 10,416,962
- Issue date Sep 17, 2019
- International Business Machines Corporation
- Steven R. Carlough
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data processing device and data processing method thereof
- Patent number 9,558,151
- Issue date Jan 31, 2017
- Renesas Electronics Corporation
- Kan Murata
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shared integer, floating point, polynomial, and vector multiplier
- Patent number 9,176,709
- Issue date Nov 3, 2015
- Apple Inc.
- Junji Sugisawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method to implement a matrix multiply unit of a broadban...
- Patent number 8,943,119
- Issue date Jan 27, 2015
- MicroUnity Systems Engineering, Inc.
- Craig Hansen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and processor unit for implementing a characteristic-2-multi...
- Patent number 8,732,227
- Issue date May 20, 2014
- Siemens Aktiengesellschaft
- Jean Georgiades
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiplier circuit configurable for real or complex operation
- Patent number 8,572,153
- Issue date Oct 29, 2013
- Xilinx, Inc.
- Bernard J. New
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DSP engine with implicit mixed sign operands
- Patent number 8,495,125
- Issue date Jul 23, 2013
- Microchip Technology Incorporated
- Michael I. Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and methods for determining attributes for arithmetic operat...
- Patent number 8,484,262
- Issue date Jul 9, 2013
- The MathWorks, Inc.
- Tom Bryan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reduced memory usage for digital signal processing system and method
- Patent number 8,386,543
- Issue date Feb 26, 2013
- L-3 Communications Corp.
- Johnny M. Harris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method to implement a matrix multiply unit of a broadban...
- Patent number 8,195,735
- Issue date Jun 5, 2012
- MicroUnity Systems Engineering, Inc.
- Craig Hansen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for decimal number addition using hardware for...
- Patent number 7,814,138
- Issue date Oct 12, 2010
- Intel Corporation
- Marius A. Cornea-Hasegan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High-speed integer multiplier unit handling signed and unsigned ope...
- Patent number 7,725,522
- Issue date May 25, 2010
- Texas Instruments Incorporated
- Mangesh Devidas Sadafale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Common shift-amount calculation for binary and hex floating point
- Patent number 7,716,266
- Issue date May 11, 2010
- International Business Machines Corporation
- Son Dao Trong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Polynomial and integer multiplication
- Patent number 7,447,726
- Issue date Nov 4, 2008
- ARM Limited
- Daniel Kershaw
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiplier structure supporting different precision multiplication...
- Patent number 7,433,912
- Issue date Oct 7, 2008
- Sun Microsystems, Inc.
- Paul J. Jagodik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transitive processing unit for performing complex operations
- Patent number 7,269,616
- Issue date Sep 11, 2007
- Stretch, Inc.
- Charle' R. Rupp
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Floating point unit for multiple data architectures
- Patent number 6,829,627
- Issue date Dec 7, 2004
- International Business Machines Corporation
- Christopher A. Krygowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reconfigurable inner product processor architecture implementing sq...
- Patent number 6,718,465
- Issue date Apr 6, 2004
- The Research Foundation of State University of New York
- Rong Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of performing operations with a variable arithmetic
- Patent number 6,681,236
- Issue date Jan 20, 2004
- STMicroelectronics S.A.
- David Jacquet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High speed incrementer/decrementer
- Patent number 6,665,698
- Issue date Dec 16, 2003
- Hewlett-Packard Development Company, L.P.
- Li C Tsai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instructions for arithmetic operations on vectored data
- Patent number 6,546,480
- Issue date Apr 8, 2003
- Hitachi, Ltd.
- Srinivas Mandavilli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Unaligned semaphore adder
- Patent number 6,405,233
- Issue date Jun 11, 2002
- Intel Corporation
- Gregory S. Mathews
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Double/saturate/add/saturate and double/saturate/subtract/saturate...
- Patent number 6,314,443
- Issue date Nov 6, 2001
- ARM Limited
- David James Seal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiplier circuit for multiplication operation between binary and...
- Patent number 6,151,617
- Issue date Nov 21, 2000
- STMicroelectronics S.r.l.
- Raffaele Costa
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PACKED 16 BITS INSTRUCTION PIPELINE
- Publication number 20190129718
- Publication date May 2, 2019
- Advanced Micro Devices, Inc.
- Jiasheng Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARED INTEGER, FLOATING POINT, POLYNOMIAL, AND VECTOR MULTIPLIER
- Publication number 20130138711
- Publication date May 30, 2013
- Junji Sugisawa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA PROCESSING DEVICE AND DATA PROCESSING METHOD THEREOF
- Publication number 20120265964
- Publication date Oct 18, 2012
- Renesas Electronics Corporation
- Kan MURATA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD TO IMPLEMENT A MATRIX MULTIPLY UNIT OF A BROADBAN...
- Publication number 20120215826
- Publication date Aug 23, 2012
- MicroUnity Systems Engineering, Inc.
- Craig HANSEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND PROCESSOR UNIT FOR IMPLEMENTING A CHARACTERISTIC-2-MULTI...
- Publication number 20110131395
- Publication date Jun 2, 2011
- Jean Georgiades
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DSP Engine with Implicit Mixed Sign Operands
- Publication number 20100306292
- Publication date Dec 2, 2010
- MICROCHIP TECHNOLOGY INCORPORATED
- Michael I. Catherwood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VECTOR MULTIPLICATION PROCESSING DEVICE, AND METHOD AND PROGRAM THE...
- Publication number 20100250635
- Publication date Sep 30, 2010
- TAKASHI OSADA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD TO IMPLEMENT A MATRIX MULTIPLY UNIT OF A BROADBAN...
- Publication number 20090094309
- Publication date Apr 9, 2009
- MicroUnity Systems Engineering, Inc.
- Craig HANSEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLY AND MULTIPLY AND ACCUMULATE UNIT
- Publication number 20080243976
- Publication date Oct 2, 2008
- Texas Instruments Deutschland GmbH
- Christian Wiencke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for decimal number addition using hardware for...
- Publication number 20070266073
- Publication date Nov 15, 2007
- Marius A. Cornea-Hasegan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
High-Speed Integer Multiplier Unit Handling Signed and Unsigned Ope...
- Publication number 20060253521
- Publication date Nov 9, 2006
- TEXAS INSTRUMENTS INCORPORATED
- Mangesh Devidas Sadafale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Common shift-amount calculation for binary and hex floating point
- Publication number 20060173946
- Publication date Aug 3, 2006
- International Business Machines Corporation
- Son Dao Trong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Polynomial and integer multiplication
- Publication number 20050273485
- Publication date Dec 8, 2005
- ARM Limited
- Daniel Kershaw
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Transitive processing unit for performing complex operations
- Publication number 20040186872
- Publication date Sep 23, 2004
- Charle' R. Rupp
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus for multiplication of data in two's complement and unsign...
- Publication number 20040010536
- Publication date Jan 15, 2004
- International Business Machines Corporation
- Jaime H. Moreno
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiple number representations for multiplication complexity reduc...
- Publication number 20030140079
- Publication date Jul 24, 2003
- Charles Douglas Murphy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reconfigurable arithmetic logic block array for FPGAs
- Publication number 20030055852
- Publication date Mar 20, 2003
- Mathew Francis Wojko
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Floating point unit for multiple data architectures
- Publication number 20020095451
- Publication date Jul 18, 2002
- International Business Machines Corporation
- Christopher A. Krygowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of performing operations with a variable arithmetic
- Publication number 20010004740
- Publication date Jun 21, 2001
- STMicroelctronics S.A.
- David Jacquet
- G06 - COMPUTING CALCULATING COUNTING

Devices capable of handling different types of numbers

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Packed 16 bits instruction pipeline

Method and apparatus for efficient binary and ternary support in fu...

Method and apparatus for efficient binary and ternary support in fu...

Multimodal digital multiplication circuits and methods

Multimodal digital multiplication circuits and methods

Method and apparatus for efficient binary and ternary support in fu...

Decimal and binary floating point arithmetic calculations

Data processing device and data processing method thereof

Shared integer, floating point, polynomial, and vector multiplier

System and method to implement a matrix multiply unit of a broadban...

Method and processor unit for implementing a characteristic-2-multi...

Multiplier circuit configurable for real or complex operation

DSP engine with implicit mixed sign operands

System and methods for determining attributes for arithmetic operat...

Reduced memory usage for digital signal processing system and method

System and method to implement a matrix multiply unit of a broadban...

Method and apparatus for decimal number addition using hardware for...

High-speed integer multiplier unit handling signed and unsigned ope...

Common shift-amount calculation for binary and hex floating point

Polynomial and integer multiplication

Multiplier structure supporting different precision multiplication...

Transitive processing unit for performing complex operations

Floating point unit for multiple data architectures

Reconfigurable inner product processor architecture implementing sq...

Method of performing operations with a variable arithmetic

High speed incrementer/decrementer

Instructions for arithmetic operations on vectored data

Unaligned semaphore adder

Double/saturate/add/saturate and double/saturate/subtract/saturate...

Multiplier circuit for multiplication operation between binary and...

Patents Applicationslast 30 patents

PACKED 16 BITS INSTRUCTION PIPELINE

SHARED INTEGER, FLOATING POINT, POLYNOMIAL, AND VECTOR MULTIPLIER

DATA PROCESSING DEVICE AND DATA PROCESSING METHOD THEREOF

SYSTEM AND METHOD TO IMPLEMENT A MATRIX MULTIPLY UNIT OF A BROADBAN...

METHOD AND PROCESSOR UNIT FOR IMPLEMENTING A CHARACTERISTIC-2-MULTI...

DSP Engine with Implicit Mixed Sign Operands

VECTOR MULTIPLICATION PROCESSING DEVICE, AND METHOD AND PROGRAM THE...

SYSTEM AND METHOD TO IMPLEMENT A MATRIX MULTIPLY UNIT OF A BROADBAN...

MULTIPLY AND MULTIPLY AND ACCUMULATE UNIT

Method and apparatus for decimal number addition using hardware for...

High-Speed Integer Multiplier Unit Handling Signed and Unsigned Ope...

Common shift-amount calculation for binary and hex floating point

Polynomial and integer multiplication

Transitive processing unit for performing complex operations

Apparatus for multiplication of data in two's complement and unsign...

Multiple number representations for multiplication complexity reduc...

Reconfigurable arithmetic logic block array for FPGAs

Floating point unit for multiple data architectures

Method of performing operations with a variable arithmetic