Fault tolerant

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F2217/00Indexing scheme relating to computer aided design [CAD]

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G06F2217/70Fault tolerant

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Patents Grantslast 30 patents

Information Patent Grant
Low power VLSI designs using circuit failure in sequential cells as...
- Patent number 10,522,237
- Issue date Dec 31, 2019
- Mentor Graphics Corporation
- Sanjay Pillay
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automated analog fault injection
- Patent number 10,346,273
- Issue date Jul 9, 2019
- Analog Devices Global Unlimited Company
- Courtney E. Fricano
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic link serialization in network-on-chip
- Patent number 10,331,846
- Issue date Jun 25, 2019
- ARTERIS, INC.
- Alexis Boutillier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement-driven generation of error detecting structures in integr...
- Patent number 10,325,049
- Issue date Jun 18, 2019
- International Business Machines Corporation
- Ashraf ElSharif
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for configuring a plurality of registers with sof...
- Patent number 10,001,999
- Issue date Jun 19, 2018
- Cavium, Inc.
- Anh Tran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Skeleton I/O generation for early ESD analysis
- Patent number 9,996,655
- Issue date Jun 12, 2018
- SanDisk Technologies LLC
- Anand Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Connectivity-aware layout data reduction for design verification
- Patent number 9,785,736
- Issue date Oct 10, 2017
- Mentor Graphics Corporation
- Yi-Ting Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Soft-error-rate calculating device
- Patent number 9,645,871
- Issue date May 9, 2017
- Hitachi, Ltd.
- Kenichi Shimbo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit device, safety circuit, safety-critical system a...
- Patent number 9,638,744
- Issue date May 2, 2017
- NXP USA, INC.
- Valérie Bernon-Enjalbert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable register circuitry for error detection and recovery
- Patent number 9,583,218
- Issue date Feb 28, 2017
- Altera Corporation
- Michael D. Hutton
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Simulation apparatus and simulation method for determining soft err...
- Patent number 9,507,895
- Issue date Nov 29, 2016
- Hitachi, Ltd.
- Tadanobu Toba
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single event upset mitigation for electronic design synthesis
- Patent number 9,275,179
- Issue date Mar 1, 2016
- Mentor Graphics Corporation
- Daniel Platzker
- G01 - MEASURING TESTING
Information Patent Grant
Reducing performance degradation in backup semiconductor chips
- Patent number 9,110,777
- Issue date Aug 18, 2015
- International Business Machines Corporation
- Aditya Bansal
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Visualization of tradeoffs between circuit designs
- Patent number 9,087,164
- Issue date Jul 21, 2015
- National Semiconductor Corporation
- Jeffrey R. Perry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sequential state elements radiation hardened by design
- Patent number 9,054,688
- Issue date Jun 9, 2015
- Arizona Board of Regents, a body corporate of the State of Arizona, acting fo...
- Lawrence T. Clark
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
In-place resynthesis and remapping techniques for soft error mitiga...
- Patent number 9,047,429
- Issue date Jun 2, 2015
- The Regents of the University of California
- Lei He
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Providing test coverage of integrated ECC logic en embedded memory
- Patent number 8,914,687
- Issue date Dec 16, 2014
- Advanced Micro Devices, Inc.
- Spencer M. Gold
- G11 - INFORMATION STORAGE
Information Patent Grant
Fault tree system reliability analysis system, fault tree system re...
- Patent number 8,909,991
- Issue date Dec 9, 2014
- NEC Corporation
- Jianwen Xiang
- G05 - CONTROLLING REGULATING
Information Patent Grant
Methods, systems, and apparatus for reliability synthesis
- Patent number 8,856,700
- Issue date Oct 7, 2014
- Cadence Design Systems, Inc.
- Yosinori Watanabe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single event upset mitigation for electronic design synthesis
- Patent number 8,719,747
- Issue date May 6, 2014
- Mentor Graphics Corporation
- Daniel Platzker
- G01 - MEASURING TESTING
Information Patent Grant
Method for synthesizing soft error tolerant combinational circuits
- Patent number 8,640,063
- Issue date Jan 28, 2014
- King Fahd University of Petroleum & Minerals
- Aiman Helmi El-Maleh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parity error detection verification
- Patent number 8,635,566
- Issue date Jan 21, 2014
- Advanced Micro Devices, Inc.
- Christopher E. Hsiong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Guiding design actions for complex failure modes
- Patent number 8,595,664
- Issue date Nov 26, 2013
- International Business Machines Corporation
- Anne Elizabeth Gattiker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Guiding design actions for complex failure modes
- Patent number 8,595,665
- Issue date Nov 26, 2013
- International Business Machines Corporation
- Ann Elizabeth Gattiker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Insertion of faults in logic model used in simulation
- Patent number 8,566,059
- Issue date Oct 22, 2013
- International Business Machines Corporation
- Rao H. Desineni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Preventing information leakage between components on a programmable...
- Patent number 8,356,358
- Issue date Jan 15, 2013
- Altera Corporation
- David Samuel Goldman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Duplicate design flow for mitigation of soft errors in IC operation
- Patent number 8,146,028
- Issue date Mar 27, 2012
- Xilinx, Inc.
- Austin H. Lesea
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for operational-level functional and degradati...
- Patent number 8,108,728
- Issue date Jan 31, 2012
- GM Global Technology Operations LLC
- Dipankar Das
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing susceptibility of circuit designs to single event upsets
- Patent number 8,065,644
- Issue date Nov 22, 2011
- Xilinx, Inc.
- Neil G. Jacobson
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for prediction of premature dielectric breakdown in a semico...
- Patent number 8,053,257
- Issue date Nov 8, 2011
- International Business Machines Corporation
- Kaushik Chanda
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
TAP CELLS
- Publication number 20200019666
- Publication date Jan 16, 2020
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Po-Chia Lai
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM AND METHOD FOR SELF-HEALING OF A DYNAMIC LINK
- Publication number 20190384875
- Publication date Dec 19, 2019
- Arteris, Inc
- Jonah Probell
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
3D MODEL VALIDATION AND OPTIMIZATION SYSTEM AND METHOD THEREOF
- Publication number 20190332723
- Publication date Oct 31, 2019
- Mixed Dimensions Inc.
- BAHA'ALDEEN ABUNOJAIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
3D MODEL VALIDATION AND OPTIMIZATION SYSTEM AND METHOD THEREOF
- Publication number 20190332724
- Publication date Oct 31, 2019
- Mixed Dimensions Inc.
- BAHA'ALDEEN ABUNOJAIM
- B29 - WORKING OF PLASTICS WORKING OF SUBSTANCES IN A PLASTIC STATE, IN GENERAL
Information Patent Application
PLACEMENT-DRIVEN GENERATION OF ERROR DETECTING STRUCTURES IN INTEGR...
- Publication number 20190266305
- Publication date Aug 29, 2019
- International Business Machines Corporation
- Ashraf ElSharif
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR ISOLATING FAULTS IN A RESILIENT SYSTEM
- Publication number 20190205489
- Publication date Jul 4, 2019
- Arteris, Inc
- Benoit de LESCURE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
3D Tolerance Analysis System And Methods
- Publication number 20190121925
- Publication date Apr 25, 2019
- Enventive Engineering, Inc.
- James Hurt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATED ANALOG FAULT INJECTION
- Publication number 20190095298
- Publication date Mar 28, 2019
- Analog Devices Global Unlimited Company
- Courtney E. FRICANO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
THREE-DIMENSIONAL NoC RELIABILITY EVALUATION
- Publication number 20180203963
- Publication date Jul 19, 2018
- Synopsys, Inc.
- Ashkan Eghbal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PLACEMENT-DRIVEN GENERATION OF ERROR DETECTING STRUCTURES IN INTEGR...
- Publication number 20180203968
- Publication date Jul 19, 2018
- International Business Machines Corporation
- Ashraf ElSharif
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SKELETON I/O GENERATION FOR EARLY ESD ANALYSIS
- Publication number 20170255741
- Publication date Sep 7, 2017
- SanDisk Technologies LLC
- Anand Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC LINK SERIALIZATION IN NETWORK-ON-CHIP
- Publication number 20170193142
- Publication date Jul 6, 2017
- Arteris, Inc
- Alexis Boutillier
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTER-READABLE STORAGE MEDIUM HAVING ELECTRO-STATIC DISCHARGE VE...
- Publication number 20170046472
- Publication date Feb 16, 2017
- Fujitsu Limited
- Daichi SHIMADA
- G01 - MEASURING TESTING
Information Patent Application
Single Event Upset Mitigation for Electronic Design Synthesis
- Publication number 20140289686
- Publication date Sep 25, 2014
- Mentor Graphics Corporation
- Daniel Platzker
- G01 - MEASURING TESTING
Information Patent Application
SEQUENTIAL STATE ELEMENTS RADIATION HARDENED BY DESIGN
- Publication number 20140077854
- Publication date Mar 20, 2014
- Arizona Board of Regents, a body corporated of the State of Arizona, acting f...
- Lawrence T. Clark
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAULT TREE SYSTEM RELIABILITY ANALYSIS SYSTEM, FAULT TREE SYSTEM RE...
- Publication number 20130332776
- Publication date Dec 12, 2013
- NEC Corporation
- Jianwen Xiang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IN-PLACE RESYNTHESIS AND REMAPPING TECHNIQUES FOR SOFT ERROR MITIGA...
- Publication number 20130305199
- Publication date Nov 14, 2013
- The Regents of the University of California
- Lei He
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCING PERFORMANCE DEGRADATION IN BACKUP SEMICONDUCTOR CHIPS
- Publication number 20130212414
- Publication date Aug 15, 2013
- International Business Machines Corporation
- Aditya Bansal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Single Event Upset Mitigation for Electronic Design Synthesis
- Publication number 20130198701
- Publication date Aug 1, 2013
- Daniel Platzker
- G01 - MEASURING TESTING
Information Patent Application
GUIDING DESIGN ACTIONS FOR COMPLEX FAILURE MODES
- Publication number 20130159947
- Publication date Jun 20, 2013
- International Business Machines Corporation
- Anne Elizabeth Gattiker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GUIDING DESIGN ACTIONS FOR COMPLEX FAILURE MODES
- Publication number 20130159946
- Publication date Jun 20, 2013
- International Business Machines Corporation
- Anne Elizabeth Gattiker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARITY ERROR DETECTION VERIFICATION
- Publication number 20130158973
- Publication date Jun 20, 2013
- Christopher E. Hsiong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIMULATION APPARATUS AND SIMULATION METHOD
- Publication number 20130132056
- Publication date May 23, 2013
- Tadanobu Toba
- G01 - MEASURING TESTING
Information Patent Application
Self-healing and reconfiguration in an integrated circuit
- Publication number 20130111071
- Publication date May 2, 2013
- International Business Machines Corporation
- Gerald Kreissig
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROVIDING TEST COVERAGE OF INTEGRATED ECC LOGIC EN EMBEDDED MEMORY
- Publication number 20120266033
- Publication date Oct 18, 2012
- Advanced Micro Devices, Inc.
- Spencer M. Gold
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND SYSTEMS FOR FAULT-TOLERANT POWER ANALYSIS
- Publication number 20120166168
- Publication date Jun 28, 2012
- Oracle International Corporation
- Vijay Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR OPERATIONAL-LEVEL FUNCTIONAL AND DEGRADATI...
- Publication number 20110246831
- Publication date Oct 6, 2011
- GM GLOBAL TECHNOLOGY OPERTIONS, INC.
- Dipankar Das
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSERTION OF FAULTS IN LOGIC MODEL USED IN SIMULATION
- Publication number 20110137602
- Publication date Jun 9, 2011
- International Business Machines Corporation
- Rao H. Desineni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREVENTING INFORMATION LEAKAGE BETWEEN COMPONENTS ON A PROGRAMMABLE...
- Publication number 20110138223
- Publication date Jun 9, 2011
- Altera Corporation
- David Samuel Goldman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VISUALIZATION OF TRADEOFFS BETWEEN CIRCUIT DESIGNS
- Publication number 20100325599
- Publication date Dec 23, 2010
- Jeffrey R. Perry
- G06 - COMPUTING CALCULATING COUNTING

Fault tolerant

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Low power VLSI designs using circuit failure in sequential cells as...

Automated analog fault injection

Dynamic link serialization in network-on-chip

Placement-driven generation of error detecting structures in integr...

System and method for configuring a plurality of registers with sof...

Skeleton I/O generation for early ESD analysis

Connectivity-aware layout data reduction for design verification

Soft-error-rate calculating device

Integrated circuit device, safety circuit, safety-critical system a...

Configurable register circuitry for error detection and recovery

Simulation apparatus and simulation method for determining soft err...

Single event upset mitigation for electronic design synthesis

Reducing performance degradation in backup semiconductor chips

Visualization of tradeoffs between circuit designs

Sequential state elements radiation hardened by design

In-place resynthesis and remapping techniques for soft error mitiga...

Providing test coverage of integrated ECC logic en embedded memory

Fault tree system reliability analysis system, fault tree system re...

Methods, systems, and apparatus for reliability synthesis

Single event upset mitigation for electronic design synthesis

Method for synthesizing soft error tolerant combinational circuits

Parity error detection verification

Guiding design actions for complex failure modes

Guiding design actions for complex failure modes

Insertion of faults in logic model used in simulation

Preventing information leakage between components on a programmable...

Duplicate design flow for mitigation of soft errors in IC operation

Method and apparatus for operational-level functional and degradati...

Reducing susceptibility of circuit designs to single event upsets

Method for prediction of premature dielectric breakdown in a semico...

Patents Applicationslast 30 patents

TAP CELLS

SYSTEM AND METHOD FOR SELF-HEALING OF A DYNAMIC LINK

3D MODEL VALIDATION AND OPTIMIZATION SYSTEM AND METHOD THEREOF

3D MODEL VALIDATION AND OPTIMIZATION SYSTEM AND METHOD THEREOF

PLACEMENT-DRIVEN GENERATION OF ERROR DETECTING STRUCTURES IN INTEGR...

SYSTEM AND METHOD FOR ISOLATING FAULTS IN A RESILIENT SYSTEM

3D Tolerance Analysis System And Methods

AUTOMATED ANALOG FAULT INJECTION

THREE-DIMENSIONAL NoC RELIABILITY EVALUATION

PLACEMENT-DRIVEN GENERATION OF ERROR DETECTING STRUCTURES IN INTEGR...

SKELETON I/O GENERATION FOR EARLY ESD ANALYSIS

DYNAMIC LINK SERIALIZATION IN NETWORK-ON-CHIP

COMPUTER-READABLE STORAGE MEDIUM HAVING ELECTRO-STATIC DISCHARGE VE...

Single Event Upset Mitigation for Electronic Design Synthesis

SEQUENTIAL STATE ELEMENTS RADIATION HARDENED BY DESIGN

FAULT TREE SYSTEM RELIABILITY ANALYSIS SYSTEM, FAULT TREE SYSTEM RE...

IN-PLACE RESYNTHESIS AND REMAPPING TECHNIQUES FOR SOFT ERROR MITIGA...

REDUCING PERFORMANCE DEGRADATION IN BACKUP SEMICONDUCTOR CHIPS

Single Event Upset Mitigation for Electronic Design Synthesis

GUIDING DESIGN ACTIONS FOR COMPLEX FAILURE MODES

GUIDING DESIGN ACTIONS FOR COMPLEX FAILURE MODES

PARITY ERROR DETECTION VERIFICATION

SIMULATION APPARATUS AND SIMULATION METHOD

Self-healing and reconfiguration in an integrated circuit

PROVIDING TEST COVERAGE OF INTEGRATED ECC LOGIC EN EMBEDDED MEMORY

METHODS AND SYSTEMS FOR FAULT-TOLERANT POWER ANALYSIS

METHOD AND APPARATUS FOR OPERATIONAL-LEVEL FUNCTIONAL AND DEGRADATI...

INSERTION OF FAULTS IN LOGIC MODEL USED IN SIMULATION

PREVENTING INFORMATION LEAKAGE BETWEEN COMPONENTS ON A PROGRAMMABLE...

VISUALIZATION OF TRADEOFFS BETWEEN CIRCUIT DESIGNS