Half adders Full adders consisting of two cascaded half adders

Industry

CPC
G06F7/502

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Parent Industries

GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled

Current Industry

G06F7/502Half adders Full adders consisting of two cascaded half adders

Industries

Patents Grantslast 30 patents

Information Patent Grant
Carry-lookahead adder, secure adder and method for performing carry...
- Patent number 12,124,816
- Issue date Oct 22, 2024
- Nuvoton Technology Corporation
- Kun-Yi Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual-domain combinational logic circuitry
- Patent number 11,941,369
- Issue date Mar 26, 2024
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Ternary logic circuit device
- Patent number 11,868,740
- Issue date Jan 9, 2024
- POSTECH Research and Business Development Foundation
- Seokhyeong Kang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual-domain combinational logic circuitry
- Patent number 11,481,192
- Issue date Oct 25, 2022
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable non-volatile arithmetic memory operators
- Patent number 11,354,098
- Issue date Jun 7, 2022
- SYNERGER INC.
- Lee Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiplication accumulating device and method thereof
- Patent number 11,294,632
- Issue date Apr 5, 2022
- Chung Yuan Christian University
- Shih-Hsu Huang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Unified programmable computational memory and configuration network
- Patent number 11,201,623
- Issue date Dec 14, 2021
- Xilinx, Inc.
- Rafael C. Camarota
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual-domain combinational logic circuitry
- Patent number 11,068,237
- Issue date Jul 20, 2021
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Unified programmable computational memory and configuration network
- Patent number 10,673,440
- Issue date Jun 2, 2020
- Xilinx, Inc.
- Rafael C. Camarota
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Energy-efficient variable power adder and methods of use thereof
- Patent number 10,223,071
- Issue date Mar 5, 2019
- QUALCOMM Incorporated
- Hari Rao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Binary half-adder using oscillators
- Patent number 8,928,353
- Issue date Jan 6, 2015
- Manchester Metropolitan University
- Stephen Lynch
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Null convention threshold gate
- Patent number 6,900,658
- Issue date May 31, 2005
- Theseus Logic Inc.
- Gerald E. Sobelman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asynchronous logic with intermediate value between data and null va...
- Patent number 6,333,640
- Issue date Dec 25, 2001
- Theseus Logic, Inc.
- Karl M. Fant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for enhancing noise tolerance in dynamic silic...
- Patent number 6,326,814
- Issue date Dec 4, 2001
- International Business Machines Corporation
- Daniel Lawrence Stasiak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit configuration with single-electron components, and operatin...
- Patent number 6,320,447
- Issue date Nov 20, 2001
- Infineon Technologies AG
- Wolfgang Rösner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit configuration having single-electron components, a method f...
- Patent number 6,307,422
- Issue date Oct 23, 2001
- Infineon Technologies AG
- Wolfgang Roesner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asynchronous register
- Patent number 6,052,770
- Issue date Apr 18, 2000
- Theseus Logic, Inc.
- Karl Fant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asynchronous registers with embedded acknowledge collection
- Patent number 6,031,390
- Issue date Feb 29, 2000
- Theseus Logic, Inc.
- Karl M. Fant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Look up table threshold gates
- Patent number 6,020,754
- Issue date Feb 1, 2000
- Theseus Logic, Inc.
- Gerald Edward Sobelman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Null convention register file
- Patent number 5,896,541
- Issue date Apr 20, 1999
- Theseus Logic, Inc.
- Karl M. Fant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Null convention logic system
- Patent number 5,828,228
- Issue date Oct 27, 1998
- Theseus Logic, Inc.
- Karl M. Fant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Null convention bus
- Patent number 5,796,962
- Issue date Aug 18, 1998
- Theeus Logic
- Karl M. Fant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Null convention threshold gate
- Patent number 5,664,211
- Issue date Sep 2, 1997
- Theseus Research, Inc.
- Gerald Sobelman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
NULL convention logic system
- Patent number 5,664,212
- Issue date Sep 2, 1997
- Theseus Research, Inc.
- Karl M. Fant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Null convention threshold gate
- Patent number 5,656,948
- Issue date Aug 12, 1997
- Theseus Research, Inc.
- Gerald E. Sobelman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asynchronous register for null convention logic systems
- Patent number 5,652,902
- Issue date Jul 29, 1997
- Theseus Research, Inc.
- Karl Fant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Current mode null convention threshold gate
- Patent number 5,640,105
- Issue date Jun 17, 1997
- Theseus Research, Inc.
- Gerald E. Sobelman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Null convention logic system
- Patent number 5,305,463
- Issue date Apr 19, 1994
- Theseus Research
- Karl M. Fant
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for converting a floating point signed magnitude binary numb...
- Patent number 5,272,654
- Issue date Dec 21, 1993
- Advanced Micro Devices, Inc.
- Michael A. Nix
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optical full adder
- Patent number 5,068,815
- Issue date Nov 26, 1991
- Hamamatsu Photonics K.K.
- Yoshihiko Mizushima
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MEMORY DEVICE AND OPERATING METHOD THEREOF
- Publication number 20240184526
- Publication date Jun 6, 2024
- Samsung Electronics Co., Ltd.
- Seungwoo SEO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRIPLE ADDER
- Publication number 20230266942
- Publication date Aug 24, 2023
- ARM Limited
- Javier Diaz BRUGUERA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CARRY-LOOKAHEAD ADDER, SECURE ADDER AND METHOD FOR PERFORMING CARRY...
- Publication number 20230214189
- Publication date Jul 6, 2023
- NUVOTON TECHNOLOGY CORPORATION
- Kun-Yi WU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HALF-ADDER, FULL-ADDER AND MULTIPLIER BASED ON MEMRISTOR ARRAY
- Publication number 20220374204
- Publication date Nov 24, 2022
- Zhuhai Fudan Innovation Institute
- Liang Zou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPRESSED WALLACE TREES IN FMA CIRCUITS
- Publication number 20220365751
- Publication date Nov 17, 2022
- Intel Corporation
- Aditya Varma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TERNARY LOGIC CIRCUIT DEVICE
- Publication number 20220350568
- Publication date Nov 3, 2022
- POSTECH Research and Business Development Foundation
- Seokhyeong KANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLICATION ACCUMULATING DEVICE AND METHOD THEREOF
- Publication number 20210096818
- Publication date Apr 1, 2021
- Chung Yuan Christian University
- Shih-Hsu Huang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
UNIFIED PROGRAMMABLE COMPUTATIONAL MEMORY AND CONFIGURATION NETWORK
- Publication number 20210050853
- Publication date Feb 18, 2021
- Xilinx, Inc.
- Rafael C. Camarota
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURABLE NON-VOLATILE ARITHMETIC MEMORY OPERATORS
- Publication number 20210019114
- Publication date Jan 21, 2021
- FLASHSILICON INCORPORATION
- Lee WANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Energy-Efficient Variable Power Adder and Methods of Use Thereof
- Publication number 20180300107
- Publication date Oct 18, 2018
- QUALCOMM Incorporated
- Hari Rao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BINARY HALF-ADDER USING OSCILLATORS
- Publication number 20130093458
- Publication date Apr 18, 2013
- MANCHESTER METROPOLITAN UNIVERSITY
- Stephen Lynch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW-COMPLEXITY ELECTRONIC ADDER CIRCUITS AND METHODS OF FORMING THE...
- Publication number 20100164543
- Publication date Jul 1, 2010
- Daniel R. Shepard
- G06 - COMPUTING CALCULATING COUNTING

Half adders Full adders consisting of two cascaded half adders

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Carry-lookahead adder, secure adder and method for performing carry...

Dual-domain combinational logic circuitry

Ternary logic circuit device

Dual-domain combinational logic circuitry

Configurable non-volatile arithmetic memory operators

Multiplication accumulating device and method thereof

Unified programmable computational memory and configuration network

Dual-domain combinational logic circuitry

Unified programmable computational memory and configuration network

Energy-efficient variable power adder and methods of use thereof

Binary half-adder using oscillators

Null convention threshold gate

Asynchronous logic with intermediate value between data and null va...

Method and apparatus for enhancing noise tolerance in dynamic silic...

Circuit configuration with single-electron components, and operatin...

Circuit configuration having single-electron components, a method f...

Asynchronous register

Asynchronous registers with embedded acknowledge collection

Look up table threshold gates

Null convention register file

Null convention logic system

Null convention bus

Null convention threshold gate

NULL convention logic system

Null convention threshold gate

Asynchronous register for null convention logic systems

Current mode null convention threshold gate

Null convention logic system

System for converting a floating point signed magnitude binary numb...

Optical full adder

Patents Applicationslast 30 patents

MEMORY DEVICE AND OPERATING METHOD THEREOF

TRIPLE ADDER

CARRY-LOOKAHEAD ADDER, SECURE ADDER AND METHOD FOR PERFORMING CARRY...

HALF-ADDER, FULL-ADDER AND MULTIPLIER BASED ON MEMRISTOR ARRAY

COMPRESSED WALLACE TREES IN FMA CIRCUITS

TERNARY LOGIC CIRCUIT DEVICE

MULTIPLICATION ACCUMULATING DEVICE AND METHOD THEREOF

UNIFIED PROGRAMMABLE COMPUTATIONAL MEMORY AND CONFIGURATION NETWORK

CONFIGURABLE NON-VOLATILE ARITHMETIC MEMORY OPERATORS

Energy-Efficient Variable Power Adder and Methods of Use Thereof

BINARY HALF-ADDER USING OSCILLATORS

LOW-COMPLEXITY ELECTRONIC ADDER CIRCUITS AND METHODS OF FORMING THE...