Implementation provisions of instruction buffers

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F9/00Arrangements for programme control

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G06F9/3814Implementation provisions of instruction buffers

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Implementation provisions of instruction buffers

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Disaggregated computing for distributed confidential computing envi...

Data loading and storage system and method

Disaggregated computing for distributed confidential computing envi...

Method and system for hardware-assisted pre-execution

Disaggregated computing for distributed confidential computing envi...

Disaggregated computing for distributed confidential computing envi...

Disaggregated computing for distributed confidential computing envi...

Metadata predictor

Branch prefetch mechanisms for mitigating frontend branch resteers

Schedule-aware tensor distribution module

Processor with multiple op cache pipelines

Stack pointer instruction buffer for zero-cycle loads

Disaggregated computing for distributed confidential computing envi...

Memory design for a processor

Processor with variable pre-fetch threshold

Method of converting extended instructions based on an emulation fl...

Instruction simulation device and method thereof

Speculative usage of parallel decode units

Debugging instruction register to receive and input debugging instr...

Coprocessor operation bundling

Methods and systems for nested stream prefetching for general purpo...

Fine-grained pipelining using index space mapping

Moving entries between multiple levels of a branch predictor based...

Circular queue management with split indexes

Way predictor and enable logic for instruction tightly-coupled memo...

Method and system for hard ware-assisted pre-execution

Method and system for instruction block to execution unit grouping

Circular buffer accessing device, system and method

Link stack based instruction prefetch augmentation

Method for replenishing a thread queue with a target instruction of...

Patents Applicationslast 30 patents

METHODS AND APPARATUS TO SEQUENCE BRANCH OPERATIONS

ASYNCHRONOUS BRIDGE, AND ASYNCHRONOUS PROCESSING METHOD

BRANCH PREDICTION CIRCUITRY

FETCHING BEYOND PREDICTED-TAKEN BRANCH INSTRUCTIONS IN FETCH BUNDLE...

SYSTEM AND METHOD FOR PROVIDING LOCK-FREE SELF-SERVICE QUEUE

DISAGGREGATED COMPUTING FOR DISTRIBUTED CONFIDENTIAL COMPUTING ENVI...

Schedule-Aware Tensor Distribution Module

ACCELERATING FETCH TARGET QUEUE (FTQ) PROCESSING IN A PROCESSOR

Stalling Issue Queue Entries Until Consecutive Allocated Entries ar...

DISAGGREGATED COMPUTING FOR DISTRIBUTED CONFIDENTIAL COMPUTING ENVI...

PROCESSOR ARCHITECTURE

NEURAL NETWORK PROCESSOR

DISAGGREGATED COMPUTING FOR DISTRIBUTED CONFIDENTIAL COMPUTING ENVI...

INSTRUCTION SET ARCHITECTURE FOR DATA PROCESSING ARRAY CONTROL

Coprocessor Operation Bundling

APPARATUS EMPLOYING WRAP TRACKING FOR ADDRESSING DATA OVERFLOW

INSTRUCTION CONVERSION METHOD, INSTRUCTION CONVERSION SYSTEM, AND P...

INSTRUCTION SIMULATION DEVICE AND METHOD THEREOF

FOLDED INSTRUCTION FETCH PIPELINE

PARALLEL PROCESSING ARCHITECTURE WITH SPLIT CONTROL WORD CACHES

CONTROL REGISTER SET TO FACILITATE PROCESSOR EVENT BASED SAMPLING

METHOD AND SYSTEM FOR HARDWARE-ASSISTED PRE-EXECUTION

DEVICE, METHOD, AND SYSTEM TO FACILITATE IMPROVED BANDWIDTH OF A BR...

EXECUTING MULTIPLE PROGRAMS SIMULTANEOUSLY ON A PROCESSOR CORE

SCALABLE TOGGLE POINT CONTROL CIRCUITRY FOR A CLUSTERED DECODE PIPE...

METHOD AND SYSTEM FOR HARDWARE-ASSISTED PRE-EXECUTION

METADATA PREDICTOR

PROCESSOR EMBEDDED STREAMING BUFFER

LINK STACK BASED INSTRUCTION PREFETCH AUGMENTATION

ALMOST-INDIRECT CONVOLUTION IN QUANTIZED NEURAL NETWORKS